KR20060110194A - Method for fabricating flash memory device - Google Patents

Method for fabricating flash memory device Download PDF

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KR20060110194A
KR20060110194A KR1020050032462A KR20050032462A KR20060110194A KR 20060110194 A KR20060110194 A KR 20060110194A KR 1020050032462 A KR1020050032462 A KR 1020050032462A KR 20050032462 A KR20050032462 A KR 20050032462A KR 20060110194 A KR20060110194 A KR 20060110194A
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region
drain
source
transistor
cell
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이현우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

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Abstract

A method for manufacturing a flash memory device is provided to reduce the depletion depth of a common drain region and to improve isolation punch characteristics of a cell transistor by omitting a plug implant process. A predetermined semiconductor substrate(10) is provided, wherein the predetermined semiconductor substrate includes a plurality of unit strings of a cell region and a high voltage transistor of a peripheral region. The unit string of the cell region is composed of a source select transistor with a common source region, a plurality of memory cells with cell doped regions, and a drain select transistor with a common drain region. The high voltage transistor of the peripheral region includes source and drain junction regions. An interlayer dielectric(13) is formed on the resultant structure. A plurality of contact holes for exposing the common drain region of the drain select transistor and the source/drain junction regions and a gate of the high voltage transistor to the outside are formed through the interlayer dielectric. Plugs(15) made of heavily doped polysilicon are filled in the contact holes.

Description

플래쉬 메모리 소자의 제조방법{Method for fabricating flash memory device}Manufacturing method of flash memory device {Method for fabricating flash memory device}

도 1a 내지 도 1c는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조공정 단면도1A to 1C are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

10 : 반도체 기판 11a : 셀 불순물 영역10 semiconductor substrate 11a cell impurity region

11b : 공통 드레인 영역 11c : 소오스 및 드레인 접합부11b: common drain region 11c: source and drain junction

12 : 식각 정지막 13 : 층간 절연막12 etch stop film 13 interlayer insulating film

14 : 콘택홀 15 : 플러그 14 contact hole 15 plug

본 발명은 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히 셀 트랜지스터의 소자분리 펀치(punch) 특성을 향상시키기에 적합한 플래쉬 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device suitable for improving device isolation punch characteristics of a cell transistor.

플래쉬 메모리 소자가 고집적화됨에 따라서 단위 셀(cell)의 크기가 작아지 게 되고, 소자분리영역의 폭(width)이 줄어들어 활성 영역들 사이의 거리가 감소되고 있으며, 이와 같은 소자분리영역의 폭 감소로 인하여 셀 영역에서 소자분리 펀치(punch)가 발생되고 있다.As the flash memory device is highly integrated, the unit cell becomes smaller in size, the width of the device isolation region is reduced, and the distance between the active regions is reduced. As a result, the width of the device isolation region is reduced. As a result, device isolation punches are generated in the cell region.

소자분리영역의 깊이(depth)를 증가시키면 소자분리영역의 폭(width) 감소를 보상할 수 있으나, 소자분리영역의 깊이가 증가되면 갭필(gap fill) 특성이 저하되는 문제가 발생된다.Increasing the depth of the device isolation region may compensate for the decrease in the width of the device isolation region. However, when the depth of the device isolation region is increased, a gap fill characteristic may be degraded.

또한, 드레인 플러그(drain plug)의 콘택 저항을 줄이기 위하여 플러그 임플란트(plug implant) 공정을 적용하고 있는데, 플러그 임플란트 공정시 주입된 이온에 의해 공핍 영역(depletion region)이 증가되게 되어 소자분리 펀치가 유발되고 있다.In addition, a plug implant process is applied to reduce the contact resistance of the drain plug, and the depletion region is increased by the ions implanted during the plug implant process, causing device isolation punches. It is becoming.

본 발명은 전술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로써, 셀 트랜지스터의 소자분리 펀치 특성을 개선할 수 있는 플래쉬 메모리 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a method of manufacturing a flash memory device capable of improving device isolation punch characteristics of a cell transistor.

본 발명의 다른 목적은 소자의 디스터브(disturb) 및 리퀴지(leakage) 특성을 향상시키는데 있다.Another object of the present invention is to improve the disturb and leakage characteristics of the device.

본 발명에 따른 플래쉬 메모리 소자의 제조방법은 셀 영역에는 공통 소오스 영역을 갖는 소오스 선택 트랜지스터와 셀 불순물 영역을 갖는 복수개의 메모리 셀들 및 공통 드레인 영역을 갖는 드레인 선택 트랜지스터가 직렬로 연결된 구조의 단위 스트링이 복수 개 형성되고, 주변회로 영역에는 소오스 및 드레인 접합부를 갖는 고전압 트랜지스터가 형성된 반도체 기판이 제공되는 단계와, 상기 결과물이 형성된 반도체 기판상에 층간 절연막을 형성하는 단계와, 상기 드레인 선택 트랜지스터의 공통 드레인 영역과 상기 고전압 트랜지스터의 소오스 및 드레인 접합부 그리고 게이트를 노출하는 콘택홀들을 형성하는 단계와, 상기 콘택홀들에 일정 농도로 도핑된 폴리실리콘을 매립하여 플러그들을 형성하는 단계를 포함한다.A method of manufacturing a flash memory device according to the present invention includes a unit string having a structure in which a source selection transistor having a common source region, a plurality of memory cells having a cell impurity region, and a drain selection transistor having a common drain region are connected in series. A plurality of semiconductor substrates are provided, the semiconductor substrate having a high voltage transistor having source and drain junctions formed in a peripheral circuit region, forming an interlayer insulating layer on the resultant semiconductor substrate, and a common drain of the drain selection transistor. Forming contact holes exposing a region, a source and drain junction of the high voltage transistor, and a gate; and filling the contact holes with polysilicon doped at a predetermined concentration to form plugs.

바람직하게, 상기 일정 농도는 5.0E20~3.0E121ions/㎠인 것을 특징으로 한다.Preferably, the predetermined concentration is characterized in that 5.0E20 ~ 3.0E121ions / ㎠.

바람직하게, 상기 플러그들을 형성한 이후에 상기 플러그들에 도핑된 이온을 확산시키어 상기 플러그 하부의 반도체 기판내에 오믹 콘택을 형성하는 단계를 더 포함하는 것을 특징으로 한다.The method may further include forming an ohmic contact in the semiconductor substrate under the plug by diffusing ions doped into the plugs after forming the plugs.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조공 정 단면도이다.1A to 1C are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

먼저, 반도체 기판(10)의 소정영역에 서로 평행한 복수개의 소자분리막(미도시)들을 형성하여 활성영역을 한정(define)한다. 소자분리막들은 로코스(LOCOS; local oxidation of silicon) 공정 또는 트렌치 소자 분리 공정으로 형성하며, 최근에는 소자의 고집적화를 위해 트렌치 소자 분리 공정을 많이 적용하고 있다. First, a plurality of device isolation layers (not shown) parallel to each other are formed in a predetermined region of the semiconductor substrate 10 to define an active region. The device isolation layers are formed by a local oxidation of silicon (LOCOS) process or a trench device isolation process, and recently, many trench device isolation processes are applied for high integration of devices.

낸드 플래쉬 메모리 소자는 도 1a에 도시하는 바와 같이 셀 영역과 주변회로 영역으로 크게 구분 지을 수 있으며, 상기 주변회로 영역에는 고전압 소자 및 저전압 소자가 형성된다.As shown in FIG. 1A, a NAND flash memory device can be roughly divided into a cell area and a peripheral circuit area, and a high voltage device and a low voltage device are formed in the peripheral circuit area.

셀 영역은 복수개의 스트링으로 구성되며, 각 스트링에는 소오스 선택 트랜지스터(미도시), 복수개의 메모리 셀들(MC1,…, MCn) 및 드레인 선택 트랜지스터(DSL)가 직렬로 연결되어 형성된다. 주변회로 영역은 PMOS 트랜지스터와 NMOS 트랜지스터 등의 주변 트랜지스터(PT)가 형성된다. 상기 소오스 선택 트랜지스터는 공통 소오스 영역을 갖고, 복수개의 메모리 셀들(MC1,…, MCn)은 셀 불순물 영역(11a)을 가지며, 드레인 선택 트랜지스터(DSL)는 공통 드레인 영역(11b)을 가지며, 주변 트랜지스터(PT)는 소오스 및 드레인 접합부(11c)를 가진다. The cell region is composed of a plurality of strings, and a source select transistor (not shown), a plurality of memory cells MC1,..., MCn, and a drain select transistor DSL are connected in series to each string. In the peripheral circuit region, peripheral transistors PT such as a PMOS transistor and an NMOS transistor are formed. The source select transistor has a common source region, the plurality of memory cells MC1,..., MCn have a cell impurity region 11a, the drain select transistor DSL has a common drain region 11b, and a peripheral transistor. PT has a source and drain junction 11c.

이러한 결과물의 전체 구조상에 식각 정지막(12)을 형성한다.An etch stop film 12 is formed on the overall structure of the resultant product.

그런 다음, 도 1b에 도시하는 바와 같이 상기 식각 정지막(12)이 형성된 결과물 전체 구조상에 층간 절연막(13)을 형성한다.Then, as shown in FIG. 1B, the interlayer insulating film 13 is formed on the entire structure of the resultant product in which the etch stop film 12 is formed.

이어, 사진 식각 공정으로 상기 층간 절연막(13) 및 식각 정지막(12)을 선택적으로 제거하여 상기 드레인 선택 트랜지스터(DSL)의 공통 드레인 영역(11b)과 주 변 트랜지스터(PT)의 소오스 및 드레인 접합부(11c) 그리고, 게이트를 노출하는 콘택홀(14)들을 형성한다. Subsequently, the interlayer insulating layer 13 and the etch stop layer 12 are selectively removed by a photolithography process, so that the source and drain junctions of the common drain region 11b of the drain select transistor DSL and the peripheral transistor PT are formed. 11c, contact holes 14 exposing the gate are formed.

종래 기술에서는 주변회로 영역에 형성되는 고전압 소자의 콘택 저항(Rc)을 줄이기 위하여 드레인 선택 트랜지스터(DSL)의 공통 드레인 영역과 주변 트랜지스터(PT)의 소오스 및 드레인 접합부 그리고 게이트를 노출하는 콘택홀들을 형성한 다음에 플러그 임플란트(plug implant) 공정을 실시하여 콘택홀 하부의 반도체 기판내에 오믹 콘택(ohmic contact)층을 형성하였다.In the related art, the common drain region of the drain select transistor DSL, the source and drain junctions of the peripheral transistor PT, and the contact holes exposing the gate are formed to reduce the contact resistance Rc of the high voltage device formed in the peripheral circuit region. Then, a plug implant process was performed to form an ohmic contact layer in the semiconductor substrate under the contact hole.

그러나, 상기 플러그 임플란트 공정시 공통 드레인 영역에 주입된 이온이 공핍 영역을 증가시켜 소자분리 펀치(punch)를 유발하는 원인이 되는 바, 본 발명에서는 플러그 임플란트 공정을 생략(skip)한다.However, since the ions implanted into the common drain region during the plug implant process increase the depletion region and cause a device isolation punch, the plug implant process is omitted in the present invention.

그리고, 플러그 임플란트 공정 생략에 따른 고전압 소자의 콘택 저항 증가 문제를 해결하기 위하여 콘택홀들에 매립하는 폴리실리콘의 도핑 농도를 증가시키고, 후속 열공정시 폴리실리콘에 도핑된 이온을 반도체 기판내로 확산시키어 오믹 콘택을 형성한다. In order to solve the problem of increasing the contact resistance of the high-voltage device due to the omission of the plug implant process, the doping concentration of the polysilicon embedded in the contact holes is increased, and the ion doped in the polysilicon is diffused into the semiconductor substrate during the subsequent thermal process. Form a contact.

즉, 도 1c에 도시하는 바와 같이, 상기 콘택홀(14)들이 형성된 결과물 전체 구조상에 5.0E20~3.0E21ions/㎠의 도핑 레벨을 갖는 폴리실리콘막을 상기 콘택홀(14)들이 완전히 매립되도록 증착한다.That is, as illustrated in FIG. 1C, a polysilicon film having a doping level of 5.0E20 to 3.0E21ions / cm 2 is deposited on the entire structure of the resultant contact hole 14 so that the contact holes 14 are completely embedded.

그런 다음, 상기 층간절연막(13)이 노출되도록 상기 폴리실리콘막을 CMP(Chemical Mechanical Polishing) 또는 에치백(etch back)하여 상기 콘택홀(14)들내에 플러그(15)들을 형성한다. Then, the polysilicon layer is chemically mechanical polished (CMP) or etched back to expose the interlayer insulating layer 13 to form plugs 15 in the contact holes 14.

이후, 도면으로 도시하지는 않았지만 이후에 실시하는 열공정시 상기 플러그(15)내의 도핑된 이온들을 반도체 기판(10)내로 확산시키어 상기 플러그(15) 하부의 반도체 기판(10)내에 오믹 콘택층(미도시)을 형성한다.Subsequently, although not illustrated in the drawings, in the subsequent thermal process, doped ions in the plug 15 are diffused into the semiconductor substrate 10 to form an ohmic contact layer (not shown) in the semiconductor substrate 10 under the plug 15. ).

이로써, 본 발명에 따른 플래쉬 메모리 소자 제조를 완료한다.This completes the manufacture of the flash memory device according to the present invention.

상술한 바와 같이, 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 플러그 임플란트 공정을 생략하여 공통 드레인 영역의 공핍 깊이를 줄일 수 있으므로 셀 트랜지스터의 소자분리 펀치(punch) 특성을 개선할 수 있다.First, since the depletion depth of the common drain region may be reduced by omitting the plug implant process, device isolation punch characteristics of the cell transistor may be improved.

둘째, 소자분리 펀치 특성이 개선되므로 소자의 디스터브(disturb) 및 누설(leakage) 특성을 향상시킬 수 있다. Second, since the device isolation punch characteristic is improved, the disturb and leakage characteristics of the device may be improved.

셋째, 콘택홀을 매립하는 폴리실리콘의 농도를 높이어 후속 열공정시 고전압 소자의 오믹 콘택 형성이 가능하므로 고전압 트랜지스터의 콘택 저항을 줄일 수 있다.Third, the ohmic contact of the high voltage device may be formed during the subsequent thermal process by increasing the concentration of the polysilicon filling the contact hole, thereby reducing the contact resistance of the high voltage transistor.

Claims (3)

셀 영역에는 공통 소오스 영역을 갖는 소오스 선택 트랜지스터와 셀 불순물 영역을 갖는 복수개의 메모리 셀들 및 공통 드레인 영역을 갖는 드레인 선택 트랜지스터가 직렬로 연결된 구조의 단위 스트링이 복수 개 형성되고, 주변회로 영역에는 소오스 및 드레인 접합부를 갖는 고전압 트랜지스터가 형성된 반도체 기판이 제공되는 단계;In the cell region, a plurality of unit strings having a structure in which a source select transistor having a common source region, a plurality of memory cells having a cell impurity region, and a drain select transistor having a common drain region are connected in series are formed, and a source and Providing a semiconductor substrate on which a high voltage transistor having a drain junction is formed; 상기 결과물이 형성된 반도체 기판상에 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on the resultant semiconductor substrate; 상기 드레인 선택 트랜지스터의 공통 드레인 영역과 상기 고전압 트랜지스터의 소오스 및 드레인 접합부 그리고 게이트를 노출하는 콘택홀들을 형성하는 단계; 및Forming contact holes exposing a common drain region of the drain select transistor, a source and drain junction of the high voltage transistor, and a gate; And 상기 콘택홀들에 일정 농도로 도핑된 폴리실리콘을 매립하여 플러그들을 형성하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법.And embedding polysilicon doped at a predetermined concentration in the contact holes to form plugs. 제 1항에 있어서, The method of claim 1, 상기 일정 농도는 5.0E20~3.0E121ions/㎠인 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.The predetermined concentration is a method of manufacturing a flash memory device, characterized in that 5.0E20 ~ 3.0E121ions / ㎠. 제 1항에 있어서,The method of claim 1, 상기 플러그들을 형성한 이후에 상기 플러그들에 도핑된 이온을 확산시키어 상기 플러그 하부의 반도체 기판내에 오믹 콘택을 형성하는 단계를 더 포함하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.And forming an ohmic contact in the semiconductor substrate under the plug by diffusing ions doped into the plugs after forming the plugs.
KR1020050032462A 2005-04-19 2005-04-19 Method for fabricating flash memory device KR20060110194A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801391B1 (en) * 2006-01-23 2008-02-05 가부시끼가이샤 도시바 Nonvolatile semiconductor storage device
US9082865B2 (en) 2012-03-13 2015-07-14 Samsung Electronics Co., Ltd. Split-gate type nonvolatile memory device, semiconductor device having split-type nonvolatile memory device embedded therein, and methods of forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801391B1 (en) * 2006-01-23 2008-02-05 가부시끼가이샤 도시바 Nonvolatile semiconductor storage device
US9082865B2 (en) 2012-03-13 2015-07-14 Samsung Electronics Co., Ltd. Split-gate type nonvolatile memory device, semiconductor device having split-type nonvolatile memory device embedded therein, and methods of forming the same

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