JP2018029178A - パワー半導体デバイスおよびこのようなパワー半導体デバイスの製造方法 - Google Patents
パワー半導体デバイスおよびこのようなパワー半導体デバイスの製造方法 Download PDFInfo
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- JP2018029178A JP2018029178A JP2017155472A JP2017155472A JP2018029178A JP 2018029178 A JP2018029178 A JP 2018029178A JP 2017155472 A JP2017155472 A JP 2017155472A JP 2017155472 A JP2017155472 A JP 2017155472A JP 2018029178 A JP2018029178 A JP 2018029178A
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Abstract
Description
技術分野
本発明は、パワーエレクトロニクスの分野に関し、より特定的には請求項1に係るパワー半導体デバイスおよび請求項8に係るこのようなパワー半導体デバイスの製造方法に関する。
パワー半導体デバイスは、電界が主接点のエッジに集中することにより比較的低い絶縁破壊電圧(VBR)でデバイスの絶縁破壊が生じることを回避するために、効率的なエッジ終端を必要とする。pinダイオードまたは絶縁ゲートバイポーラトランジスタ(IGBT)などの一般的なパワー半導体デバイスは、通常、理想的な一次元ダイオード絶縁破壊電圧の80〜90%の範囲内の絶縁破壊電圧を実現するために平面的なエッジ終端部を有する。公知の平面エッジ終端技術としては、接合終端拡張部(junction termination extension:JTE)、横方向ドーピング変化(variation of lateral doping:VLD)層、およびフィールドプレート拡張部を有していたり有していなかったりするフローティングフィールドリング終端部(floating field ring:FFR)が挙げられる。別のタイプのエッジ終端構造は、ベベル終端構造である。ベベリングによって、横型p−n接合部とウェハの表面との間に規定の角度が形成され、それによってエッジは高電界から解放される。
本発明の目的は、高湿度において頑強でありかつ長期信頼性を有する、パッシベーション層構造を有するパワー半導体デバイスを提供することである。
本発明の半導体デバイスでは、シリコンまたは炭化ケイ素のようなワイドバンドギャップ材料でできていてもよい半導体ウェハが設けられる。まず、半絶縁層がウェハ上に配置され、続いて、基板を化学的および機械的に保護する窒化シリコン層が配置される。窒化シリコン層は、非ドープシリケートガラス層に付着し、それによって非ドープシリケートガラス層によって被覆され、その上に有機誘電体層が付着する。
例示的な実施形態において、シリケートガラス層は、少なくとも0.4μmまたは少なくとも0.5μmの層厚みを有する。シリケートガラス層の阻止機能は、厚みが増すとともに向上する。0.4μmを上回る厚みで、シリケートガラス層は湿気を効率的に阻止することができる。
図1には、本発明のパワー半導体デバイスの実施形態として終端構造が示されている。半導体ウェハWは、例示的には、SiCでできている。半導体ウェハWは、第1の主要側2と、第1の主要側の面に平行な、横方向に延在する第2の主要側3とを有する。半導体ウェハWは、活性領域ARと、活性領域ARを側方から取囲む終端領域TRとを有する。活性領域は、電界が活性に制御される領域であるのに対して、終端領域では、電界はデバイスのエッジに向かって減少する。
Claims (14)
- パワー半導体デバイスであって、前記パワー半導体デバイスは、ウェハを備え、
前記デバイスの終端領域において、前記ウェハの面の少なくとも一部にパッシベーション層構造が形成され、
前記パッシベーション層構造は、前記ウェハの前記面から、前記ウェハから離れる方向に、半絶縁層(13)と、窒化シリコン層と、非ドープシリケートガラス層(16)と、有機誘電体層(17)とをこの順序で備え、
前記窒化シリコン層は、少なくとも0.5μmの層厚みを有し、前記有機誘電体層(17)は、前記非ドープシリケートガラス層(16)に付着し、前記非ドープシリケートガラス層(16)は、前記窒化シリコン層に付着することを特徴とする、パワー半導体デバイス。 - 前記窒化シリコン層は、少なくとも0.7μmまたは少なくとも0.9μmの層厚みを有する、請求項1に記載のパワー半導体デバイス。
- 前記窒化シリコン層は、せいぜい2.0μmの層厚みを有する、請求項1または2に記載のパワー半導体デバイス。
- 前記非ドープシリケートガラス層(16)は、少なくとも0.4μmまたは少なくとも0.5μmの層厚みを有する、請求項1〜3のいずれか1項に記載のパワー半導体デバイス。
- 前記有機誘電体層(17)は、ポリイミド層、ポリベンゾオキサゾール層およびシリコーン層のうちの少なくとも1つを含む、請求項1〜4のいずれか1項に記載のパワー半導体デバイス。
- 前記半絶縁層(13)は、半絶縁性多結晶シリコン層、アモルファスシリコン層、アモルファス窒化シリコンまたはダイヤモンド状炭素層である、請求項1〜5のいずれか1項に記載のパワー半導体デバイス。
- 前記ウェハは、シリコンまたはワイドバンドギャップ材料または炭化ケイ素でできている、請求項1〜6のいずれか1項に記載のパワー半導体デバイス。
- パワー半導体デバイスの製造方法であって、前記パワー半導体デバイスは、請求項1〜7のいずれか1項に記載のデバイスであり、前記方法は、
ウェハを設けるステップと、
前記デバイスの終端領域において、前記ウェハの面の少なくとも一部にパッシベーション層構造を形成するステップとを備え、前記パッシベーション層構造を形成するステップは、半絶縁層(13)を形成するステップと、前記半絶縁層(13)の上に窒化シリコン層を形成するステップと、前記窒化シリコン層の上に非ドープシリケートガラス層(16)を形成するステップと、前記非ドープシリケートガラス層(16)の上に有機誘電体層(17)を形成するステップとを含み、前記窒化シリコン層は、少なくとも0.5μmの層厚みを有し、前記有機誘電体層(17)は、前記非ドープシリケートガラス層(16)に付着し、前記非ドープシリケートガラス層(16)は、前記窒化シリコン層に付着することを特徴とする、方法。 - 前記窒化シリコン層を形成するステップは、600℃を上回る温度で第1の窒化シリコン層(14)を形成する第1のステップと、425℃を下回る温度で第2の窒化シリコン層(15)を形成する第2のステップとを含む、請求項8に記載の方法。
- 低圧化学蒸着によって前記第1の窒化シリコン層(14)を形成する、請求項9に記載の方法。
- プラズマ強化化学蒸着によって前記第2の窒化シリコン層(15)を形成する、請求項9または10に記載の方法。
- 少なくとも0.5μmまたは少なくとも0.7μmまたは少なくとも0.9μmの層厚みを有する前記第2の窒化シリコン層を形成する、請求項9〜11のいずれか1項に記載の方法。
- 425℃を下回る温度でプラズマ強化化学蒸着によって前記非ドープシリケートガラス層(16)を形成する、請求項8〜12のいずれか1項に記載の方法。
- 同一のマスキング層を使用して前記窒化シリコン層および前記非ドープシリケートガラス層(16)を選択的にエッチングする、請求項8〜12のいずれか1項に記載の方法。
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