JP2017535075A5 - - Google Patents

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Publication number
JP2017535075A5
JP2017535075A5 JP2017520461A JP2017520461A JP2017535075A5 JP 2017535075 A5 JP2017535075 A5 JP 2017535075A5 JP 2017520461 A JP2017520461 A JP 2017520461A JP 2017520461 A JP2017520461 A JP 2017520461A JP 2017535075 A5 JP2017535075 A5 JP 2017535075A5
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JP
Japan
Prior art keywords
oxide
etching
depositing
silicon substrate
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017520461A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017535075A (ja
Filing date
Publication date
Priority claimed from US14/525,543 external-priority patent/US9589828B2/en
Application filed filed Critical
Publication of JP2017535075A publication Critical patent/JP2017535075A/ja
Publication of JP2017535075A5 publication Critical patent/JP2017535075A5/ja
Pending legal-status Critical Current

Links

JP2017520461A 2014-10-28 2015-10-27 フォトリソグラフィを用いない自己整合逆活性エッチングのための方法 Pending JP2017535075A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/525,543 US9589828B2 (en) 2014-10-28 2014-10-28 Method for photolithography-free self-aligned reverse active etch
US14/525,543 2014-10-28
PCT/US2015/057469 WO2016069531A1 (en) 2014-10-28 2015-10-27 A method for photolithography-free self-aligned reverse active etch

Publications (2)

Publication Number Publication Date
JP2017535075A JP2017535075A (ja) 2017-11-24
JP2017535075A5 true JP2017535075A5 (https=) 2018-11-22

Family

ID=54477334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017520461A Pending JP2017535075A (ja) 2014-10-28 2015-10-27 フォトリソグラフィを用いない自己整合逆活性エッチングのための方法

Country Status (8)

Country Link
US (1) US9589828B2 (https=)
EP (1) EP3213343B1 (https=)
JP (1) JP2017535075A (https=)
KR (1) KR20170075716A (https=)
CN (1) CN107078022B (https=)
SG (1) SG11201702042YA (https=)
TW (1) TW201631650A (https=)
WO (1) WO2016069531A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019169581A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体装置の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6395620B1 (en) 1996-10-08 2002-05-28 Micron Technology, Inc. Method for forming a planar surface over low density field areas on a semiconductor wafer
US5874345A (en) 1996-11-18 1999-02-23 International Business Machines Corporation Method for planarizing TEOS SiO2 filled shallow isolation trenches
US5728621A (en) 1997-04-28 1998-03-17 Chartered Semiconductor Manufacturing Pte Ltd Method for shallow trench isolation
US5976982A (en) * 1997-06-27 1999-11-02 Siemens Aktiengesellschaft Methods for protecting device components from chemical mechanical polish induced defects
US6146975A (en) * 1998-07-10 2000-11-14 Lucent Technologies Inc. Shallow trench isolation
TW413883B (en) * 1999-02-26 2000-12-01 Vanguard Int Semiconduct Corp Method for using nitride hard mask for local reversed back-etching and CMP to solve the dishing effect encountered during CMP plantarization process
US6444581B1 (en) 1999-07-15 2002-09-03 International Business Machines Corporation AB etch endpoint by ABFILL compensation
US6391781B1 (en) 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
TW436975B (en) * 2000-03-23 2001-05-28 United Microelectronics Corp Shallow trench isolation process
US6593208B1 (en) * 2001-02-14 2003-07-15 Cypress Semiconductor Corp. Method of uniform polish in shallow trench isolation process
US6617251B1 (en) * 2001-06-19 2003-09-09 Lsi Logic Corporation Method of shallow trench isolation formation and planarization
US6638866B1 (en) * 2001-10-18 2003-10-28 Taiwan Semiconductor Manufacturing Company Chemical-mechanical polishing (CMP) process for shallow trench isolation
US8426300B2 (en) * 2010-12-02 2013-04-23 International Business Machines Corporation Self-aligned contact for replacement gate devices

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