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  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
  • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
  • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
  • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
  • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
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  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
  • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/694—Inorganic materials composed of nitrides
  • H10P14/6943—Inorganic materials composed of nitrides containing silicon
  • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
  • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
  • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/60—Wet etching
  • H10P50/64—Wet etching of semiconductor materials
  • H10P50/642—Chemical etching
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/06—Planarisation of inorganic insulating materials
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  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/06—Planarisation of inorganic insulating materials
  • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
• • H—ELECTRICITY
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/06—Planarisation of inorganic insulating materials
  • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
  • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
  • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

• the present disclosure relates to fabrication of semiconductor integrated circuits, and more particularly, to a method of fabricating semiconductor integrated circuits using photolithography-free self-aligned reverse active etch.
• HDP high density plasma
• a method for photolithography-free self-aligned reverse active etch of a semiconductor wafer may comprise the steps of: depositing a pad oxide on a silicon substrate of a semiconductor wafer; depositing an active silicon nitride on the pad oxide; forming shallow trench isolation (STI) wells in the silicon substrate; forming an oxidization liner in the STI wells, wherein the oxidization liner may be only formed where the silicon substrate may be exposed; depositing an oxide over the silicon nitride and the STI wells; depositing a partially planarized organosilicate (DUO) layer over the oxide; performing a dry plasma etch to remove the DUO layer from the oxide; performing a chemical-mechanical polish (CMP) to remove all of the oxide covering the active silicon nitride; and removing the active silicon nitride, wherein portions of the silicon substrate may be exposed between the remaining oxide and ready for the step of active transistor element doping in the silicon substrate
• STI shallow trench isolation
• the pad oxide may be silicon nitride.
• the step of forming STI wells may comprise the step of etching the silicon substrate to form the STI wells.
• the oxidization liner may be silicon oxide.
• the step of depositing an oxide over the oxidation liner may comprise the step of depositing a high density plasma (HDP) oxide over the oxidation liner.
• the step of depositing the DUO layer over the oxide may comprise the step of spin-coating the DUO layer onto the oxide.
• the step of removing the DUO layer from the oxide may comprise the steps of doing a tuned etch to open the DUO layer, and etching a short selective etch to the DUO layer, wherein the semiconductor wafer may be etched in an oxide etcher.
• the step of removing the DUO layer from the oxide may comprise the steps of multiple dry plasma etching.
• the steps of multiple dry plasma etching may comprise the steps of etching non-selective to oxide and etching partial to oxide.
• the step of etching non-selective to oxide may use gases selected from the group consisting of CF 4 , 0 2 , and Ar.
• the step of etching partial to oxide may use gases selected from the group consisting of C5F8, O2, N 2 , and Ar.
• the step of removing the DUO layer from the oxide may be performed until the step of performing the dry plasma etch may be completed.
• a semiconductor integrated circuit prepared by a process may comprise the steps of: depositing a pad oxide on a silicon substrate of a semiconductor wafer; depositing an active silicon nitride on the pad oxide; forming shallow trench isolation (STI) wells in the silicon substrate; forming an oxidization liner in the STI wells, wherein the oxidization liner may only be formed where the silicon substrate may be exposed; depositing an oxide over the silicon nitride and the STI wells; depositing a partially planarized organosilicate (DUO) layer over the oxide; performing a dry plasma etch to remove the DUO layer from the oxide; performing a chemical-mechanical polish (CMP) to remove all of the oxide covering the active silicon nitride; and removing the active silicon nitride, wherein portions of the silicon substrate may be exposed between the remaining oxide and ready for the step of active transistor element doping in the silicon substrate.
• STI shallow trench isolation
• the step of depositing an oxide over the oxidation liner may comprise the step of depositing a high density plasma (HDP) oxide over the oxidation liner.
• the step of removing the DUO layer from the oxide may comprise the steps of doing a tuned etch to open the DUO layer, and etching a short selective etch to the DUO layer, wherein the semiconductor wafer may be etched in an oxide etcher.
• the step of removing the DUO layer from the oxide may comprise the steps of multiple-step dry plasma etching.
• the steps of multiple-step dry plasma etching may comprise the steps of etching non-selective to oxide and etching partial to oxide.
• the step of etching non-selective to oxide may use gases selected from the group consisting of CF 4 , 0 2 , and Ar.
• the step of etching partial to oxide may use gases selected from the group consisting of C5F8, O2, N 2 , and Ar.
• a semiconductor wafer may have a surface treated in accordance with the steps of: depositing a pad oxide on a silicon substrate of a semiconductor wafer; depositing an active silicon nitride on the pad oxide; forming shallow trench isolation (STI) wells in the silicon substrate; forming an oxidization liner in the STI wells, wherein the oxidization liner may only be formed where the silicon substrate may be exposed; depositing an oxide over the silicon nitride and the STI wells; depositing a partially planarized organosilicate (DUO) layer over the oxide; performing a dry plasma etch to remove the DUO layer from the oxide; performing a chemical-mechanical polish (CMP) to remove all of the oxide covering the active silicon nitride; and removing the active silicon nitride, wherein portions of the silicon substrate may be exposed between the remaining oxide and ready for the step of active transistor element doping in the silicon substrate.
• STI shallow trench isolation
• Figure 1 illustrates a schematic flow diagram of prior art process fabrication steps used to form field oxides and expose a silicon substrate for further processing of active transistor element doping in the silicon substrate;
• Figure 2 illustrates a schematic flow diagram of process fabrication steps used to form field oxides and expose a silicon substrate for further processing of active transistor element doping in the silicon substrate, according to a specific example embodiment
• Figure 3 illustrates a schematic elevational cross-section of a silicon wafer having a thin layer of oxide and a layer of silicon nitride deposited thereon, according to the teachings of this disclosure
• Figure 3A illustrates a schematic elevational cross-section of a silicon wafer after the step of shallow trench isolation (STI) etch of the silicon wafer shown in Figure 3;
• STI shallow trench isolation
• Figure 3B illustrates a schematic elevational cross-section of a silicon wafer after performing the process steps of shallow trench isolation (STI) etch, liner oxidation and high- density plasma (HDP) deposition of the silicon wafer shown in Figures 3 and 3 A;
• STI shallow trench isolation
• HDP high- density plasma
• Figure 4 illustrates a schematic elevational cross-section of the silicon wafer after performing the process step of spin-coating a layer of partially planarized organosilicate (DUO) onto the silicon wafer shown in Figure 3, according to a specific example embodiment of this disclosure;
• DAO partially planarized organosilicate
• Figure 5 illustrates a schematic elevational cross-section of the silicon wafer after performing the process step of etching the DUO on the silicon wafer shown in Figure 4, according to a specific example embodiment of this disclosure
• Figure 6 illustrates a schematic elevational cross-section of the silicon wafer after performing the process step of removing the DUO on the silicon wafer shown in Figure 5, according to a specific example embodiment of this disclosure
• Figure 7 illustrates a schematic elevational cross-section of the silicon wafer after performing the process step of shallow trench isolation (STI) chemical mechanical polishing (CMP), according to a specific example embodiment of this disclosure.
• STI shallow trench isolation
• CMP chemical mechanical polishing
• Figure 8 illustrates a schematic elevational cross-section of the silicon wafer after performing the process step of removing the silicon nitride to expose portions of the silicon substrate, according to a specific example embodiment of this disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims. DETAILED DESCRIPTION
• a layer of partially planarized organosilicate (DUO) is spin-coated onto the wafers after the shallow trench isolation (STI) fill. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity.
• the higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is achieved.
• a prior art front-end- of-line (FEOL) process fabrication to produce a silicon wafer with shallow trench isolation (STI) field oxide (FOX) wells and ready for active transistor element doping in the silicon substrate may comprise the following steps.
• step 102 after a silicon wafer 320 has a thin layer of oxide 321 and a layer of silicon nitride 322 deposited thereon, the surface of the silicon wafer is patterned and etched to produce shallow trench isolation (STI) wells.
• STI shallow trench isolation
• step 104 the surface of a silicon wafer and the STI wells are oxidized to produce a liner thereon.
• step 106 a high density plasma (HDP) oxide is deposed on the oxidized liner.
• step 108 a reverse active mask is performed.
• step 110 a reverse active etch is performed.
• step 112 a reverse active ash (0 2 ) is performed.
• step 114 a reverse acid strip on the silicon wafer is performed.
• step 116 a shallow trench isolation (STI) chemical mechanical polish (CMP) is performed on the surface of the silicon wafer.
• step 118 a top oxide etch is performed.
• step 120 a nitride strip of the silicon wafer is preformed, leaving field oxides in the STI wells and exposed portions of the silicon wafer ready for the step of active transistor element doping in the silicon wafer substrate.
• STI shallow trench isolation
• CMP chemical mechanical polish
• a new, novel and non-obvious front-end-of-line (FEOL) process fabrication to produce a silicon wafer with shallow trench isolation (STI) field oxide (FOX) wells and ready for active transistor element doping in the silicon substrate may comprise the following steps. Steps 102, 104 and 106 are substantially the same as described in Figure 1 above. Also refer to Figures 3-8 showing element numbers referenced hereinafter.
• STI shallow trench isolation
• step 208 is performed, by coating a partially planarizing organosilicate (DUO) 426 that is deposited onto the high density plasma (HDP) oxide 324.
• the DUO 426 may be etched with, for example is but is not limited to, a multiple step dry-plasma etch using common process gases, e.g., CF 4 , C 4 F 6 , C 5 F 8 , C 4 F 8 , 0 2 , N 2 , Ar, etc.
• the first sub-step 210a may be non-selective-to-oxide (CF 4 , O2, Ar) and the second sub-step 210b may be partial-to-oxide (C 5 F 8 , O2, N 2 , Ar).
• the DUO 426 is striped off of all remaining areas silicon nitride using, for example but is not limited to, an oxidizing ash (O2) and an HF strip, respectively.
• O2 oxidizing ash
• the profile of the remaining HDP 324 after etch and DUO removal is similar to the conventional reverse-mask process.
• the wafer may then go through CMP, TOP OXIDE ETCH, and NITRIDE STRIP just like what is done in other present technology semiconductor integrated circuit fabrication processes.
• FIG. 3 depicted is a schematic elevational cross-section of a silicon wafer 320 having a thin layer of oxide 321 and a layer of silicon nitride 322 deposited thereon, according to the teachings of this disclosure.
• FIG 3A depicted is a schematic elevational cross-section of the silicon wafer 320 after the step of shallow trench isolation (STI) etch 323.
• FIG 3B depicted is a schematic elevational cross-section of a silicon wafer after performing the process steps of shallow trench isolation (STI) etch, liner oxidation and high-density plasma (HDP) deposition of the silicon wafer shown in Figures 3 and 3A.
• STI shallow trench isolation
• HDP high-density plasma
• a layer of HDP oxide 324 may be deposited onto the silicon substrate 320 and the silicon nitride 322.
• a liner oxidation is performed, oxidizing the portion of the silicon substrate 320 that was exposed by the STI etch 323.
• Other oxides besides HDP oxide may be used and are contemplated herein so long as those oxides have good fill characteristics. Even Spin-On-Glass may be used, for example.
• the STI etch profile and the HDP oxide 324 deposition leave the top of the silicon wafer with an irregular topography.
• FIG 4 depicted is a schematic elevational cross-section of the silicon wafer after performing the process step of spin-coating a layer of partially planarized organosilicate (DUO) onto the silicon wafer shown in Figure 3, according to a specific example embodiment of this disclosure.
• a layer of DUO 426 may be spin-coated onto the HDP oxide 324 which provides a somewhat planarizing effect thereto.
• the layer of DUO 426 may be selective or non-selective to the silicon oxide based upon etch process gases mix.
• a preferable characteristic is that the DUO etch rate may be tuned to be selective or non-selective to the oxide that is being etched. That allows the ability to planarise the oxide stack using only etching (no mask).
• FIG. 5 depicted is a schematic elevational cross-section of the silicon wafer after performing the process step of etching the DUO on the silicon wafer shown in Figure 4, according to a specific example embodiment of this disclosure.
• the silicon wafer may be etched in an oxide etcher, first with a plasma etch that non-selectively etches the DUO 426, using a mixture of CF 4 , 0 2 and Ar.
• a second step may then selectively etch the HDP Oxide 324 over the DUO 426 using gases such as C 4 F 6 , C5F8, C 4 F 8 , O2, N 2 , and/or Ar.
• the etching process stops when a certain depth is reached before coming into contact with the silicon nitride 322.
• FIG. 6 illustrates a schematic elevational cross-section of the silicon wafer after performing the process step of removing the DUO on the silicon wafer shown in Figure 5, according to a specific example embodiment of this disclosure.
• the DUO 426 may be removed by a dry 0 2 ash and an HF clean.
• FIG 7 depicted is a schematic elevational cross-section of the silicon wafer after performing the process step of shallow trench isolation (STI) chemical mechanical polishing (CMP), according to a specific example embodiment of this disclosure.
• the STI CMP is a standard semiconductor integrated circuit process well known to one having ordinary skill in semiconductor integrated circuit manufacturing.
• the HDP oxide 324 is substantially planarized and removed from the layer of silicon nitride 322.
• FIG. 8 depicted is a schematic elevational cross-section of the silicon wafer after performing the process step of removing the silicon nitride to expose portions of the silicon substrate, according to a specific example embodiment of this disclosure.
• the silicon nitride 322 may be removed by using a hot phosphoric acid bath, leaving the silicon substrate 320 exposed between field oxides (FOX) 624, ready for the step of active transistor element doping in the silicon substrate.
• FOX field oxides
• the aforementioned integrated circuit fabrication process could be used in other fabrication steps such as oxide CMP. It may not be economical as this process would add cost at the other steps.
• the liner oxidation is not silicon nitride; it is made of thermally-grown silicon dioxide. Any oxide deposition or fill may be used provided it meets the filling requirement for the given STI process.
• DUO is fairly unique because it was designed for fill and with the ability to change selectivity with different plasma etch processes.
• Bottom anti-reflective-coating BARC has been used in place of DUO for some processing, and it might be applicable in the present process application disclosed herein.

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