JP2017525200A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2017525200A5 JP2017525200A5 JP2016572746A JP2016572746A JP2017525200A5 JP 2017525200 A5 JP2017525200 A5 JP 2017525200A5 JP 2016572746 A JP2016572746 A JP 2016572746A JP 2016572746 A JP2016572746 A JP 2016572746A JP 2017525200 A5 JP2017525200 A5 JP 2017525200A5
- Authority
- JP
- Japan
- Prior art keywords
- utmi
- message
- bus
- phy
- signaling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201462012888P | 2014-06-16 | 2014-06-16 | |
| US62/012,888 | 2014-06-16 | ||
| US14/739,439 US9971730B2 (en) | 2014-06-16 | 2015-06-15 | Link layer to physical layer (PHY) serial interface |
| US14/739,439 | 2015-06-15 | ||
| PCT/US2015/035948 WO2015195612A1 (en) | 2014-06-16 | 2015-06-16 | Link layer to physical layer (phy) serial interface |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017525200A JP2017525200A (ja) | 2017-08-31 |
| JP2017525200A5 true JP2017525200A5 (enExample) | 2018-07-12 |
| JP6517243B2 JP6517243B2 (ja) | 2019-05-22 |
Family
ID=54836282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016572746A Expired - Fee Related JP6517243B2 (ja) | 2014-06-16 | 2015-06-16 | リンクレイヤ／物理レイヤ（ｐｈｙ）シリアルインターフェース |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9971730B2 (enExample) |
| EP (1) | EP3158461B1 (enExample) |
| JP (1) | JP6517243B2 (enExample) |
| ES (1) | ES2705042T3 (enExample) |
| HU (1) | HUE041477T2 (enExample) |
| WO (1) | WO2015195612A1 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9692448B1 (en) | 2016-09-22 | 2017-06-27 | Qualcomm Incorporated | Split chip solution for die-to-die serdes |
| US10372657B2 (en) * | 2016-12-26 | 2019-08-06 | Intel Corporation | Bimodal PHY for low latency in high speed interconnects |
| US10705142B2 (en) * | 2016-12-29 | 2020-07-07 | Intel Corporation | Device, system and method for providing on-chip test/debug functionality |
| US10083147B2 (en) * | 2016-12-30 | 2018-09-25 | Intel Corporation | Apparatuses and methods for multilane universal serial bus (USB2) communication over embedded universal serial bus (eUSB2) |
| US20190025872A1 (en) * | 2017-07-18 | 2019-01-24 | Qualcomm Incorporated | Usb device with clock domain correlation |
| US10762018B1 (en) * | 2018-02-06 | 2020-09-01 | Synopsys, Inc. | Method and apparatus for increasing the number of USB root hub ports |
| US10545902B2 (en) * | 2018-06-25 | 2020-01-28 | Western Digital Technologies, Inc. | Devices and methods for decoupling of physical layer |
| US11637657B2 (en) | 2019-02-15 | 2023-04-25 | Intel Corporation | Low-latency forward error correction for high-speed serial links |
| US11249837B2 (en) | 2019-03-01 | 2022-02-15 | Intel Corporation | Flit-based parallel-forward error correction and parity |
| CN111934707B (zh) * | 2019-04-25 | 2024-07-09 | 恩智浦有限公司 | 数据发射代码和接口 |
| JP7293986B2 (ja) * | 2019-08-27 | 2023-06-20 | 沖電気工業株式会社 | データ処理装置 |
| US11740958B2 (en) * | 2019-11-27 | 2023-08-29 | Intel Corporation | Multi-protocol support on common physical layer |
| KR102833253B1 (ko) | 2020-08-11 | 2025-07-10 | 삼성전자주식회사 | 메모리 컨트롤러, 메모리 컨트롤러의 동작 방법 및 스토리지 장치 |
| US12189470B2 (en) | 2020-09-18 | 2025-01-07 | Intel Corporation | Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects |
| US11921651B2 (en) * | 2021-06-07 | 2024-03-05 | AyDeeKay LLC | Interface module with low-latency communication of electrical signals between power domains |
| EP4318252B1 (en) | 2021-09-29 | 2025-10-01 | Samsung Electronics Co., Ltd. | Electronic device for communicating with external device via usb interface and operation method thereof |
| CN118708520B (zh) * | 2024-05-27 | 2025-12-26 | 芯云晟(杭州)电子科技有限公司 | 基于UCIe的数据传输方法、系统、介质及电子设备 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04290342A (ja) * | 1991-03-19 | 1992-10-14 | Fujitsu Ltd | 情報伝送方式 |
| US7412588B2 (en) | 2003-07-25 | 2008-08-12 | International Business Machines Corporation | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus |
| US8463962B2 (en) | 2006-08-18 | 2013-06-11 | Nxp B.V. | MAC and PHY interface arrangement |
| US8261002B2 (en) * | 2007-09-11 | 2012-09-04 | Quicklogic Corporation | PHY-less ULPI and UTMI bridges |
| US7873774B2 (en) * | 2008-02-01 | 2011-01-18 | Telefonaktiebolaget Lm Ericsson (Publ) | Connections and dynamic configuration of interfaces for mobile phones and multifunctional devices |
| JP2010218196A (ja) * | 2009-03-17 | 2010-09-30 | Seiko Epson Corp | データ転送制御装置及び電子機器 |
| US8416905B2 (en) | 2010-09-24 | 2013-04-09 | Intel Corporation | Digital NRZI signal for serial interconnect communications between the link layer and physical layer |
| US8730978B2 (en) | 2010-09-30 | 2014-05-20 | Maxim Integrated Products, Inc | Analog front end protocol converter/adapter for SLPI protocol |
| US8626975B1 (en) | 2011-09-28 | 2014-01-07 | Maxim Integrated Products, Inc. | Communication interface with reduced signal lines |
| JP5876752B2 (ja) * | 2012-03-12 | 2016-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置及び携帯端末装置 |
| US8972646B2 (en) | 2012-03-30 | 2015-03-03 | Intel Corporation | Superspeed inter-chip interface |
| US8982746B2 (en) * | 2012-06-30 | 2015-03-17 | Intel Corporation | Clock-less half-duplex repeater |
| US9239810B2 (en) | 2012-06-30 | 2016-01-19 | Intel Corporation | Low power universal serial bus |
-
2015
- 2015-06-15 US US14/739,439 patent/US9971730B2/en active Active
- 2015-06-16 HU HUE15733958A patent/HUE041477T2/hu unknown
- 2015-06-16 JP JP2016572746A patent/JP6517243B2/ja not_active Expired - Fee Related
- 2015-06-16 EP EP15733958.1A patent/EP3158461B1/en active Active
- 2015-06-16 ES ES15733958T patent/ES2705042T3/es active Active
- 2015-06-16 WO PCT/US2015/035948 patent/WO2015195612A1/en not_active Ceased
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2017525200A5 (enExample) | ||
| US12111785B2 (en) | PCIE device, apparatus, and method with different bandwidths compatible in same slot | |
| JP6517243B2 (ja) | リンクレイヤ／物理レイヤ（ｐｈｙ）シリアルインターフェース | |
| KR102243771B1 (ko) | 직렬 측파대 시그널링 링크 | |
| JP5346978B2 (ja) | インターフェイス装置、配線基板、及び情報処理装置 | |
| KR20150064243A (ko) | 대역폭 설정가능한 io 커넥터 | |
| CN103092175B (zh) | I2c主设备与从设备之间串行时钟线scl控制的方法及装置 | |
| CN202564744U (zh) | 高速外设组件互连接口与usb3.0装置之间的桥接器 | |
| US20170286357A1 (en) | Method, Apparatus And System For Communicating Between Multiple Protocols | |
| CN101217651B (zh) | 处理串行化的视频数据以用于显示的方法和设备 | |
| CN102163184A (zh) | 一种基于专用多芯片串行互连接口的主从传输系统及方法 | |
| CN107943733A (zh) | 一种单板间并行总线的互联方法 | |
| CN102073611A (zh) | 一种i2c总线控制系统及方法 | |
| CN105281782A (zh) | 通用串行器架构 | |
| CN103077144A (zh) | 一种确保数据完整的spi通讯接口及其通讯方法 | |
| CN105512070A (zh) | 一种基于串行总线的控制系统 | |
| CN109495278B (zh) | 一种基于xmc标准接口的网卡 | |
| CN103873031A (zh) | 非时钟触发寄存器 | |
| Szecówka et al. | USB receiver/transmitter for FPGA implementation | |
| US20070022219A1 (en) | Information processing apparatus and method for initializing flow control | |
| US7770095B2 (en) | Request processing between failure windows | |
| US20020112106A1 (en) | Backplane physical layer controller with an internal bus reset | |
| CN105550151A (zh) | 一种高效串行总线控制电路 | |
| CN104102606A (zh) | 一种pci-express信号长距离传输的方法 | |
| CN205581857U (zh) | 一种实现spi总线上存在多个主设备的装置 |