JP6517243B2 - リンクレイヤ／物理レイヤ（ｐｈｙ）シリアルインターフェース - Google Patents

リンクレイヤ／物理レイヤ（ｐｈｙ）シリアルインターフェース Download PDF

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JP6517243B2
JP6517243B2 JP2016572746A JP2016572746A JP6517243B2 JP 6517243 B2 JP6517243 B2 JP 6517243B2 JP 2016572746 A JP2016572746 A JP 2016572746A JP 2016572746 A JP2016572746 A JP 2016572746A JP 6517243 B2 JP6517243 B2 JP 6517243B2
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phy
utmi
bus
bridge
message
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Japanese (ja)
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JP2017525200A (ja
JP2017525200A5 (enExample
Inventor
テレンス・ブライアン・レンプル
ナム・ヴァン・ダン
ササン・シャーロキニア
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/426—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3812—USB port controller

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
JP2016572746A 2014-06-16 2015-06-16 リンクレイヤ／物理レイヤ（ｐｈｙ）シリアルインターフェース Expired - Fee Related JP6517243B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462012888P 2014-06-16 2014-06-16
US62/012,888 2014-06-16
US14/739,439 US9971730B2 (en) 2014-06-16 2015-06-15 Link layer to physical layer (PHY) serial interface
US14/739,439 2015-06-15
PCT/US2015/035948 WO2015195612A1 (en) 2014-06-16 2015-06-16 Link layer to physical layer (phy) serial interface

Publications (3)

Publication Number Publication Date
JP2017525200A JP2017525200A (ja) 2017-08-31
JP2017525200A5 JP2017525200A5 (enExample) 2018-07-12
JP6517243B2 true JP6517243B2 (ja) 2019-05-22

Family

ID=54836282

Family Applications (1)

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JP2016572746A Expired - Fee Related JP6517243B2 (ja) 2014-06-16 2015-06-16 リンクレイヤ／物理レイヤ（ｐｈｙ）シリアルインターフェース

Country Status (6)

Country Link
US (1) US9971730B2 (enExample)
EP (1) EP3158461B1 (enExample)
JP (1) JP6517243B2 (enExample)
ES (1) ES2705042T3 (enExample)
HU (1) HUE041477T2 (enExample)
WO (1) WO2015195612A1 (enExample)

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US10372657B2 (en) * 2016-12-26 2019-08-06 Intel Corporation Bimodal PHY for low latency in high speed interconnects
US10705142B2 (en) * 2016-12-29 2020-07-07 Intel Corporation Device, system and method for providing on-chip test/debug functionality
US10083147B2 (en) * 2016-12-30 2018-09-25 Intel Corporation Apparatuses and methods for multilane universal serial bus (USB2) communication over embedded universal serial bus (eUSB2)
US20190025872A1 (en) * 2017-07-18 2019-01-24 Qualcomm Incorporated Usb device with clock domain correlation
US10762018B1 (en) * 2018-02-06 2020-09-01 Synopsys, Inc. Method and apparatus for increasing the number of USB root hub ports
US10545902B2 (en) * 2018-06-25 2020-01-28 Western Digital Technologies, Inc. Devices and methods for decoupling of physical layer
US11637657B2 (en) 2019-02-15 2023-04-25 Intel Corporation Low-latency forward error correction for high-speed serial links
US11249837B2 (en) 2019-03-01 2022-02-15 Intel Corporation Flit-based parallel-forward error correction and parity
CN111934707B (zh) * 2019-04-25 2024-07-09 恩智浦有限公司 数据发射代码和接口
JP7293986B2 (ja) * 2019-08-27 2023-06-20 沖電気工業株式会社 データ処理装置
US11740958B2 (en) * 2019-11-27 2023-08-29 Intel Corporation Multi-protocol support on common physical layer
KR102833253B1 (ko) 2020-08-11 2025-07-10 삼성전자주식회사 메모리 컨트롤러, 메모리 컨트롤러의 동작 방법 및 스토리지 장치
US12189470B2 (en) 2020-09-18 2025-01-07 Intel Corporation Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects
US11921651B2 (en) * 2021-06-07 2024-03-05 AyDeeKay LLC Interface module with low-latency communication of electrical signals between power domains
EP4318252B1 (en) 2021-09-29 2025-10-01 Samsung Electronics Co., Ltd. Electronic device for communicating with external device via usb interface and operation method thereof
CN118708520B (zh) * 2024-05-27 2025-12-26 芯云晟(杭州)电子科技有限公司 基于UCIe的数据传输方法、系统、介质及电子设备

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JPH04290342A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd 情報伝送方式
US7412588B2 (en) 2003-07-25 2008-08-12 International Business Machines Corporation Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
US8463962B2 (en) 2006-08-18 2013-06-11 Nxp B.V. MAC and PHY interface arrangement
US8261002B2 (en) * 2007-09-11 2012-09-04 Quicklogic Corporation PHY-less ULPI and UTMI bridges
US7873774B2 (en) * 2008-02-01 2011-01-18 Telefonaktiebolaget Lm Ericsson (Publ) Connections and dynamic configuration of interfaces for mobile phones and multifunctional devices
JP2010218196A (ja) * 2009-03-17 2010-09-30 Seiko Epson Corp データ転送制御装置及び電子機器
US8416905B2 (en) 2010-09-24 2013-04-09 Intel Corporation Digital NRZI signal for serial interconnect communications between the link layer and physical layer
US8730978B2 (en) 2010-09-30 2014-05-20 Maxim Integrated Products, Inc Analog front end protocol converter/adapter for SLPI protocol
US8626975B1 (en) 2011-09-28 2014-01-07 Maxim Integrated Products, Inc. Communication interface with reduced signal lines
JP5876752B2 (ja) * 2012-03-12 2016-03-02 ルネサスエレクトロニクス株式会社 半導体装置及び携帯端末装置
US8972646B2 (en) 2012-03-30 2015-03-03 Intel Corporation Superspeed inter-chip interface
US8982746B2 (en) * 2012-06-30 2015-03-17 Intel Corporation Clock-less half-duplex repeater
US9239810B2 (en) 2012-06-30 2016-01-19 Intel Corporation Low power universal serial bus

Also Published As

Publication number Publication date
ES2705042T3 (es) 2019-03-21
WO2015195612A1 (en) 2015-12-23
HUE041477T2 (hu) 2019-05-28
US9971730B2 (en) 2018-05-15
JP2017525200A (ja) 2017-08-31
CN106462534A (zh) 2017-02-22
US20150363349A1 (en) 2015-12-17
EP3158461B1 (en) 2018-10-24
EP3158461A1 (en) 2017-04-26

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