JP2017514300A - Tsv接続された背部側分離 - Google Patents
Tsv接続された背部側分離 Download PDFInfo
- Publication number
- JP2017514300A JP2017514300A JP2016558360A JP2016558360A JP2017514300A JP 2017514300 A JP2017514300 A JP 2017514300A JP 2016558360 A JP2016558360 A JP 2016558360A JP 2016558360 A JP2016558360 A JP 2016558360A JP 2017514300 A JP2017514300 A JP 2017514300A
- Authority
- JP
- Japan
- Prior art keywords
- die
- capacitor
- back side
- contact point
- mim
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/117—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
実例1: 装置がダイを含み、ダイがダイのデバイス側から背部側へと延びる複数のスルーシリコンビア(TSV)と;TSVに接続された分離キャパシタとを含む。
Claims (27)
- 装置であって、
ダイであり、当該ダイのデバイス側から背部側へと延びる複数のスルーシリコンビア(TSV)を含むダイと、
前記TSVに接続されている分離キャパシタと
を含む装置。 - 前記分離キャパシタが金属−絶縁体−金属(MIM)キャパシタを含む、請求項1の装置。
- 前記TSVがダイの背部側上でコンタクトポイントを画成しており、前記MIMキャパシタはコンタクトポイントに直接に結合されている金属−誘電体−金属層を含む、請求項2の装置。
- さらに第2のダイを含み、MIMキャパシタが前記第2のダイの上に形成されている、請求項2の装置。
- 前記TSVはダイの背部側上でコンタクトポイントを画成しており、前記MIMキャパシタの金属層がコンタクトポイントに結合されている、請求項4の装置。
- 前記MIMキャパシタの第1層がハンダ接続部を通じて前記コンタクトポイントに結合されている、請求項5の装置。
- 前記TSVがダイの背部側上でコンタクトポイントを画成しており、前記分離キャパシタはコンタクトポイントに結合されるセラミックアレイキャパシタを含む、請求項1の装置。
- 前記セラミックアレイキャパシタは、ハンダ接続部を介して前記コンタクトポイントに結合されている、請求項7の装置。
- さらにダイのデバイス側に位置する金属−絶縁体−金属(MIM)キャパシタを含む、請求項1の装置。
- 方法であって、
ダイを提供する工程であり、当該ダイは当該ダイのデバイス側から背部側へと延びる複数のスルーシリコンビア(TSV)を含む、ダイの提供工程と、
前記ダイの背部側に分離キャパシタを結合する工程と、
を含む方法。 - 前記分離キャパシタが、金属−絶縁体−金属(MIM)キャパシタを含む、請求項10記載の方法。
- 前記TSVがダイの背部側上でコンタクトポイントを画成し、前記のMIMキャパシタを結合する工程は、MIMの金属層をコンタクトポイントに直接に結合する工程を含む、請求項11記載の方法。
- 前記のダイの背部側に分離キャパシタを結合する工程が、ダイの背部側に第2のダイを結合する工程を含み、MIMキャパシタが第2のダイ上に形成される、請求項11記載の方法。
- 前記TSVがダイの背部側上でコンタクトポイントを画成し、前記分離キャパシタの金属層が前記コンタクトポイントに結合される、請求項13記載の方法。
- 前記MIMキャパシタの金属層が、ハンダ接続部を通じて前記コンタクトポイントに結合される、請求項14記載の方法。
- 前記TSVがダイの背部側上でコンタクトポイントを画成し、分離キャパシタはセラミックアレイキャパシタを含み、前記のダイの背部側に接続する工程は、前記セラミックアレイキャパシタを前記コンタクトポイントに結合する工程を含む、請求項10記載の方法。
- 前記セラミックアレイキャパシタは、ハンダ接続部を通じてコンタクトポイントに結合される、請求項16記載の方法。
- さらに、金属−絶縁体−金属(MIM)キャパシタを前記ダイのデバイス側に結合する工程を含む、請求項10記載の方法。
- 装置であって、
パッケージを含むコンピューティングデバイスと、
プリント回路ボードとを含み、
前記コンピューティングデバイスは、
デバイス側と背部側とを含むマイクロプロセッサであり、スルーシリコンビア(TSV)がデバイス側から背部側へと延びるマイクロプロセッサと、
ダイの背部側に結合されている分離キャパシタとを含み、
前記パッケージは、プリント回路ボードに結合されている、
装置。 - 前記分離キャパシタが金属−絶縁体−金属(MIM)キャパシタを含む、請求項19記載の装置。
- 前記TSVがダイの背部側上でコンタクトポイントを画成しており、前記MIMキャパシタはコンタクトポイントに直接に接続されている金属層を含む、請求項20記載の装置。
- さらに、第2のダイを含み、MIMキャパシタが第2のダイ上に形成されている、請求項21記載の装置。
- 前記TSVはダイの背部側上でコンタクトポイントを画成しており、MIMキャパシタの金属層が前記コンタクトポイントに結合されている、請求項22記載の装置。
- 前記MIMキャパシタの第1層はハンダ接続部を通じて前記コンタクトポイントに結合されている、請求項23記載の装置。
- 前記TSVはダイの背部側上でコンタクトポイントを画成しており、前記分離キャパシタは前記コンタクトポイントに結合されるセラミックアレイキャパシタを含む、請求項23記載の装置。
- 前記セラミックアレイキャパシタはハンダ接続部を介して前記コンタクトポイントに結合されている、請求項25記載の装置。
- さらに、マイクロプロセッサのデバイス側に接続される金属−絶縁体−金属(MIM)キャパシタを含む、請求項19記載の装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2014/032263 WO2015147881A1 (en) | 2014-03-28 | 2014-03-28 | Tsv-connected backside decoupling |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017514300A true JP2017514300A (ja) | 2017-06-01 |
JP6416276B2 JP6416276B2 (ja) | 2018-10-31 |
Family
ID=54196195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016558360A Active JP6416276B2 (ja) | 2014-03-28 | 2014-03-28 | Tsv接続された背部側分離 |
Country Status (8)
Country | Link |
---|---|
US (1) | US20170012029A1 (ja) |
EP (1) | EP3123504A4 (ja) |
JP (1) | JP6416276B2 (ja) |
KR (1) | KR101950078B1 (ja) |
CN (1) | CN106463489A (ja) |
MY (1) | MY186309A (ja) |
TW (1) | TWI642165B (ja) |
WO (1) | WO2015147881A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021079975A1 (ja) * | 2019-10-23 | 2021-04-29 | ソニー株式会社 | 表示システム、表示装置、表示方法、及び、移動装置 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9893042B2 (en) * | 2015-12-14 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
KR20190092407A (ko) | 2016-12-29 | 2019-08-07 | 인텔 코포레이션 | 하이퍼칩 |
KR102450580B1 (ko) | 2017-12-22 | 2022-10-07 | 삼성전자주식회사 | 금속 배선 하부의 절연층 구조를 갖는 반도체 장치 |
JP7430718B2 (ja) * | 2018-10-18 | 2024-02-13 | スモルテク アクティエボラーグ | ディスクリート金属-絶縁体-金属(mim)エネルギー蓄積部品及びその製造方法 |
TW202038266A (zh) * | 2018-11-26 | 2020-10-16 | 瑞典商斯莫勒科技公司 | 具有離散的能量儲存構件之半導體組件 |
US11393763B2 (en) * | 2020-05-28 | 2022-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out (info) package structure and method |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0888319A (ja) * | 1994-09-16 | 1996-04-02 | Toshiba Corp | 半導体集積回路 |
JP2000331805A (ja) * | 1999-05-19 | 2000-11-30 | Matsushita Electric Ind Co Ltd | 積層型セラミックアレイ |
JP2007184324A (ja) * | 2006-01-04 | 2007-07-19 | Nec Corp | キャパシタ、チップキャリア型キャパシタ、半導体装置および実装基板ならびにキャパシタの製造方法 |
US20080157313A1 (en) * | 2006-12-29 | 2008-07-03 | Sriram Dattaguru | Array capacitor for decoupling multiple voltages |
US20090057867A1 (en) * | 2007-08-30 | 2009-03-05 | Vincent Hool | Integrated Circuit Package with Passive Component |
JP2010080801A (ja) * | 2008-09-29 | 2010-04-08 | Hitachi Ltd | 半導体装置 |
WO2010047227A1 (ja) * | 2008-10-21 | 2010-04-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
WO2012157167A1 (ja) * | 2011-05-17 | 2012-11-22 | パナソニック株式会社 | 三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法 |
JP2013138123A (ja) * | 2011-12-28 | 2013-07-11 | Tokyo Electron Ltd | 半導体装置の製造方法及び半導体装置 |
US20130256834A1 (en) * | 2012-03-27 | 2013-10-03 | Globalfoundries Singapore Pte. Ltd. | Back-side mom/mim devices |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811868A (en) * | 1996-12-20 | 1998-09-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor |
US6459561B1 (en) * | 2001-06-12 | 2002-10-01 | Avx Corporation | Low inductance grid array capacitor |
US7719079B2 (en) * | 2007-01-18 | 2010-05-18 | International Business Machines Corporation | Chip carrier substrate capacitor and method for fabrication thereof |
US7605458B1 (en) * | 2007-02-01 | 2009-10-20 | Xilinx, Inc. | Method and apparatus for integrating capacitors in stacked integrated circuits |
US8362599B2 (en) * | 2009-09-24 | 2013-01-29 | Qualcomm Incorporated | Forming radio frequency integrated circuits |
US8748284B2 (en) * | 2011-08-12 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing decoupling MIM capacitor designs for interposers |
US8716856B2 (en) * | 2012-08-02 | 2014-05-06 | Globalfoundries Singapore Pte. Ltd. | Device with integrated power supply |
US8610281B1 (en) * | 2012-10-02 | 2013-12-17 | Global Foundries Inc. | Double-sided semiconductor structure using through-silicon vias |
TWI517354B (zh) * | 2014-02-25 | 2016-01-11 | 力成科技股份有限公司 | 內藏去耦合電容之半導體封裝構造 |
-
2014
- 2014-03-28 WO PCT/US2014/032263 patent/WO2015147881A1/en active Application Filing
- 2014-03-28 MY MYPI2016703126A patent/MY186309A/en unknown
- 2014-03-28 EP EP14886705.4A patent/EP3123504A4/en not_active Ceased
- 2014-03-28 CN CN201480076464.9A patent/CN106463489A/zh active Pending
- 2014-03-28 US US15/117,708 patent/US20170012029A1/en not_active Abandoned
- 2014-03-28 JP JP2016558360A patent/JP6416276B2/ja active Active
- 2014-03-28 KR KR1020167023653A patent/KR101950078B1/ko active IP Right Grant
-
2015
- 2015-02-04 TW TW104103743A patent/TWI642165B/zh active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0888319A (ja) * | 1994-09-16 | 1996-04-02 | Toshiba Corp | 半導体集積回路 |
JP2000331805A (ja) * | 1999-05-19 | 2000-11-30 | Matsushita Electric Ind Co Ltd | 積層型セラミックアレイ |
JP2007184324A (ja) * | 2006-01-04 | 2007-07-19 | Nec Corp | キャパシタ、チップキャリア型キャパシタ、半導体装置および実装基板ならびにキャパシタの製造方法 |
US20080157313A1 (en) * | 2006-12-29 | 2008-07-03 | Sriram Dattaguru | Array capacitor for decoupling multiple voltages |
US20090057867A1 (en) * | 2007-08-30 | 2009-03-05 | Vincent Hool | Integrated Circuit Package with Passive Component |
JP2010080801A (ja) * | 2008-09-29 | 2010-04-08 | Hitachi Ltd | 半導体装置 |
WO2010047227A1 (ja) * | 2008-10-21 | 2010-04-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
WO2012157167A1 (ja) * | 2011-05-17 | 2012-11-22 | パナソニック株式会社 | 三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法 |
JP2013138123A (ja) * | 2011-12-28 | 2013-07-11 | Tokyo Electron Ltd | 半導体装置の製造方法及び半導体装置 |
US20130256834A1 (en) * | 2012-03-27 | 2013-10-03 | Globalfoundries Singapore Pte. Ltd. | Back-side mom/mim devices |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021079975A1 (ja) * | 2019-10-23 | 2021-04-29 | ソニー株式会社 | 表示システム、表示装置、表示方法、及び、移動装置 |
Also Published As
Publication number | Publication date |
---|---|
KR101950078B1 (ko) | 2019-02-19 |
JP6416276B2 (ja) | 2018-10-31 |
KR20160113701A (ko) | 2016-09-30 |
US20170012029A1 (en) | 2017-01-12 |
TWI642165B (zh) | 2018-11-21 |
MY186309A (en) | 2021-07-07 |
CN106463489A (zh) | 2017-02-22 |
TW201541608A (zh) | 2015-11-01 |
EP3123504A4 (en) | 2017-12-13 |
WO2015147881A1 (en) | 2015-10-01 |
EP3123504A1 (en) | 2017-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6416276B2 (ja) | Tsv接続された背部側分離 | |
US10522454B2 (en) | Microelectronic package having a passive microelectronic device disposed within a package body | |
KR101815489B1 (ko) | 스루 브리지 도전성 비아 신호 접속에 의한 임베딩된 멀티디바이스 브리지 | |
US20190198481A1 (en) | Integrated circuit die having backside passive components and methods associated therewith | |
US11721631B2 (en) | Via structures having tapered profiles for embedded interconnect bridge substrates | |
US20190013301A1 (en) | Stacked dies with passive components within facing recesses | |
US10014278B2 (en) | Semiconductor chip and stacked semiconductor package having the same | |
TWI572574B (zh) | 硫族玻璃組成物及硫族開關裝置 | |
US10916524B2 (en) | Stacked dice systems | |
US20190103357A1 (en) | Methods of forming package on package assemblies with reduced z height and structures formed thereby | |
TWI795072B (zh) | 在導電連接件的形成中使用貴金屬 | |
TW202101727A (zh) | 晶粒的互連轂 | |
US10985136B2 (en) | Microelectronic die stack having at least one rotated microelectronic die | |
US20150279774A1 (en) | Space transformer | |
US10770429B2 (en) | Microelectronic device stacks having interior window wirebonding | |
JP2023507701A (ja) | 集積回路デバイスのためのメタライゼーション層におけるスキップレベルビア | |
US11848311B2 (en) | Microelectronic packages having a die stack and a device within the footprint of the die stack |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170825 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170905 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20171204 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180201 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180515 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180814 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180904 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20181003 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6416276 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |