JP6416276B2 - Tsv接続された背部側分離 - Google Patents
Tsv接続された背部側分離 Download PDFInfo
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- JP6416276B2 JP6416276B2 JP2016558360A JP2016558360A JP6416276B2 JP 6416276 B2 JP6416276 B2 JP 6416276B2 JP 2016558360 A JP2016558360 A JP 2016558360A JP 2016558360 A JP2016558360 A JP 2016558360A JP 6416276 B2 JP6416276 B2 JP 6416276B2
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- 238000000926 separation method Methods 0.000 title claims description 5
- 239000003990 capacitor Substances 0.000 claims description 109
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 30
- 229910000679 solder Inorganic materials 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000010949 copper Substances 0.000 description 19
- 238000004891 communication Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 12
- 238000001465 metallisation Methods 0.000 description 11
- 239000000919 ceramic Substances 0.000 description 8
- 230000007704 transition Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- MPTQRFCYZCXJFQ-UHFFFAOYSA-L copper(II) chloride dihydrate Chemical compound O.O.[Cl-].[Cl-].[Cu+2] MPTQRFCYZCXJFQ-UHFFFAOYSA-L 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
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Description
実例1: 装置がダイを含み、ダイがダイのデバイス側から背部側へと延びる複数のスルーシリコンビア(TSV)と;TSVに接続された分離キャパシタとを含む。
Claims (12)
- 装置であって、
集積回路ダイであり、当該集積回路ダイのデバイス側から背部側へと延びる複数のスルーシリコンビア(TSV)を含む集積回路ダイと、
前記集積回路ダイの背部側にある第2の集積回路ダイと、
前記第2の集積回路ダイの前記集積回路ダイ側の上に形成され、前記TSVに接続されている分離キャパシタと
を含み、
前記分離キャパシタが、前記第2の集積回路ダイの前記集積回路側の面に平行な第1金属層と、該第1金属層に平行な絶縁層と、該絶縁層に平行であり前記TSVに接続されている第2金属層とを有する金属−絶縁体−金属(MIM)キャパシタを含む、
装置。 - 前記TSVは前記集積回路ダイの背部側上でコンタクトポイントを画成しており、前記MIMキャパシタの前記第2金属層がコンタクトポイントに結合されている、請求項1の装置。
- 前記MIMキャパシタの前記第2金属層がハンダ接続部を通じて前記コンタクトポイントに結合されている、請求項2の装置。
- さらに前記集積回路ダイのデバイス側に位置する金属−絶縁体−金属(MIM)キャパシタを含む、請求項1の装置。
- 方法であって、
集積回路ダイを提供する工程であり、当該集積回路ダイは当該集積回路ダイのデバイス側から背部側へと延びる複数のスルーシリコンビア(TSV)を含む、当該集積回路ダイの提供工程と、
前記集積回路ダイの背部側に第2の集積回路ダイを提供する工程と、
前記第2の集積回路ダイの前記集積回路ダイ側の上に形成され、前記TSVに接続される分離キャパシタを提供する工程と、
を含み、
前記分離キャパシタを、前記第2の集積回路ダイの前記集積回路側の面に平行な第1金属層と、該第1金属層に平行な絶縁層と、該絶縁層に平行であり前記TSVに接続されている第2金属層とを有する金属−絶縁体−金属(MIM)キャパシタを含むように提供する、
方法。 - 前記TSVが前記集積回路ダイの背部側上でコンタクトポイントを画成し、前記MIMキャパシタを提供する工程は、前記MIMキャパシタの前記第2金属層を前記コンタクトポイントに直接に結合する工程を含む、請求項5記載の方法。
- 前記MIMキャパシタの前記第2金属層が、ハンダ接続部を通じて前記コンタクトポイントに結合される、請求項6記載の方法。
- さらに、金属−絶縁体−金属(MIM)キャパシタを前記集積回路ダイのデバイス側に結合する工程を含む、請求項5記載の方法。
- 装置であって、
パッケージを含むコンピューティングデバイスと、
プリント回路ボードとを含み、
前記コンピューティングデバイスは、
デバイス側と背部側とを含むマイクロプロセッサダイであり、スルーシリコンビア(TSV)がデバイス側から背部側へと延びるマイクロプロセッサダイと、
前記マイクロプロセッサダイの背部側にある第2の集積回路ダイと、
前記第2の集積回路ダイの前記マイクロプロセッサダイ側の上に形成され、前記TSVに接続されている分離キャパシタと、
を含み、
前記パッケージは、プリント回路ボードに結合されており、
前記分離キャパシタが、前記第2の集積回路ダイの前記マイクロプロセッサダイ側の面に平行な第1金属層と、該第1金属層に平行な絶縁層と、該絶縁層に平行であり前記TSVに接続されている第2金属層とを有する金属−絶縁体−金属(MIM)キャパシタを含む、
装置。 - 前記TSVは前記マイクロプロセッサダイの背部側上でコンタクトポイントを画成しており、前記MIMキャパシタの前記第2金属層が前記コンタクトポイントに結合されている、請求項9記載の装置。
- 前記MIMキャパシタの前記第2金属層はハンダ接続部を通じて前記コンタクトポイントに結合されている、請求項10記載の装置。
- さらに、前記マイクロプロセッサダイのデバイス側に接続される金属−絶縁体−金属(MIM)キャパシタを含む、請求項9記載の装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2014/032263 WO2015147881A1 (en) | 2014-03-28 | 2014-03-28 | Tsv-connected backside decoupling |
Publications (2)
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US (1) | US20170012029A1 (ja) |
EP (1) | EP3123504A4 (ja) |
JP (1) | JP6416276B2 (ja) |
KR (1) | KR101950078B1 (ja) |
CN (1) | CN106463489A (ja) |
MY (1) | MY186309A (ja) |
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US9893042B2 (en) * | 2015-12-14 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
DE112017006705T5 (de) | 2016-12-29 | 2019-09-12 | Intel Corporation | Hyperchip |
KR102450580B1 (ko) | 2017-12-22 | 2022-10-07 | 삼성전자주식회사 | 금속 배선 하부의 절연층 구조를 갖는 반도체 장치 |
CN112823403B (zh) * | 2018-10-18 | 2023-05-02 | 斯莫特克有限公司 | 分立金属-绝缘体-金属(mim)能量存储部件和制造方法 |
TW202038266A (zh) * | 2018-11-26 | 2020-10-16 | 瑞典商斯莫勒科技公司 | 具有離散的能量儲存構件之半導體組件 |
EP4049877A4 (en) * | 2019-10-23 | 2022-12-21 | Sony Group Corporation | DISPLAY SYSTEM, DISPLAY DEVICE, DISPLAY METHOD AND MOVING DEVICE |
US11393763B2 (en) * | 2020-05-28 | 2022-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out (info) package structure and method |
US12002758B2 (en) | 2021-11-04 | 2024-06-04 | International Business Machines Corporation | Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer |
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---|---|---|---|---|
JPH0888319A (ja) * | 1994-09-16 | 1996-04-02 | Toshiba Corp | 半導体集積回路 |
US5811868A (en) * | 1996-12-20 | 1998-09-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor |
JP2000331805A (ja) * | 1999-05-19 | 2000-11-30 | Matsushita Electric Ind Co Ltd | 積層型セラミックアレイ |
US6459561B1 (en) * | 2001-06-12 | 2002-10-01 | Avx Corporation | Low inductance grid array capacitor |
JP4470013B2 (ja) * | 2006-01-04 | 2010-06-02 | 日本電気株式会社 | キャパシタ、チップキャリア型キャパシタ、半導体装置および実装基板 |
US20080157313A1 (en) * | 2006-12-29 | 2008-07-03 | Sriram Dattaguru | Array capacitor for decoupling multiple voltages |
US7719079B2 (en) * | 2007-01-18 | 2010-05-18 | International Business Machines Corporation | Chip carrier substrate capacitor and method for fabrication thereof |
US7605458B1 (en) * | 2007-02-01 | 2009-10-20 | Xilinx, Inc. | Method and apparatus for integrating capacitors in stacked integrated circuits |
US20090057867A1 (en) * | 2007-08-30 | 2009-03-05 | Vincent Hool | Integrated Circuit Package with Passive Component |
JP2010080801A (ja) * | 2008-09-29 | 2010-04-08 | Hitachi Ltd | 半導体装置 |
JP5413371B2 (ja) * | 2008-10-21 | 2014-02-12 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US8362599B2 (en) * | 2009-09-24 | 2013-01-29 | Qualcomm Incorporated | Forming radio frequency integrated circuits |
WO2012157167A1 (ja) * | 2011-05-17 | 2012-11-22 | パナソニック株式会社 | 三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法 |
US8748284B2 (en) * | 2011-08-12 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing decoupling MIM capacitor designs for interposers |
JP2013138123A (ja) * | 2011-12-28 | 2013-07-11 | Tokyo Electron Ltd | 半導体装置の製造方法及び半導体装置 |
US8759947B2 (en) * | 2012-03-27 | 2014-06-24 | Globalfoundries Singapore Pte. Ltd. | Back-side MOM/MIM devices |
US8716856B2 (en) * | 2012-08-02 | 2014-05-06 | Globalfoundries Singapore Pte. Ltd. | Device with integrated power supply |
US8610281B1 (en) * | 2012-10-02 | 2013-12-17 | Global Foundries Inc. | Double-sided semiconductor structure using through-silicon vias |
TWI517354B (zh) * | 2014-02-25 | 2016-01-11 | 力成科技股份有限公司 | 內藏去耦合電容之半導體封裝構造 |
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TWI642165B (zh) | 2018-11-21 |
EP3123504A1 (en) | 2017-02-01 |
WO2015147881A1 (en) | 2015-10-01 |
JP2017514300A (ja) | 2017-06-01 |
US20170012029A1 (en) | 2017-01-12 |
KR101950078B1 (ko) | 2019-02-19 |
KR20160113701A (ko) | 2016-09-30 |
EP3123504A4 (en) | 2017-12-13 |
CN106463489A (zh) | 2017-02-22 |
TW201541608A (zh) | 2015-11-01 |
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