JP2017510902A5 - - Google Patents

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Publication number
JP2017510902A5
JP2017510902A5 JP2016561316A JP2016561316A JP2017510902A5 JP 2017510902 A5 JP2017510902 A5 JP 2017510902A5 JP 2016561316 A JP2016561316 A JP 2016561316A JP 2016561316 A JP2016561316 A JP 2016561316A JP 2017510902 A5 JP2017510902 A5 JP 2017510902A5
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JP
Japan
Prior art keywords
cache
cache line
response
line
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2016561316A
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English (en)
Japanese (ja)
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JP2017510902A (ja
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Publication date
Priority claimed from US14/251,628 external-priority patent/US20150293847A1/en
Application filed filed Critical
Publication of JP2017510902A publication Critical patent/JP2017510902A/ja
Publication of JP2017510902A5 publication Critical patent/JP2017510902A5/ja
Ceased legal-status Critical Current

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JP2016561316A 2014-04-13 2015-03-31 無効化を伴う読取りを使用してキャッシュにおける帯域幅および電力を下げる方法および装置 Ceased JP2017510902A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/251,628 2014-04-13
US14/251,628 US20150293847A1 (en) 2014-04-13 2014-04-13 Method and apparatus for lowering bandwidth and power in a cache using read with invalidate
PCT/US2015/023686 WO2015160503A1 (en) 2014-04-13 2015-03-31 Method and apparatus for lowering bandwidth and power in a cache using read with invalidate

Publications (2)

Publication Number Publication Date
JP2017510902A JP2017510902A (ja) 2017-04-13
JP2017510902A5 true JP2017510902A5 (enExample) 2018-04-26

Family

ID=53039586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016561316A Ceased JP2017510902A (ja) 2014-04-13 2015-03-31 無効化を伴う読取りを使用してキャッシュにおける帯域幅および電力を下げる方法および装置

Country Status (8)

Country Link
US (1) US20150293847A1 (enExample)
EP (1) EP3132354A1 (enExample)
JP (1) JP2017510902A (enExample)
KR (1) KR20160143682A (enExample)
CN (1) CN106170776A (enExample)
BR (1) BR112016023745A2 (enExample)
TW (1) TW201604681A (enExample)
WO (1) WO2015160503A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10176096B2 (en) * 2016-02-22 2019-01-08 Qualcomm Incorporated Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
US10552153B2 (en) * 2017-03-31 2020-02-04 Intel Corporation Efficient range-based memory writeback to improve host to device communication for optimal power and performance
US11023162B2 (en) 2019-08-22 2021-06-01 Apple Inc. Cache memory with transient storage for cache lines
CN113918081B (zh) 2020-07-08 2024-03-26 慧荣科技股份有限公司 计算机可读取存储介质、配置可靠命令的方法及装置
TWI771707B (zh) * 2020-07-08 2022-07-21 慧榮科技股份有限公司 組態可靠命令的方法及裝置以及電腦程式產品

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354649A (ja) * 1989-07-24 1991-03-08 Oki Electric Ind Co Ltd バッファ記憶制御方式
JPH0448358A (ja) * 1990-06-18 1992-02-18 Nec Corp キャッシュ・メモリ制御方式
JPH08137748A (ja) * 1994-11-08 1996-05-31 Toshiba Corp コピーバックキャッシュを有するコンピュータ及びコピーバックキャッシュ制御方法
DE69622079T2 (de) * 1995-03-31 2002-10-31 Sun Microsystems, Inc. Verfahren und Vorrichtung zur schnellen Einleitung von Speicherzugriffen in einem cachekohärenten Multiprozessorsystem
JP4434534B2 (ja) * 2001-09-27 2010-03-17 株式会社東芝 プロセッサ・システム
JP2003177963A (ja) * 2001-12-12 2003-06-27 Hitachi Ltd ストレージ装置
US6968429B2 (en) * 2003-02-20 2005-11-22 Sun Microsystems, Inc. Method and apparatus for controlling line eviction in a cache
US8214601B2 (en) * 2004-07-30 2012-07-03 Hewlett-Packard Development Company, L.P. Purging without write-back of cache lines containing spent data
JP2006119796A (ja) * 2004-10-20 2006-05-11 Matsushita Electric Ind Co Ltd キャッシュメモリシステムおよび動画処理装置
US7461209B2 (en) * 2005-12-06 2008-12-02 International Business Machines Corporation Transient cache storage with discard function for disposable data
US20090006668A1 (en) * 2007-06-28 2009-01-01 Anil Vasudevan Performing direct data transactions with a cache memory
US20090037661A1 (en) * 2007-08-04 2009-02-05 Applied Micro Circuits Corporation Cache mechanism for managing transient data
US20120047330A1 (en) * 2010-08-18 2012-02-23 Nec Laboratories America, Inc. I/o efficiency of persistent caches in a storage system
US20120297147A1 (en) * 2011-05-20 2012-11-22 Nokia Corporation Caching Operations for a Non-Volatile Memory Array
JP2014178804A (ja) * 2013-03-14 2014-09-25 Sony Corp キャッシュ制御装置、プロセッサ、情報処理システム、および、その制御方法

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