BR112016023745A2 - método e aparelho para reduzir a largura de banda e energia em uma memória temporária utilizando leitura com invalidação - Google Patents
método e aparelho para reduzir a largura de banda e energia em uma memória temporária utilizando leitura com invalidaçãoInfo
- Publication number
- BR112016023745A2 BR112016023745A2 BR112016023745A BR112016023745A BR112016023745A2 BR 112016023745 A2 BR112016023745 A2 BR 112016023745A2 BR 112016023745 A BR112016023745 A BR 112016023745A BR 112016023745 A BR112016023745 A BR 112016023745A BR 112016023745 A2 BR112016023745 A2 BR 112016023745A2
- Authority
- BR
- Brazil
- Prior art keywords
- temporary memory
- buffer
- power
- writeback
- reducing bandwidth
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
dados efêmeros armazenados em uma memória temporária são lidos quando necessário, mas não são escritos na memória do sistema de modo a e economizar energia e largura de banda. em uma modalidade, um bit sem escrita de retorno associado com os dados efêmeros é configurado em resposta a uma instrução de leitura sem escrita de retorno. os dados em uma linha de memória temporária para a qual seu bit sem escrita de retorno foi configurado não é escrita novamente na memória do sistema. de acordo, quando da eliminação das linhas de memória temporária, se uma linha de memória temporária possuir um bit sem escrita de retorno configurado, então os dados nessa linha de memória temporária são descartados sem serem escritos de volta na memória do sistema.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/251,628 US20150293847A1 (en) | 2014-04-13 | 2014-04-13 | Method and apparatus for lowering bandwidth and power in a cache using read with invalidate |
PCT/US2015/023686 WO2015160503A1 (en) | 2014-04-13 | 2015-03-31 | Method and apparatus for lowering bandwidth and power in a cache using read with invalidate |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112016023745A2 true BR112016023745A2 (pt) | 2017-08-15 |
Family
ID=53039586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112016023745A BR112016023745A2 (pt) | 2014-04-13 | 2015-03-31 | método e aparelho para reduzir a largura de banda e energia em uma memória temporária utilizando leitura com invalidação |
Country Status (8)
Country | Link |
---|---|
US (1) | US20150293847A1 (pt) |
EP (1) | EP3132354A1 (pt) |
JP (1) | JP2017510902A (pt) |
KR (1) | KR20160143682A (pt) |
CN (1) | CN106170776A (pt) |
BR (1) | BR112016023745A2 (pt) |
TW (1) | TW201604681A (pt) |
WO (1) | WO2015160503A1 (pt) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10176096B2 (en) * | 2016-02-22 | 2019-01-08 | Qualcomm Incorporated | Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches |
US10552153B2 (en) * | 2017-03-31 | 2020-02-04 | Intel Corporation | Efficient range-based memory writeback to improve host to device communication for optimal power and performance |
US11023162B2 (en) | 2019-08-22 | 2021-06-01 | Apple Inc. | Cache memory with transient storage for cache lines |
CN113918081B (zh) | 2020-07-08 | 2024-03-26 | 慧荣科技股份有限公司 | 计算机可读取存储介质、配置可靠命令的方法及装置 |
TWI771707B (zh) * | 2020-07-08 | 2022-07-21 | 慧榮科技股份有限公司 | 組態可靠命令的方法及裝置以及電腦程式產品 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0354649A (ja) * | 1989-07-24 | 1991-03-08 | Oki Electric Ind Co Ltd | バッファ記憶制御方式 |
JPH0448358A (ja) * | 1990-06-18 | 1992-02-18 | Nec Corp | キャッシュ・メモリ制御方式 |
JPH08137748A (ja) * | 1994-11-08 | 1996-05-31 | Toshiba Corp | コピーバックキャッシュを有するコンピュータ及びコピーバックキャッシュ制御方法 |
EP0738977B1 (en) * | 1995-03-31 | 2002-07-03 | Sun Microsystems, Inc. | Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system |
JP4434534B2 (ja) * | 2001-09-27 | 2010-03-17 | 株式会社東芝 | プロセッサ・システム |
JP2003177963A (ja) * | 2001-12-12 | 2003-06-27 | Hitachi Ltd | ストレージ装置 |
US6968429B2 (en) * | 2003-02-20 | 2005-11-22 | Sun Microsystems, Inc. | Method and apparatus for controlling line eviction in a cache |
US8214601B2 (en) * | 2004-07-30 | 2012-07-03 | Hewlett-Packard Development Company, L.P. | Purging without write-back of cache lines containing spent data |
JP2006119796A (ja) * | 2004-10-20 | 2006-05-11 | Matsushita Electric Ind Co Ltd | キャッシュメモリシステムおよび動画処理装置 |
US7461209B2 (en) * | 2005-12-06 | 2008-12-02 | International Business Machines Corporation | Transient cache storage with discard function for disposable data |
US20090006668A1 (en) * | 2007-06-28 | 2009-01-01 | Anil Vasudevan | Performing direct data transactions with a cache memory |
US20090037661A1 (en) * | 2007-08-04 | 2009-02-05 | Applied Micro Circuits Corporation | Cache mechanism for managing transient data |
US20120047330A1 (en) * | 2010-08-18 | 2012-02-23 | Nec Laboratories America, Inc. | I/o efficiency of persistent caches in a storage system |
US20120297147A1 (en) * | 2011-05-20 | 2012-11-22 | Nokia Corporation | Caching Operations for a Non-Volatile Memory Array |
JP2014178804A (ja) * | 2013-03-14 | 2014-09-25 | Sony Corp | キャッシュ制御装置、プロセッサ、情報処理システム、および、その制御方法 |
-
2014
- 2014-04-13 US US14/251,628 patent/US20150293847A1/en not_active Abandoned
-
2015
- 2015-03-31 CN CN201580019273.3A patent/CN106170776A/zh active Pending
- 2015-03-31 EP EP15719898.7A patent/EP3132354A1/en not_active Withdrawn
- 2015-03-31 BR BR112016023745A patent/BR112016023745A2/pt not_active IP Right Cessation
- 2015-03-31 JP JP2016561316A patent/JP2017510902A/ja not_active Ceased
- 2015-03-31 KR KR1020167028125A patent/KR20160143682A/ko unknown
- 2015-03-31 WO PCT/US2015/023686 patent/WO2015160503A1/en active Application Filing
- 2015-04-10 TW TW104111685A patent/TW201604681A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
KR20160143682A (ko) | 2016-12-14 |
TW201604681A (zh) | 2016-02-01 |
CN106170776A (zh) | 2016-11-30 |
EP3132354A1 (en) | 2017-02-22 |
US20150293847A1 (en) | 2015-10-15 |
WO2015160503A1 (en) | 2015-10-22 |
JP2017510902A (ja) | 2017-04-13 |
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B08F | Application fees: application dismissed [chapter 8.6 patent gazette] |
Free format text: REFERENTE A 5A ANUIDADE. |
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B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |
Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2560 DE 28/01/2020. |
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B350 | Update of information on the portal [chapter 15.35 patent gazette] |