BR112015030158A2 - preempção de armazenamento temporário de comando intermediário para cargas de trabalho gráficas - Google Patents

preempção de armazenamento temporário de comando intermediário para cargas de trabalho gráficas

Info

Publication number
BR112015030158A2
BR112015030158A2 BR112015030158A BR112015030158A BR112015030158A2 BR 112015030158 A2 BR112015030158 A2 BR 112015030158A2 BR 112015030158 A BR112015030158 A BR 112015030158A BR 112015030158 A BR112015030158 A BR 112015030158A BR 112015030158 A2 BR112015030158 A2 BR 112015030158A2
Authority
BR
Brazil
Prior art keywords
preemption
context
graphical
workloads
temporary storage
Prior art date
Application number
BR112015030158A
Other languages
English (en)
Inventor
Navale Aditya
Chand Nalluri Hema
S Boles Jeffery
Ramadoss Murali
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015030158A2 publication Critical patent/BR112015030158A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

preempção de armazenamento temporário de comando intermediário para cargas de trabalho gráficas” trata-se de uma preempção de armazenamento temporário de comando intermediário para cargas de trabalho gráficas em um ambiente de processamento gráfico. em um exemplo, as instruções de um primeiro contexto são executadas em um processador gráfico, sendo que o primeiro contexto tem uma sequência de instruções em um armazenamento temporário endereçável e pelo menos uma das instruções é uma instrução de preempção. após a execução da instrução de preempção, a execução do primeiro contexto é interrompida antes da sequência de instruções ser concluída. um endereço é armazenado para uma instrução com a qual o primeiro contexto será retomado. o segundo contexto é executado e, após o término da execução do segundo contexto, a execução do primeiro contexto é retomada no endereço armazenado.
BR112015030158A 2013-06-29 2014-06-18 preempção de armazenamento temporário de comando intermediário para cargas de trabalho gráficas BR112015030158A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/931,915 US9659342B2 (en) 2013-06-29 2013-06-29 Mid command buffer preemption for graphics workloads
PCT/US2014/042972 WO2014209721A1 (en) 2013-06-29 2014-06-18 Mid command buffer preemption for graphics workloads

Publications (1)

Publication Number Publication Date
BR112015030158A2 true BR112015030158A2 (pt) 2017-07-25

Family

ID=52115145

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015030158A BR112015030158A2 (pt) 2013-06-29 2014-06-18 preempção de armazenamento temporário de comando intermediário para cargas de trabalho gráficas

Country Status (4)

Country Link
US (1) US9659342B2 (pt)
EP (1) EP3014437A4 (pt)
BR (1) BR112015030158A2 (pt)
WO (1) WO2014209721A1 (pt)

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US20180107728A1 (en) * 2014-12-31 2018-04-19 International Business Machines Corporation Using tombstone objects to synchronize deletes
US20180101434A1 (en) * 2014-12-31 2018-04-12 International Business Machines Corporation Listing types in a distributed storage system
US20180107398A1 (en) * 2014-12-31 2018-04-19 International Business Machines Corporation Vault synchronization within a dispersed storage network
US10126974B2 (en) * 2014-12-31 2018-11-13 International Business Machines Corporation Redistributing encoded data slices in a dispersed storage network
US10026142B2 (en) * 2015-04-14 2018-07-17 Intel Corporation Supporting multi-level nesting of command buffers in graphics command streams at computing devices
US10134103B2 (en) * 2015-10-23 2018-11-20 Qualcomm Incorporated GPU operation algorithm selection based on command stream marker
US10394468B2 (en) * 2017-02-23 2019-08-27 International Business Machines Corporation Handling data slice revisions in a dispersed storage network
US10013734B1 (en) * 2017-04-01 2018-07-03 Intel Corporation Programmable controller and command cache for graphics processors
US10761983B2 (en) * 2017-11-14 2020-09-01 International Business Machines Corporation Memory based configuration state registers
US10761751B2 (en) 2017-11-14 2020-09-01 International Business Machines Corporation Configuration state registers grouped based on functional affinity
US10698686B2 (en) 2017-11-14 2020-06-30 International Business Machines Corporation Configurable architectural placement control
US10496437B2 (en) 2017-11-14 2019-12-03 International Business Machines Corporation Context switch by changing memory pointers
US10642757B2 (en) 2017-11-14 2020-05-05 International Business Machines Corporation Single call to perform pin and unpin operations
US10664181B2 (en) 2017-11-14 2020-05-26 International Business Machines Corporation Protecting in-memory configuration state registers
US10901738B2 (en) 2017-11-14 2021-01-26 International Business Machines Corporation Bulk store and load operations of configuration state registers
US10592164B2 (en) 2017-11-14 2020-03-17 International Business Machines Corporation Portions of configuration state registers in-memory
US10558366B2 (en) 2017-11-14 2020-02-11 International Business Machines Corporation Automatic pinning of units of memory
US10635602B2 (en) 2017-11-14 2020-04-28 International Business Machines Corporation Address translation prior to receiving a storage reference using the address to be translated
US11609791B2 (en) 2017-11-30 2023-03-21 Advanced Micro Devices, Inc. Precise suspend and resume of workloads in a processing unit
CN110046114B (zh) * 2019-03-06 2020-08-14 上海熠知电子科技有限公司 基于pcie协议的dma控制器及dma数据传输方法
US11593026B2 (en) 2020-03-06 2023-02-28 International Business Machines Corporation Zone storage optimization using predictive protocol patterns

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US7173627B2 (en) * 2001-06-29 2007-02-06 Intel Corporation Apparatus, method and system with a graphics-rendering engine having a graphics context manager
US6747657B2 (en) * 2001-12-31 2004-06-08 Intel Corporation Depth write disable for zone rendering
US7493615B2 (en) * 2003-05-01 2009-02-17 Sun Microsystems, Inc. Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
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US7612783B2 (en) * 2006-05-08 2009-11-03 Ati Technologies Inc. Advanced anti-aliasing with multiple graphics processing units
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US8310492B2 (en) 2009-09-03 2012-11-13 Ati Technologies Ulc Hardware-based scheduling of GPU work
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US20130124838A1 (en) 2011-11-10 2013-05-16 Lacky V. Shah Instruction level execution preemption

Also Published As

Publication number Publication date
WO2014209721A1 (en) 2014-12-31
EP3014437A4 (en) 2017-01-11
US20150002522A1 (en) 2015-01-01
EP3014437A1 (en) 2016-05-04
US9659342B2 (en) 2017-05-23

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2675 DE 12-04-2022 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.