BR112018072407A2 - estrutura de dados comum em máquina de aprendizagem. - Google Patents

estrutura de dados comum em máquina de aprendizagem.

Info

Publication number
BR112018072407A2
BR112018072407A2 BR112018072407-6A BR112018072407A BR112018072407A2 BR 112018072407 A2 BR112018072407 A2 BR 112018072407A2 BR 112018072407 A BR112018072407 A BR 112018072407A BR 112018072407 A2 BR112018072407 A2 BR 112018072407A2
Authority
BR
Brazil
Prior art keywords
data structure
machine learning
learning data
common data
processing resource
Prior art date
Application number
BR112018072407-6A
Other languages
English (en)
Inventor
Perone Christian
Haas Carlos
Per Silveira Roberto
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Publication of BR112018072407A2 publication Critical patent/BR112018072407A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Image Analysis (AREA)
  • Advance Control (AREA)
  • Memory System (AREA)
  • Storing Facsimile Image Data (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

estrutura de dados de aprendizagem de máquina compartilhada exemplos incluem um sistema compreendendo uma memória não volátil para armazenar uma estrutura de dados de aprendizagem de máquina. exemplos acessam a estrutura de dados de aprendizagem de máquina com um primeiro recurso de processamento, e exemplos acessam a estrutura de dados de aprendizagem de máquina com um segundo recurso de processamento, o qual inclui pelo menos um núcleo de processamento gráfico, de tal maneira que a estrutura de dados de aprendizagem de máquina é um espaço de memória compartilhado do primeiro recurso de processamento e do segundo recurso de processamento.
BR112018072407-6A 2016-06-17 2016-06-17 estrutura de dados comum em máquina de aprendizagem. BR112018072407A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/038128 WO2017218009A1 (en) 2016-06-17 2016-06-17 Shared machine-learning data structure

Publications (1)

Publication Number Publication Date
BR112018072407A2 true BR112018072407A2 (pt) 2019-02-19

Family

ID=60664580

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018072407-6A BR112018072407A2 (pt) 2016-06-17 2016-06-17 estrutura de dados comum em máquina de aprendizagem.

Country Status (7)

Country Link
US (1) US11797459B2 (pt)
EP (1) EP3436929A4 (pt)
JP (1) JP6928616B2 (pt)
KR (1) KR102205087B1 (pt)
CN (1) CN109416636B (pt)
BR (1) BR112018072407A2 (pt)
WO (1) WO2017218009A1 (pt)

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Also Published As

Publication number Publication date
KR20180122741A (ko) 2018-11-13
CN109416636A (zh) 2019-03-01
KR102205087B1 (ko) 2021-01-20
CN109416636B (zh) 2023-05-26
EP3436929A1 (en) 2019-02-06
JP6928616B2 (ja) 2021-09-01
WO2017218009A1 (en) 2017-12-21
US20190130300A1 (en) 2019-05-02
JP2019525277A (ja) 2019-09-05
US11797459B2 (en) 2023-10-24
EP3436929A4 (en) 2019-10-16

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B25G Requested change of headquarter approved

Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (US)

B350 Update of information on the portal [chapter 15.35 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]