JP2017184293A - Phase voltage detection circuit and power generation controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a phase voltage detection circuit capable of detecting a phase voltage signal reliably, even when the DC bias voltage of the phase voltage signal varies due to inflow of the leakage current.SOLUTION: A phase voltage detection circuit for detecting a phase voltage signal generated in the armature coil of an AC generator includes a peak hold circuit for obtaining the envelope of the phase voltage signal by using an operational amplifier, a voltage offset circuit for shifting the output voltage from the peak hold circuit by a previously set offset amount, and a comparator for comparing the phase voltage signal and the output voltage from the voltage offset circuit, and outputting a phase voltage detection signal.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a phase voltage detection circuit applied to, for example, an automotive alternator and a power generation control device using the phase voltage detection circuit.

  In general, an AC generator for a vehicle includes a power generation control device, a field coil, an armature coil, and a rectifier. The power generation control device supplies an excitation current to the field coil and adjusts the excitation current. The generated voltage is controlled.

  At this time, the phase voltage signal generated in the armature coil is input to the power generation control device, and the phase voltage signal is detected by the phase voltage detection circuit and shaped into a digital signal. The power generation control device performs processing such as detection of the engine speed based on the phase voltage signal whose waveform has been shaped by the digital circuit.

  Normally, an AC generator for a vehicle receives a start signal from a vehicle control unit or a start signal directly linked to an ignition key via a signal line connected to the vehicle side, thereby Power generation is started by supplying an exciting current to the magnetic coil. Here, when this signal line is disconnected or grounded, an activation signal from the vehicle cannot be received when the engine is started, and power generation cannot be started.

  However, even in such a state, the vehicle alternator can start power generation by having a function capable of starting independent power generation. Specifically, even if the exciting current is not supplied to the field coil by the power generation control device, the armature coil of the vehicle alternator remains as a result of the rotation of the vehicle alternator. A minute phase voltage signal is generated by the magnetic flux. Therefore, the engine rotation state can be estimated from the phase voltage signal.

  In this case, it is necessary to detect a minute phase voltage signal due to the residual magnetic flux. Further, since the frequency of the phase voltage signal is proportional to the engine speed, it is also necessary to detect within the operating rotation range of the engine. Therefore, the phase voltage detection circuit needs to detect a phase voltage signal generated by the residual magnetic flux and having an amplitude of about 0.2 V or more and a frequency in the range of several hundred Hz.

  In addition, when a leak current is generated in the diode constituting the rectifier in a state before power generation, the leak current flows into the phase voltage detection circuit, and the DC bias voltage of the phase voltage signal increases. Here, since the leakage current changes due to manufacturing variations of diodes, contact resistance, and aging deterioration, the DC bias voltage of the phase voltage signal also changes. Therefore, the phase voltage signal cannot be detected using a fixed threshold voltage.

  Therefore, in order to solve the above-described problem, the DC bias voltage of the phase voltage signal is obtained by obtaining the envelope of the phase voltage signal using a peak hold circuit and generating the variable threshold voltage using the obtained envelope. A technique for detecting a phase voltage signal has been disclosed even if is indefinite (see, for example, Patent Document 1).

JP 2002-125398 A

  However, since a configuration using a diode in the peak hold circuit is adopted in Patent Document 1, the phase voltage signal is detected when the phase voltage signal is about 0.7 V or less, which is the forward voltage of the diode. Can not do it. As described above, the phase voltage detection circuit needs to detect a phase voltage signal having an amplitude of about 0.2 V or more. However, in a configuration using a diode, for example, the amplitude is 0.2 V and the DC bias voltage is 0. There is a problem that a phase voltage signal of 2V cannot be detected.

  Further, in Patent Document 1, since the output of the peak hold circuit does not become a complete envelope due to the time constant, the phase voltage signal and the output signal of the peak hold circuit cross each other, and the phase voltage signal can be detected by the comparator. Yes. However, in the configuration using the signal delay due to the time constant, the amplitude of the phase voltage signal to be detected cannot be set. Therefore, when the amplitude of the phase voltage signal is not necessary to be detected, there is a problem that even if the amplitude is 0.1 V, for example, it is detected.

  To summarize the contents so far, as described above, the phase voltage detection circuit needs to detect the phase voltage signal even when the leakage current flows and the DC bias voltage rises. At this time, since the amount of inflowing leakage current is indefinite, it is possible to reliably detect where the phase voltage signal is between the battery potential and the reference potential, even when there is no leakage current. A circuit configuration is required.

  However, the configuration using a diode in the peak hold circuit disclosed in Patent Document 1 has a problem that a phase voltage signal below the forward voltage of the diode cannot be detected. In order to prevent malfunction due to erroneous detection of the phase voltage signal, it is necessary to have a circuit configuration in which the amplitude of the detected phase voltage signal can be easily set at the time of circuit design, but the phase voltage detection circuit is configured with an integrated circuit. In this case, there is a problem that it is difficult to finely adjust the time constant of the circuit.

  The present invention has been made to solve the above-described problems, and reliably detects a phase voltage signal even when a leakage current flows and the DC bias voltage of the phase voltage signal fluctuates. An object of the present invention is to obtain a phase voltage detection circuit capable of performing the above.

  A phase voltage detection circuit according to the present invention is a phase voltage detection circuit for detecting a phase voltage signal generated in an armature coil of an AC generator, and a peak hold circuit for obtaining an envelope of the phase voltage signal using an operational amplifier, A voltage offset circuit that shifts the output voltage from the peak hold circuit by a preset offset amount, and a comparator that compares the phase voltage signal with the output voltage from the voltage offset circuit and outputs a phase voltage detection signal. It is provided.

According to the phase voltage detection circuit of the present invention, the peak hold circuit obtains the envelope of the phase voltage signal using an operational amplifier, and the voltage offset circuit shifts the output voltage from the peak hold circuit by a preset offset amount. The comparator compares the phase voltage signal with the output voltage from the voltage offset circuit and outputs a phase voltage detection signal.
Therefore, even when a leak current flows and the DC bias voltage of the phase voltage signal fluctuates, the phase voltage signal can be reliably detected.

It is a block diagram which shows the alternating current generator for vehicles to which the phase voltage detection circuit which concerns on Embodiment 1 of this invention was applied. It is a circuit diagram which shows the phase voltage detection circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the discharge resistance in the peak hold circuit of the phase voltage detection circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the voltage offset circuit and comparator of the phase voltage detection circuit which concern on Embodiment 1 of this invention. It is a circuit diagram which shows a general subtraction circuit. It is a timing chart which shows operation | movement of the phase voltage detection circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the phase voltage detection circuit which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the subject of the phase voltage detection circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the phase voltage detection circuit which concerns on Embodiment 3 of this invention.

  Hereinafter, preferred embodiments of a phase voltage detection circuit according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing an automotive alternator to which a phase voltage detection circuit according to Embodiment 1 of the present invention is applied. In FIG. 1, a vehicular AC generator 1 is connected to a battery 2 that is a power source for accumulating generated power.

  The vehicle alternator 1 includes a power generation control device 11, a field coil 12, an armature coil 13, and a rectifier 14, and the power generation control device 11 supplies an excitation current to the field coil 12, and the excitation current. The generated voltage is controlled by adjusting. The power generation control device 11 includes a phase voltage detection circuit 100 and a voltage control circuit 200.

  The phase voltage detection circuit 100 detects a phase voltage signal generated in the armature coil 13 and outputs a phase voltage detection signal that is a digital signal. The voltage control circuit 200 controls the gate voltage of the transistor for adjusting the exciting current of the field coil 12 based on the phase voltage detection signal from the phase voltage detection circuit 100.

  FIG. 2 is a circuit diagram showing a phase voltage detection circuit according to the first embodiment of the present invention. In FIG. 2, a phase voltage signal divided by a resistor 101 and a resistor 102 is input to the phase voltage detection circuit 100. The phase voltage detection circuit 100 includes a peak hold circuit 110, a voltage offset circuit 120, and a comparator 130.

  The peak hold circuit 110 obtains the envelope of the phase voltage signal (node A) using the operational amplifier 111, and the voltage offset circuit 120 shifts the output voltage (node B) from the peak hold circuit 110 by a preset offset amount. The comparator 130 compares the phase voltage signal with the output voltage (node C) from the voltage offset circuit 120 and outputs a phase voltage detection signal.

  As described above, the phase voltage detection circuit 100 needs to detect even when the amplitude of the phase voltage signal and the DC bias voltage are about 0.7 V or less, which is the forward voltage of the diode. Therefore, a configuration using a diode for the peak hold circuit 110 cannot be employed.

  Therefore, in the peak hold circuit 110 according to the first embodiment of the present invention, the divided phase voltage signal is connected to the inverting input terminal of the operational amplifier 111, the gate is connected to the output terminal of the operational amplifier 111, and the source is the power source. The PMOS transistor 112 is connected, and the drain is connected to the non-inverting input terminal of the operational amplifier 111. The capacitor 113 and the diode 114 are connected between the drain of the PMOS transistor 112 and the reference potential.

  Note that it is necessary to connect a discharge resistor to the reference potential at the output of the peak hold circuit 110. However, as described above, since the phase voltage detection circuit 100 needs to detect a phase voltage signal having a frequency in the range of several hundreds of Hz, the resistance value of the discharge resistor is set to a very large value, or the capacitor 113 The capacitance value needs to be very large. Here, the discharge resistor is constituted by a diode 114 for mounting in an integrated circuit.

  Here, when the potential of the node B is higher than the reference potential, only a slight reverse current flows through the diode 114, so that the diode 114 can be used as a high resistance. Further, by using the diode 114 as the discharge resistor, the capacitance value of the capacitor 113 can be set to a value that can be mounted on the integrated circuit. Further, as shown in FIG. 3, a higher resistance value can be realized by connecting a plurality of diodes in series.

  FIG. 4 is a circuit diagram showing a voltage offset circuit and a comparator of the phase voltage detection circuit according to the first embodiment of the present invention. In FIG. 4, the ratio of the MOS transistors constituting the input differential pair 131 of the comparator 130 is N: 1, so that the comparator 130 is compared with the envelope of the phase voltage signal that is the output of the input peak hold circuit 110. Thus, it reacts at a voltage that is reduced by a certain voltage. Therefore, the voltage offset circuit 120 and the comparator 130 can be realized as an integrated unit.

  As a voltage offset circuit, a subtraction circuit as shown in FIG. 5 is generally known. This subtraction circuit has four resistors 301 to 304 and an operational amplifier 305. The resistor 301 is connected between the offset voltage and the inverting input terminal of the operational amplifier 305, the resistor 302 is connected between the output terminal and the inverting input terminal of the operational amplifier 305, and the resistor 303 is connected to the node B and the operational amplifier 305. The resistor 304 is connected between a non-inverting input terminal of the operational amplifier 305 and a reference potential.

  As described above, it is necessary to increase the impedance of the node B, which is the output of the peak hold circuit 110, but in the configuration shown in FIG. 5, the resistor 303 and the resistor 304 act as discharge resistors. For this reason, the subtraction circuit shown in FIG. 5 cannot be employed as the voltage offset circuit 120. When the subtracting circuit shown in FIG. 5 is used as the voltage offset circuit 120, it is necessary to insert a buffer amplifier between the voltage offset circuit 120 and the peak hold circuit 110.

  In the phase voltage detection circuit 100 according to the first embodiment of the present invention, the voltage offset circuit 120 is separately mounted by adopting the comparator 130 in which the ratio of the input differential pair is N: 1 as the voltage offset circuit 120. This eliminates the need for the circuit area. Further, by using the voltage offset circuit 120, the offset amount can be easily set at the time of circuit design, so that erroneous detection of the phase voltage signal can be prevented.

  The operation of the phase voltage detection circuit 100 having the above configuration will be described below with reference to the timing chart of FIG. FIG. 6 is a timing chart showing the operation of the phase voltage detection circuit according to the first embodiment of the present invention. Further, FIG. 6 shows operation waveforms of the phase voltage detection signal which is the node A, the node B, the node C and the output of the phase voltage detection circuit 100.

  First, the phase voltage signal input to the phase voltage detection circuit 100 is divided by the resistor 101 and the resistor 102 to form a waveform at the node A. Subsequently, the waveform of the node B is obtained as an envelope of the waveform of the node A by the peak hold circuit 110. Next, the voltage of the node B is shifted by the voltage offset circuit 120, and the waveform of the node C is obtained. The waveform at node C becomes the threshold voltage of the comparator 130.

  Since this threshold voltage fluctuates in accordance with the phase voltage signal, it becomes a variable threshold voltage, and is represented by the phase voltage signal divided by the waveform of the node A by the comparator 130 and the waveform of the node C. By comparing with the threshold voltage, the phase voltage detection signal that can be input to the digital circuit can be obtained as the output waveform regardless of the DC bias voltage of the phase voltage signal.

As described above, according to the first embodiment, the peak hold circuit obtains the envelope of the phase voltage signal using the operational amplifier, and the voltage offset circuit outputs the output voltage from the peak hold circuit by a preset offset amount. The comparator compares the phase voltage signal with the output voltage from the voltage offset circuit, and outputs a phase voltage detection signal.
Therefore, even when a leak current flows and the DC bias voltage of the phase voltage signal fluctuates, it is possible to reliably detect the phase voltage signal and start power generation.

Embodiment 2. FIG.
FIG. 7 is a circuit diagram showing a phase voltage detection circuit according to Embodiment 2 of the present invention. In FIG. 7, the phase voltage detection circuit 100A has a peak hold circuit 110A instead of the peak hold circuit 110 shown in FIG. Note that the voltage offset circuit 120 and the comparator 130 are the same as those in FIG.

  In the peak hold circuit 110A, the divided phase voltage signal is connected to the non-inverting input terminal of the operational amplifier 111, the gate is connected to the output terminal of the operational amplifier 111, the drain is connected to the power supply, and the source is the inverting input of the operational amplifier 111. An NMOS transistor 115 connected to the terminal, and a capacitor 113 and a diode 114 connected between the drain of the NMOS transistor 115 and a reference potential are included.

  Since the phase voltage detection circuit 100A needs to operate in a state before receiving an activation signal from the vehicle and starting power generation, it needs to be operated with a constant power source. That is, in the phase voltage detection circuit 100A, the circuit that detects the amplitude of the phase voltage signal and activates the internal circuit must always be operated by a power source, but the circuit for detecting the frequency of the phase voltage signal is It can be operated with an internally generated power supply. Here, the frequency of the phase voltage signal can be detected with higher accuracy by using the internally generated power supply.

  In the case of using the power supply generated internally by the peak hold circuit, when the output transistor is the PMOS transistor 112 shown in FIG. 2 of the first embodiment, as shown in FIG. There is a period during which the PMOS transistor is turned on until the gate of the transistor is charged.

  As a result, the output of the peak hold circuit rises to the power supply potential at startup. As described above, since the discharge resistance of the peak hold circuit in the present invention is high resistance, if the output voltage rises to the power supply potential, it takes time to be discharged, and during that time as a peak hold circuit Do not work.

  On the other hand, when the NMOS transistor 115 is used as the output transistor, the NMOS transistor 115 is turned off when the power source is activated, so that the output of the peak hold circuit 110A does not increase, and the peak hold circuit 110A is not activated after the power source is activated. As a result, it is possible to eliminate a period of non-operation.

Embodiment 3 FIG.
FIG. 9 is a circuit diagram showing a phase voltage detection circuit according to Embodiment 3 of the present invention. In FIG. 7, the phase voltage detection circuit 100B has a peak hold circuit 110B instead of the peak hold circuit 110A shown in FIG. Note that the voltage offset circuit 120 and the comparator 130 are the same as those shown in FIG.

  The peak hold circuit 110B has an NMOS transistor 116 instead of the diode 114 shown in FIG. The gate of the NMOS transistor 116 is controlled to a low level when operating as the peak hold circuit 110B by a refresh signal from a control circuit (not shown), and when the output of the peak hold circuit 110B is short-circuited to the reference potential, it is high. Controlled by level.

  In the phase voltage detection circuit 100A shown in FIG. 7 of the second embodiment, since the impedance of the node B that is the output of the peak hold circuit 110A is high, the voltage of the node B increases due to the influence of noise or the like. Then, it takes time to discharge, and the peak hold circuit 110A does not operate during that time.

  In contrast, in the peak hold circuit 110B according to the third embodiment of the present invention, when the gate of the NMOS transistor 116 is at the low level, the NMOS transistor 116 is turned off, and a parasitic diode between the drain and the back gate is formed. Can be used with discharge resistance.

  When the gate of the NMOS transistor 116 is at a high level, the NMOS transistor 116 is turned on, the node B and the reference potential are short-circuited, and the node B has the same potential as the reference potential. Therefore, by periodically setting the gate of the NMOS transistor 116 to High, it is possible to prevent the peak hold circuit 110B from becoming inoperable due to noise or the like.

  In addition, this invention is not limited to the said Embodiment 1-3, In the range which does not deviate from the meaning of this invention, these structures are combined suitably, a part modification is added to the structure, or a structure Can be partially omitted.

  DESCRIPTION OF SYMBOLS 1 Vehicle alternator, 2 Battery, 11 Power generation control apparatus, 12 Field coil, 13 Armature coil, 14 Rectifier, 100, 100A, 100B Phase voltage detection circuit, 101, 102 Resistance, 110, 110A, 110B Peak hold Circuit, 111 operational amplifier, 112 PMOS transistor, 113 capacitor, 114 diode, 115 NMOS transistor (first NMOS transistor), 116 NMOS transistor (second NMOS transistor), 120 voltage offset circuit, 130 comparator, 131 input differential pair, 200 voltage control Circuit, 301-304 resistor, 305 operational amplifier.

A phase voltage detection circuit according to the present invention is a phase voltage detection circuit for detecting a phase voltage signal generated in an armature coil of an AC generator, and a peak hold circuit for obtaining an envelope of the phase voltage signal using an operational amplifier, A voltage offset circuit that shifts the output voltage from the peak hold circuit by a preset offset amount, and a comparator that compares the phase voltage signal with the output voltage from the voltage offset circuit and outputs a phase voltage detection signal. The peak hold circuit has an operational amplifier with the phase voltage signal connected to the inverting input terminal, a gate connected to the output terminal of the operational amplifier, a source connected to the power supply, and a drain connected to the non-inverting input terminal of the operational amplifier. PMOS transistor and a capacitor connected between the drain of the PMOS transistor and the reference potential And and a diode, and has a.

In the peak hold circuit 110A, the divided phase voltage signal is connected to the non-inverting input terminal of the operational amplifier 111, the gate is connected to the output terminal of the operational amplifier 111, the source is connected to the power supply, and the drain is the inverting input of the operational amplifier 111. An NMOS transistor 115 connected to the terminal, and a capacitor 113 and a diode 114 connected between the drain of the NMOS transistor 115 and a reference potential are included.

Claims (7)

A phase voltage detection circuit for detecting a phase voltage signal generated in an armature coil of an AC generator,
A peak hold circuit for obtaining an envelope of the phase voltage signal using an operational amplifier;
A voltage offset circuit that shifts the output voltage from the peak hold circuit by a preset offset amount;
Comparing the phase voltage signal and the output voltage from the voltage offset circuit, and outputting a phase voltage detection signal;
A phase voltage detection circuit. The peak hold circuit is:
An operational amplifier in which the phase voltage signal is connected to an inverting input terminal;
A PMOS transistor having a gate connected to the output terminal of the operational amplifier, a source connected to a power supply, and a drain connected to the non-inverting input terminal of the operational amplifier;
A capacitor and a diode connected between the drain of the PMOS transistor and a reference potential;
The phase voltage detection circuit according to claim 1. The peak hold circuit is:
An operational amplifier in which the phase voltage signal is connected to a non-inverting input terminal;
A first NMOS transistor having a gate connected to the output terminal of the operational amplifier, a drain connected to the power supply, and a source connected to the inverting input terminal of the operational amplifier;
A capacitor and a diode connected between the drain of the first NMOS transistor and a reference potential;
The phase voltage detection circuit according to claim 1. The phase voltage detection circuit according to claim 2, wherein the diode is configured by connecting a plurality of diodes in series. The peak hold circuit is:
An operational amplifier in which the phase voltage signal is connected to a non-inverting input terminal;
A first NMOS transistor having a gate connected to the output terminal of the operational amplifier, a drain connected to the power supply, and a source connected to the inverting input terminal of the operational amplifier;
A capacitor and a second NMOS transistor connected between the drain of the first NMOS transistor and a reference potential;
The phase voltage detection circuit according to claim 1. The phase voltage detection circuit according to any one of claims 1 to 5, wherein the voltage offset circuit includes a circuit in which a ratio of an input differential pair of the comparator is N to 1.   A power generation control device comprising the phase voltage detection circuit according to any one of claims 1 to 6.

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