JPH0194268A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To achieve high speed response without generating such a situation that a peak value is not held, by constituting the title circuit so that the static comparator of a peak holding circuit always has positive offset voltage. CONSTITUTION:In a peak holding circuit, a holding capacity 9 receiving an input signal through an analogue multiplexer 7, a static comparator 6 and the output circuit connected to the capacity 9 are provided and this circuit is constituted so that the comparator 6 always has positive offset voltage. For example, when the P channel MOS transistor connected to the power supply voltage of the first branch in the differential amplifying stage therein is set to M1, the channel width and length of the transistor are set to W1 and L1, the P channel MOS transistor connected to the power supply voltage of the second branch is set to M2 and the channel width and length of the transistor are set to W2 and L2, the circuit is formed so as to satisfy W1/L1<W2/L2. As a result, it is eliminated that holding voltage becomes higher than input voltage and the lowering factor of yield can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to analog circuits, and more particularly to peak hold circuits.

2. Description of the Related Art Conventionally, a peak hold circuit including two operational amplifiers and two diodes as shown in FIG. 4 has been proposed.

The input terminal of the first operational amplifier 1 is the input voltage terminal VX
One input terminal of the first operational amplifier 1 is connected to its own output via a diode 3. The diode 3 is connected in a forward direction from one input terminal of the first operational amplifier 1 to the output of the first operational amplifier 1, that is, to the point A.

The output of the first operational amplifier 1 is connected to another diode 4
is connected to the ten input terminal of the second operational amplifier 2 through
One end of the holding capacitor 5 is connected to the input terminal of the second operational amplifier 2. The other end of the holding capacitor 5 is grounded. The diode 4 connects from point A to the connection point between the holding capacitor 5 and the input terminal of the second operational amplifier 2, that is, point B.
It is connected so that it is in the forward direction.

Furthermore, the output of the second operational amplifier 2 is an output voltage terminal V.

It is connected to the LIT, and also connected to one input terminal of itself and one input terminal of the first operational amplifier 1.

In the peak hold circuit having the above configuration, the point B holding the peak value is the output A of the operational amplifier 1.
The voltage at point B is lower than the voltage of one diode stage, so in order for point B to hold the correct peak value, operational amplifier 1 operates in response to the input peak value, and operational amplifier 2 operates in response to the input peak value. , it was necessary to apply feedback to the operational amplifier 1 so that the potential at point A becomes a voltage one diode step higher than the input peak value. However, op amp 1
．． This method is limited by a slimy rate of 2, and has the disadvantage that it cannot correctly hold the peak of a high-frequency input signal.

As a high-speed peak hold circuit that compensates for this drawback, a circuit configuration including a static comparator, an operational amplifier, an analog multiplexer (analog switch), and a holding capacitor as shown in FIG. 5 has already been proposed.

Here, the ten input terminals of the static comparator 6 are:
connected to the input terminal terminal VIN, and the input terminal terminal Vr)
l is connected to one input terminal of the static comparator 6 via the analog multiplexer 7 and also to the ten input terminal of the operational amplifier 8. The output of the static comparator 6 and the inverted output via an inverter are connected to the analog multiplexer 7 for gate opening/closing functions. A point C on the connection line between the analog multiplexer 7 and one input terminal of the static comparator 6 is connected to the other end of the holding capacitor 9 whose one end is grounded. The output of the operational amplifier 8 is the output voltage terminal V. L
It is connected to IT and also to one input terminal of the operational amplifier 8. Note that the analog multiplexer 7 is
When the output of the static comparator 6 has a positive voltage, it is opened, and when it has a negative voltage, it is closed.

According to this circuit configuration, the hold error is determined by the speed of the static comparator and the speed of the analog multiplexer, but the speed of the static comparator is significantly lower than the slew rate of the operational amplifier, which is limited by the capacitance for phase compensation. Since the speed is increased, the peak hold circuit itself can follow a higher frequency input than the circuit shown in FIG.

Problems to be Solved by the Invention However, the peak hold circuit having the circuit configuration as shown in FIG. 5 has the following drawbacks.

In order to explain this drawback, let us assume that in the static comparator 6 of this peak hold circuit, the ten input terminals have a negative offset voltage of -a [:V] with respect to the one input terminal. Suppose that a voltage of (V) is held.

At this time, if an input whose peak value is B [V] enters the peak hold circuit as shown in FIG. 6, and the input terminal is VIN Cv), the comparator 6 will be
Since the static comparator 6 has an offset of (V) = 4-, the static comparator 6 has an offset of (V, N-
A10a) Output [V]. Here, input terminal VIN
Considering the time when [v) increases, the input voltage VIN(
When V) becomes (A-a)[:V], the above (vrN-
A+a) [vE becomes 0, and the sono value takes a positive value thereafter.

Therefore, the gate of the analog multiplexer 7 is opened and the input voltage from the hold voltage is held as is. Therefore, the input voltage is the peak value B [:V]
, the hold voltage also has B [V].

Next, the input voltage starts to fall, but the input terminal (Vl
The analog multiplexer 7 will not be closed unless ll B+ a ) < 0 is satisfied, that is, unless a [V] becomes lower than the holding voltage.

The input voltage VrN[v] is changed from B[:V] to (B=a)[
During the period when the input voltage drops to V], the input voltage becomes lower than the hold voltage held in the holding capacitor 9, so the held charges conversely escape to the input side and the hold voltage decreases. When the falling speed of this hold voltage becomes equal to the falling speed of the input voltage, the static comparator 6 will always output a positive value, the analog multiplexer 7 will not close, and the output of the peak hold circuit will change to the input waveform. Since a similar waveform is output as is, the peak value will not be held.

Therefore, as mentioned above, when the 10 input terminal has a negative offset with respect to the - input terminal, a phenomenon occurs in which the peak hold circuit outputs a waveform close to the human waveform, and this phenomenon is caused by the offset voltage. depends on the size of

Thus, the peak hold circuit having the configuration shown in FIG. 5 has the disadvantage that if the static comparator has a negative offset, the yield of non-defective products in manufacturing the peak hold circuit will be lowered.

Therefore, the present invention aims to achieve high-speed response without causing a situation in which the peak value is not held in a peak hold circuit having a static comparator as shown in FIG.

Means for Solving the Problems According to the present invention, a holding capacitor receives an input signal at one end via an analog multiplexer, and one human power is connected to the one end of the holding capacitor, and the input signal is transferred to the other end. In a peak hold circuit comprising a static comparator that receives human power directly and controls the analog multiplexer by its output, and an output circuit connected to the one end of the holding capacitor, the static comparator always maintains a positive offset voltage. It is configured to have.

According to a preferred embodiment of the present invention, the static comparator in the peak hold circuit has a P-channel MO transistor connected to the power supply voltage of the first branch in the internal differential amplifier stage. Let the channel width and channel length be Wl and Ll, respectively, and let the P-channel MO3) transistor connected to the power supply voltage of the second branch in the differential amplification stage be M2, and the channel width and channel length of the transistor be W2, respectively. L
2, the configuration is such that Wl/L 1 <W2/L 2 is satisfied.

According to another preferred embodiment of the present invention, the static comparator in the peak hold circuit includes an N-channel MO3) transistor connected to one input terminal of the first branch in the internal differential amplifier stage. The channel width and channel length of the transistor are W3 and L3, respectively.
Also, the N-channel MO3) transistor connected to the second branch power supply voltage in the differential amplifier stage is M.
4. Letting the channel width and channel length of the transistor be W4 and L4, respectively, the transistor is configured to satisfy W3/L3>W4/L4.

According to yet another preferred embodiment of the present invention, the static comparator in the peak hold circuit comprises:
The P-channel MO3 transistor connected to the power supply voltage of the second branch in the internal differential amplifier stage is M2, and the channel width and channel length of this transistor are W2 and L, respectively.
2. The current flowing through the bias power supply is 11, the N-channel MOS transistor connected to the power supply voltage in the differential-to-single conversion stage inside the static comparator is M5, and the channel width and channel length of this transistor are W5, respectively. , L5, and the current flowing through the bias power supply is 12.As is clear from the explanation of the configuration above, the peak hold circuit according to the present invention has a static comparator in the peak hold circuit configured as shown in FIG. , on the contrary +b
It has a positive offset value of (V).

Under such conditions, the output of the static comparator at the time when the input voltage drops (V, -B-b) (v
) always takes a negative value when the −degree peak voltage B (V) is held in the holding capacitor 9, since Vllll E3<o, and the gate of the analog multiplexer 7 is closed.

Therefore, the above-mentioned problems do not occur.

Example The present invention will be described below with reference to the accompanying drawings.

In order to realize the peak hold circuit according to the present invention,
In the peak hold circuit shown in FIG. 5, it is only necessary to devise a circuit so that the input offset of the static comparator is always output only in a certain direction. In other words, the input terminal may have a positive offset with respect to the input terminal.

An example of the configuration of a static comparator having such an offset will be described with reference to the drawings.

The static comparator has a differential amplification stage and a differential-to-single conversion stage, as shown in FIG. On the circuit, in such a static controller,
In order to have an offset, the power supply voltage V of the paired transistors, that is, the first branch and the second branch in the differential amplification stage. P-channel MO 3) transistors M1 and M2 connected to 0, N-channel MO 3) transistors M3 and M4 connected to one input terminal and one input terminal of the first branch and second branch of the differential amplifier stage, respectively; All you have to do is make the dimension of Furthermore, the power supply voltage V at the transistor M2 and the differential-to-single conversion stage. 0
An offset is also generated by manipulating the dimensions of the N-channel MOS transistor M5 connected to.

Here, the reason why the offset occurs will be explained. First, consider the case where there is no offset on the circuit. A differential amplifier such as the one shown in FIG.

When the potential at the midpoint of 0 is applied, the potentials at points D, E, and F are also designed to be near the midpoint. With such a design, the bias states of the paired transistors will be equal, so no offset will occur. In such a case, the channel width W/channel length of each transistor M1, M2, M3, M4, and M5 is Wl/LL, W2, respectively.
They are shown in FIG. 7 as /L2, W3/L3, W4/L4, and W5/L5.

Now, if the dimensions of ML M2 are made unbalanced in this state, the channel width W of Ml is /The W/L of M2 must be increased relative to the channel length.

That is, it is necessary to satisfy Wl/LL<W2/L2 (1).

In this state, in order to make the potential of DSESF the same as the state without the offset, the potential of 10 human forces must be changed to a certain voltage b.
[V] Must be raised.

Therefore, the input terminal of this static comparator has an offset of +b (v) with respect to the - input terminal.

In order to achieve equation (1), as shown in Figure 1, the transistor after changing the dimension is set to M2'', and Ml
Let W/L of M2° be Wl/Ll, and W/L of M2° be W2°/L.
2°, L2'< Ll ・ ・(2) (However, W2'
-Wl) or W2° >Wl (3) (However, L2''=L1).

In addition, as shown in Figure 2, in order to satisfy W3/L3 > W4/L4 (4), L4"> L3 (5) (however, W4° - W
3) or W4° <W3...(6) (However, L4' - L3)
A similar result can be obtained by doing .

Yet another method will be explained below. In FIG. 7, if the current flowing through the current source 1.2 is I+, 12, then
Usually M2 and M5 are used to equalize the potentials at points D, E, and F.
The dimension of is M 5−− M 2 ・
・(6) Engineering.

It is determined that

Generally, the dimension setting is selected because it satisfies equation (6), so this case will be explained.

Here the condition to have the desired offset mentioned above is All you have to do is satisfy. That is, as shown in FIG. 3, or l2 W5°>-W2 (however, L5'=L2)I.

You can set the dimension so that

By setting the dimensions in this way, a static comparator can be designed in which the input terminal has a positive OFF and 0 voltage with respect to the - input terminal.

Effects of the Invention - If a peak hold circuit is configured using a static comparator having a positive offset voltage with respect to the input terminal, the hold voltage will never be higher than the input voltage. This makes it possible to eliminate the cause of yield decline.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams of a static comparator for implementing the present invention, FIG. 4 is a circuit diagram of a conventional peak hold circuit, and FIG. 5 is a circuit diagram of a conventional peak hold circuit. Figure 6 is a diagram of human input waveforms to the peak hold circuit, and Figure 7 is a circuit diagram of a static comparator. (Main reference numbers) 1.2.8... Operational amplifier (operational amplifier), = 15- 3.4 - Diode, 5.9... Holding capacitor, 6... Static comparator, 7... Analog multiplexer, Ml, M2, M2', M5, M5゜...P channel MO3) transistor, M3, M4, M4゜...N channel MO3) transistor

Claims (1)

[Claims] a holding capacitor that receives an input signal at one end via an analog multiplexer; one input is connected to the one end of the holding capacitor; the input signal is directly received at the other input; and the analog multiplexer is controlled by the output. A peak hold circuit comprising a static comparator and an output circuit connected to the one end of the holding capacitor, wherein the static comparator is configured to always have a positive offset voltage. circuit.