JP2010057264A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC-DC converter wherein when an output short circuit protection function is provided, an internal circuit (internal element) can be protected without externally providing a bypass circuit for bypassing a short circuit current. <P>SOLUTION: The DC-DC converter that boosts a DC voltage to generate an output voltage is obtained by connecting multiple MOS transistors M1 to M4 between an input terminal 1 and an output terminal 2 for generating this output voltage. The MOS transistor M4 includes MOS transistors M41, M42 for controlling its own substrate potential. When the DC-DC converter is in steady-state operation, the MOS transistor M42 is turned on and the potential at the output terminal 2 is applied to the substrate terminal of the MOS transistor M4. When the output of the DC-DC converter is short-circuited, the MOS transistor M41 is turned on and the potential on the opposite side to the output terminal 2 is applied to the substrate terminal of the MOS transistor M4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a charge pump type DC-DC converter.

Conventionally, a circuit having a configuration shown in FIG. 7 is known as an example of this type of DC-DC converter.
The DC-DC converter of FIG. 7 is a positive direction quadruple booster circuit that boosts the input voltage VIN of the DC power supply 4 applied to the input terminal 1 four times and outputs the boosted voltage from the output terminal 2. The voltage VOUT is output.
For this reason, the DC-DC converter of FIG. 7 includes MOS transistors M1 to M8 that are switching transistors, boosting capacitors C1 to C3, an output capacitor CO, and an inverter 3, as illustrated. . Here, the MOS transistors M1 to M4, M5, and M7 are P-type MOS transistors, and the MOS transistors M6 and M8 are N-type MOS transistors.

The MOS transistors M2, M4, M5, and M6 are turned on / off by the clock signal CLK. The MOS transistors M1, M3, M7, and M8 are turned on / off by an inverted signal obtained by inverting the clock signal CLK by the inverter 3.
In the DC-DC inverter of FIG. 7 having such a configuration, the operations in the first period and the second period are alternately repeated.
That is, in the first period, the MOS transistors M1, M3, M6, and M7 are turned on, and the MOS transistors M2, M4, M5, and M8 are turned off. On the other hand, in the second period, the MOS transistors M2, M4, M5, and M8 are turned on, and the MOS transistors M1, M3, M6, and M7 are turned off.

Therefore, in the first period, the capacitor C1 is charged by the input voltage VIN (for example, 5V), and the charging voltage 5V becomes the terminal voltage C1P of the capacitor C1. At this time, the capacitor C2 has become 10V due to the previous charging, and the input voltage 5V is added to this to become 15V. This 15V is charged in the capacitor C3, and the charging voltage 15V becomes the terminal voltage C3P.
On the other hand, in the second period, the voltage 5V of the capacitor C1 is added to the input voltage 5V, and the terminal voltage C1P of the capacitor C1 becomes 10V, thereby charging the capacitor C2 to 10V. At this time, the capacitor C3 is 15V due to the previous charging, and the input voltage 5V is added to this to become 20V, and this 20V becomes the output voltage VOUT of the output terminal 2.

By the way, in the DC-DC converter of FIG. 7, MOS transistors M1 to M4 are connected in series between the input terminal 1 and the output terminal. Further, the MOS transistors M1 to M4 have parasitic diodes D1 to D4 between the drain terminal and the substrate terminal as shown in the figure.
For this reason, for example, even if the MOS transistors M1 to M4 are in the off state, if the output terminal 2 is short-circuited for some reason, the parasitic diodes D1 to D4 are in the forward connection state and the input terminal 1 and the output terminal 2 are connected. In other words, an excessive current flows in a circuit (specifically, an integrated circuit). For this reason, it is considered that aluminum wiring is blown out or the device is destroyed.

In order to solve such a problem, for example, the invention described in Patent Document 1 is known.
The invention described in Patent Document 1 is a constant voltage circuit having a short-circuit protection circuit having a U-shaped characteristic at the front stage of a charge pump circuit when a load connected to the output terminal of the charge pump circuit is short-circuited to a ground voltage. And a switching circuit that bypasses the short-circuit current flowing in the charge pump circuit.
However, in the invention described in Patent Document 1, it is necessary to provide a constant voltage circuit having a short-circuit protection circuit having a U-shaped characteristic at the front stage of the charge pump circuit, and the load connected to the output terminal of the charge pump circuit is When short-circuiting to the ground voltage, it is necessary to provide a circuit for bypassing the short-circuit current outside the charge pump circuit. For this reason, a bypass wiring is required.
JP-A-5-276011

  Accordingly, an object of the present invention is to provide a bypass for bypassing a short-circuit current without providing a constant voltage circuit having a short-circuit protection circuit having a U-shaped characteristic before the charge pump circuit when providing an output short-circuit protection function. An object of the present invention is to provide a DC-DC converter capable of protecting an internal circuit (internal element) without providing a circuit outside.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
In the first invention, a DC voltage is boosted to generate an output voltage, and N (N is an integer of 2 or more) switching transistors are connected in series between the input terminal and the output terminal to generate the output voltage. In the connected DC-DC converter, the N switching transistors have a parasitic diode structure between a drain terminal or a source terminal and a substrate terminal, and (N−M) (N−M) of the N switching transistors ( M is an integer greater than or equal to 1), the switching transistor has a parasitic diode whose anode is on the input terminal side and whose cathode is on the output terminal side, or (N−M) of the N switching transistors The switching transistor (M is an integer of 1 or more) has a cathode on the input terminal side and an anode on the output terminal side. A raw diodes, the substrate terminal of the M switching transistor, the first potential is applied to the steady state operation, the second potential is adapted to be applied at the time of output shorting.

According to a second aspect of the present invention, in the first aspect, the M switching transistors include a first transistor that selects the first voltage during steady operation as its own substrate potential, and a second voltage when its output is short-circuited as its own substrate potential. And a second transistor for selecting.
According to a third invention, in the second invention, the detection means for detecting either a steady operation state or an output short-circuit state based on the output voltage of the output terminal, and when the detection means detects a steady operation state, Control means for turning on the first transistor and turning on the second transistor when the detecting means detects an output short-circuit state.

In a fourth aspect based on the third aspect, the detection means divides the output voltage to output a divided voltage, and compares the divided voltage of the voltage dividing means with a reference voltage. Based on the comparison result, the output of the output short circuit signal in the output short circuit state, and the output duration of the output short circuit signal output from the comparison means, and when the measured value is greater than or equal to a predetermined value Measuring means for outputting a signal for turning on the second transistor.
According to a fifth invention, in the second invention, a detection means for detecting an output short-circuit state based on an output current flowing through the output terminal, and the first transistor is turned on when the detection means does not detect an output short-circuit state. And a control means for turning on the second transistor when the detection means detects an output short-circuit state.

In a sixth aspect based on the fifth aspect, the detection means compares the output voltage of the current sensor amplifier with a current sense amplifier that converts an output current flowing through the output terminal into a voltage, and compares the output voltage with a reference voltage. Based on the result, the comparison means for outputting the output short circuit signal in the output short circuit state, and the output duration of the output short circuit signal output from the comparison means are measured, and when the measured value is a predetermined value or more, the first Measuring means for outputting a trigger signal for turning on the two transistors, and a latch for generating and holding a signal for turning on the second transistor from the trigger signal for turning on the second transistor output from the measuring means A circuit.
According to the present invention having such a configuration, when the output short-circuit protection function is provided, it is not necessary to provide a constant voltage circuit having a short-circuit protection circuit having a U-shaped characteristic before the charge pump circuit, and a short-circuit current can be reduced. An internal circuit (internal element) can be protected without providing a bypass circuit for bypassing outside.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
The DC-DC converter according to the first embodiment of the present invention is based on the circuit shown in FIG. 7, and an output short circuit protection function as shown in FIG. 1 is added to the circuit shown in FIG.
FIG. 1 shows only a part of MOS transistors M1 to M4 which are switching transistors connected in series between the input terminal 1 and the output terminal 2 of the DC-DC converter of FIG. Output short circuit protection function has been added.
Therefore, in the first embodiment, the MOS transistor M4 includes MOS transistors M41 and M42 for controlling the substrate potential so that the substrate potential supplied to the MOS transistor M4 can be changed (controlled) according to the presence or absence of an output short circuit. ing.
Further, in the first embodiment, in order to perform on / off control of the MOS transistors M41 and M42 according to the output short circuit, as shown in FIG. 1, an output voltage detection circuit 11, a comparator (comparison circuit) 12, a NAND A circuit (NAND circuit) 13 and a substrate potential control circuit 14 are provided.

The output voltage detection circuit 11 is a circuit that detects the output voltage VOUT, and divides the output voltage VOUT by the voltage dividing resistors R1 and R2. This divided voltage is supplied to the inverting input terminal (− terminal) of the comparator 12.
The comparator 12 compares the divided voltage of the output voltage detection circuit 11 with the reference voltage VR, and outputs the H level when the divided voltage is equal to or lower than the reference voltage VR, that is, when the output of the DC-DC converter is short-circuited. The comparator 12 outputs an L level when the divided voltage is equal to or higher than the reference voltage VR, that is, in the case of a steady operation (normal boosting operation) rather than an output short circuit.
The NAND circuit 13 controls the output signal of the comparator 12 by the soft start period end signal. The soft start period end signal is a signal that is at the L level only during the soft start period T1 when the DC-DC converter is activated, and becomes the H level after the soft start period T1 has elapsed. Therefore, the output signal of the NAND circuit 13 becomes L level when the output signal of the DC-DC converter is short-circuited and the output signal of the comparator 12 becomes H level after the elapse of the soft start period T1.

The substrate potential control circuit 14 selectively turns on the MOS transistors M41 and M42 based on the output signal of the NAND circuit 13. That is, the substrate potential control circuit 14 turns on the MOS transistor M42 during the soft start period T1. After the soft start period T1, the MOS transistor M41 is turned on when the output signal of the comparator 12 is at the H level and the DC-DC converter is short-circuited. Thereby, the potential of the source terminal of the MOS transistor M3 is applied to the substrate terminal (substrate terminal) of the MOS transistor M4.
On the other hand, when the output signal of the comparator 12 is at L level and the DC-DC converter is in a steady operation, the MOS transistor M42 is turned on. Thereby, the potential of the output terminal 2 is applied to the substrate terminal of the MOS transistor M4.

Next, a specific circuit configuration of the substrate potential control circuit 14 will be described with reference to FIG.
As shown in FIG. 2, the substrate potential control circuit 14 includes MOS transistors M11 and M12, resistors R3 and R4, and an inverter 141.
A signal obtained by inverting the output signal of the NAND circuit 13 by the inverter 141 is supplied to the gate of the MOS transistor M11. The source of the MOS transistor M11 is grounded. The drain of the MOS transistor M11 is connected to the gate of the MOS transistor M41, and the output voltage VOUT is applied via the resistor R3.
The output signal of the NAND circuit 13 is supplied to the gate of the MOS transistor M12. The source of the MOS transistor M12 is grounded. The drain of the MOS transistor M12 is connected to the gate of the MOS transistor M42, and the output voltage VOUT is applied via the resistor R4.

Next, the structure of the MOS transistor M4 and the MOS transistors M41 and M42 will be described with reference to FIG.
An N-type well region 302 is formed on the surface of a P-type semiconductor substrate 301. In this N-type well region 302, a MOS transistor M4 and MOS transistors M41 and M42 are formed, and a potential is supplied to the N-type well region 302. A high-concentration N + region 303.
The MOS transistor M4 includes a high concentration P + region 304, a high concentration P + region 305, and a gate electrode 306. The MOS transistor M41 includes a drain of the high concentration P + region 307, a source of the high concentration P + region 308, and a gate electrode 309. The MOS transistor M42 includes a drain of the high concentration P + region 310, a source of the high concentration P + region 308, and a gate electrode 311.

Next, an operation example of the first embodiment will be described with reference to FIG. 1, FIG. 2, FIG.
Now, when the DC-DC converter according to the first embodiment is activated, the soft start period end signal supplied to the NAND circuit 13 becomes L level with the start of activation, and this L level becomes the soft start period T1. Will only continue.
During the soft start period T1, regardless of the output signal of the comparator 12, the output signal of the NAND circuit 13 is at the H level during the soft start period T1 because the soft start period end signal is at the L level. Therefore, since the MOS transistor M12 of the substrate voltage control circuit 14 shown in FIG. 2 is turned on, the MOS transistor M42 is turned on. The equivalent circuit of the MOS transistor M4 at this time is in a state as shown in FIG.

When the soft start period T1 elapses, the soft start period end signal changes from the L level to the H level, and thereafter maintains the H level.
The comparator 12 compares the divided voltage of the output voltage detection circuit 11 with the reference voltage VR and outputs an output signal corresponding to the comparison result. That is, the comparator 12 outputs an L level in the case of steady operation when the divided voltage is equal to or higher than the reference voltage VR. On the other hand, when the divided voltage is equal to or lower than the reference voltage VR, that is, when the output is short-circuited, the H level is output.
The output signal of the NAND circuit 13 is H level when the output signal of the comparator 12 is L level and the DC-DC converter is in steady operation. Therefore, since the MOS transistor M12 of the substrate voltage control circuit 14 shown in FIG. 2 is turned on, the MOS transistor M42 is turned on. The equivalent circuit of the MOS transistor M4 at this time is in a state as shown in FIG. 4A, and the potential of the output terminal 2 is applied to the substrate terminal of the MOS transistor M4.

Thus, when the DC-DC converter is in a steady operation, the direction of the parasitic diode D4 of the MOS transistor M4 is the same as the direction of the parasitic diodes D1 to D3 of the MOS transistors M1 to M3. Therefore, the MOS transistor M4 can perform a boosting operation similarly to the MOS transistors M1 to M3.
On the other hand, the output signal of the NAND circuit 13 is L level when the output signal of the comparator 12 is H level and the output of the DC-DC converter is short-circuited. Therefore, since the MOS transistor M11 of the substrate voltage control circuit 14 shown in FIG. 2 is turned on, the MOS transistor M41 is turned on. The equivalent circuit of the MOS transistor M4 at this time is in a state as shown in FIG. 4B, and the substrate terminal of the MOS transistor M4 is connected to the terminal opposite to the output terminal 2.

Thereby, when the output of the DC-DC converter is short-circuited, the parasitic diodes D1 to D3 of the MOS transistors M1 to M3 among the MOS transistors M1 to M4 constituting the internal circuit of the DC-DC converter are connected in the forward direction. However, since the parasitic diode D4 of the MOS transistor M4 is connected in the reverse direction, a short-circuit current can be prevented from flowing into the IC due to the parasitic structure of the switching transistor.
As described above, according to the first embodiment, when the output short circuit protection function is provided, it is not necessary to provide a bypass circuit for bypassing the short circuit current flowing inside, and the internal circuit (internal element) is protected. Can do.
Further, in the first embodiment, it is not necessary to provide a constant voltage circuit having a short circuit protection circuit having a U-characteristic in front of the charge pump circuit, so that an area corresponding to the output short circuit protection function is not required. Thus, an output short-circuit protection function can be realized with a small area and a low cost.

(Second Embodiment)
The DC-DC converter according to the second embodiment of the present invention is based on the circuit shown in FIG. 7, and an output short-circuit protection function as shown in FIG. 5 is added to this circuit.
The second embodiment is different from the configuration of the first embodiment in FIG. 1 in that the first embodiment detects the output short circuit using the output voltage VOUT of the output terminal 2 whereas the second embodiment. In the embodiment, the output short circuit is detected by using the current I flowing through the output terminal 2.
Therefore, in the second embodiment, in order to perform on / off control of the MOS transistors M41 and M42 according to the output short circuit, as shown in FIG. 5, a current detection circuit 15, a NAND circuit (NAND circuit) 13, and a short circuit are provided. A detection signal holding circuit 16 and a substrate potential control circuit 14 are provided.

That is, in the second embodiment, the output voltage detection circuit 11 and the comparator 12 in FIG. 1 are replaced with the current detection circuit 15 in FIG. The same components are denoted by the same reference numerals, and description thereof is omitted as much as possible.
The current detection circuit 15 detects the current flowing through the output terminal 2, that is, the current I flowing through the current detection resistor R5 connected between the output terminal 2 and the MOS transistor M4. When the detected current I is not more than a predetermined value and the DC-DC converter is in a steady operation, an L level output signal is output. On the other hand, when the detected current I is equal to or greater than a predetermined value and the DC-DC converter is short-circuited, an H level output signal is output.

The NAND circuit 13 controls the output signal of the current detection circuit 15 by the soft start period end signal. The soft start period end signal is a signal that is at the L level only during the soft start period T1 when the DC-DC converter is activated, and becomes the H level after the soft start period T1 has elapsed. For this reason, the output signal of the NAND circuit 13 becomes L level when the output signal of the DC-DC converter is short-circuited after the soft start period T1 and the output signal of the current detection circuit 15 becomes H level.
The short circuit detection signal holding circuit 16 has a latch circuit configuration, and outputs an H level output to the substrate potential control circuit 14 during the soft start period. After the soft start period, when the output of the NAND circuit 13 is at the H level, the H level output is output to the substrate potential control circuit 14. When the output terminal 2 is short-circuited and a short-circuit current flows and the output of the NAND circuit 13 becomes L level, an L level output is output to the substrate potential control circuit 14. Even if the short circuit current stops flowing and the output of the NAND circuit 13 returns to the H level, the short circuit detection signal holding circuit 16 maintains the L level output and continues to output to the substrate potential control circuit 14.

  The substrate potential control circuit 14 selectively turns on the MOS transistors M41 and M42 based on the output signal of the short circuit detection signal holding circuit 16. That is, the substrate potential control circuit 14 turns on the MOS transistor M41 when the output signal of the short-circuit detection signal holding circuit 16 is at L level and the DC-DC converter is short-circuited. Further, when the output signal of the output signal of the short circuit detection signal holding circuit 16 is at the H level and the DC-DC converter is in a steady operation, the MOS transistor M42 is turned on.

Next, a specific configuration of the current detection circuit 15 will be described with reference to FIG.
As shown in FIG. 6, the current detection circuit 15 includes a current sense amplifier 151 and a comparator 152.
The current sense amplifier 151 converts the current I flowing through the current detection resistor R5 into a voltage value, amplifies the converted voltage, and outputs an output voltage. For this reason, the two input terminals of the current sense amplifier 151 are connected to both ends of the current detection resistor R5. The output voltage of the current sense amplifier 151 is supplied to the non-inverting input terminal (+ input terminal) of the comparator 152.

The current sense amplifier 151 having such a configuration has an output voltage in a predetermined range when the DC-DC converter is in a steady operation, and an excessive short-circuit current flows when the DC-DC converter is short-circuited in output, resulting in an output voltage. It is considerably larger than the predetermined range.
The comparator 152 compares the output voltage of the current sense amplifier 151 with the reference voltage VR, and outputs an H level when the output voltage is equal to or higher than the reference voltage VR, that is, when the output is short-circuited. The comparator 152 outputs an L level when the output voltage is equal to or lower than the reference voltage VR, that is, when the output is not a short circuit but a steady operation.
According to the second embodiment as described above, the same operation and effect as the first embodiment can be realized.

(Modification of the first and second embodiments)
Next, a modification of the first embodiment will be described with reference to FIG.
In the modification of the first embodiment, a measurement circuit is provided between the output terminal of the comparator 12 and the input terminal of the NAND circuit 13 in FIG.
This measurement circuit measures the duration of a signal when an H level signal is output as an output signal from the comparator 12, that is, when an H level signal indicating an output short circuit is output from the comparator 12. When the measured value becomes equal to or greater than a predetermined value, an H level signal is output.
For this reason, according to the modification of the first embodiment, the output potential short circuit is reliably detected without being affected by the noise of the output voltage of the DC-DC converter, and the substrate potential control circuit 14 is detected when the output short circuit is detected. The MOS transistor M41 can be turned on.

Next, a modification of the second embodiment will be described with reference to FIG.
In the modification of the second embodiment, a measurement circuit is provided between the output terminal of the current detection circuit 15 and the input terminal of the NAND circuit 13 shown in FIG.
When the H level signal is output as the output signal from the current detection circuit 15, that is, when the H level signal indicating the output short circuit is output from the current detection circuit 15, the measurement circuit The duration time is measured, and when the measured value becomes a predetermined value or more, an H level signal is output.
Therefore, according to the modification of the second embodiment, the output potential short circuit is reliably detected without being affected by the noise of the output voltage of the DC-DC converter, and the substrate potential control circuit 14 is detected when the output short circuit is detected. The MOS transistor M41 can be turned on.

(Other embodiments)
In the above embodiment, the output short circuit protection function is provided only for the MOS transistor M4 among the MOS transistors M1 to M4 connected in series between the input terminal 1 and the output terminal 2 of the DC-DC converter.
However, the output short-circuit protection function may be provided in any one of the MOS transistors M1 to M4. Moreover, you may provide in predetermined 2 or more of MOS transistor M1-M4. In this case, the substrate potential control circuit 14 may be added according to the number (see FIG. 1).
In the above embodiment, the case of the positive quadruple boost circuit has been described. However, the present invention can also be applied to a case of positive double boost or positive triple boost.

In the above-described embodiment, the case of the positive booster circuit using the P-channel transistor connected in series between the input terminal VIN and the output terminal VOUT has been described. However, it is connected in series between the input terminal VIN and the output terminal VOUT. The present invention can also be applied to a negative booster circuit using N-channel transistors.
In this case, the N-channel transistor has a parasitic diode structure between the drain terminal and the substrate terminal, and the direction of the parasitic diode is opposite to the direction of the parasitic diode of the P-channel transistor of the above embodiment.

It is a figure which shows the structure of the part which concerns on the output short circuit protection function of 1st Embodiment of the DC-DC converter of this invention. It is a circuit diagram which shows the specific example of a substrate potential control circuit. It is sectional drawing which shows the structural example of MOS transistor M4 and MOS transistor M41, M42. It is an equivalent circuit when the MOS transistor M4 operates. It is a figure which shows the structure of the part which concerns on the output short circuit protection function of 2nd Embodiment of the DC-DC converter of this invention. It is a circuit diagram which shows the specific example of a current detection circuit. It is a circuit diagram which shows an example of a conventional apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Output terminal, 11 ... Output voltage detection circuit, 12 ... Comparator, 13 ... NAND circuit, 14 ... Substrate potential control circuit, 15 ... Current Detection circuit, M1 to M4... MOS transistors for switching, M41, M42... MOS transistors for substrate potential control.

Claims (6)

DC-DC in which DC voltage is boosted to generate an output voltage, and N switching transistors (N is an integer of 2 or more) are connected in series between the input terminal and the output terminal to generate the output voltage. In the converter
The N switching transistors have a parasitic diode structure between a drain terminal or a source terminal and a substrate terminal,
Of the N switching transistors, (N−M) (M is an integer of 1 or more) switching transistors include a parasitic diode having an anode on the input terminal side and a cathode on the output terminal side,
Alternatively, (N−M) (M is an integer greater than or equal to 1) of the N switching transistors includes a parasitic diode having a cathode on the input terminal side and an anode on the output terminal side. ,
A DC-DC converter, wherein a first potential is applied to substrate terminals of the M switching transistors during a steady operation, and a second potential is applied when an output is short-circuited. The M switching transistors are:
A first transistor that selects a first voltage during steady operation as its own substrate potential;
A second transistor that selects a second voltage when the output is short-circuited as its own substrate potential;
The DC-DC converter according to claim 1, comprising: Detecting means for detecting either a steady operation state or an output short circuit state based on the output voltage of the output terminal;
Control means for turning on the first transistor when the detection means detects a steady operation state, and turning on the second transistor when the detection means detects an output short-circuit state;
The DC-DC converter according to claim 2, further comprising: The detection means includes
Voltage dividing means for dividing the output voltage and outputting a divided voltage;
Comparing means for comparing the divided voltage of the voltage dividing means with a reference voltage, and outputting an output short circuit signal in the case of an output short circuit state based on the comparison result;
Measuring means for measuring the output duration of the output short circuit signal output from the comparing means, and outputting a signal for turning on the second transistor when the measured value is equal to or greater than a predetermined value;
The DC-DC converter according to claim 3, further comprising: Detecting means for detecting an output short circuit state based on an output current flowing through the output terminal;
Control means for turning on the first transistor when the detection means does not detect an output short-circuit state, and turning on the second transistor when the detection means detects an output short-circuit state;
The DC-DC converter according to claim 2, further comprising: The detection means includes
A current sense amplifier that converts an output current flowing through the output terminal into a voltage;
Comparing means for comparing the output voltage of the current sensor amplifier with a reference voltage, and outputting an output short-circuit signal when the output is short-circuited based on the comparison result;
Measuring means for measuring an output continuation time of the output short-circuit signal output from the comparing means, and outputting a trigger signal for turning on the second transistor when the measured value is a predetermined value or more;
A latch circuit that generates and holds a signal for turning on the second transistor from a trigger signal for turning on the second transistor output from the measuring means;
The DC-DC converter according to claim 5, comprising:

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