JP2017077138A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the influence of output fluctuation in a charge pump circuit.SOLUTION: A semiconductor device 100 comprises: a charge pump circuit 4 for generating a boosting voltage VCP higher than a power supply voltage Vbb; a smoothing circuit 15 for smoothing the boosting voltage VCP to generate a smoothed boosting voltage VCP2; and a post-stage circuit (e.g., overcurrent protection circuit 13) which operates when receiving supply of the smoothed boosting voltage VCP2. The smoothing circuit 15 includes: a current mirror 151 for generating a charging current Ic which fluctuated in a behavior similar to the boosting voltage VCP; and a capacitor 152 for outputting a charging voltage Vc corresponding the charging current Ic as a smoothed boosting voltage VCP.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a semiconductor device provided with a charge pump circuit.

  Conventionally, a charge pump circuit has been widely used as a means for generating a boosted voltage higher than an input voltage.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2008-017596 A

  However, the output of the charge pump circuit varies depending on the driving frequency of the flying capacitor when the output rises (starts up). Therefore, there is room for improvement in the operation accuracy of the subsequent circuit that receives the boosted voltage.

  An object of the invention disclosed in this specification is to provide a semiconductor device capable of reducing the influence of output fluctuations in a charge pump circuit in view of the above-mentioned problems found by the inventors of the present application. .

  A semiconductor device disclosed in the present specification includes a charge pump circuit that generates a boosted voltage higher than a power supply voltage, a smoothing circuit that smoothes the boosted voltage to generate a smoothed boosted voltage, and the smoothed boosted voltage And a post-stage circuit that operates in response to the supply, and the smoothing circuit generates a charging current that fluctuates in the same manner as the boosted voltage, and the smoothing booster boosts the charging voltage according to the charging current. And a capacitor that outputs as a voltage (first configuration).

  In the semiconductor device having the first configuration, the current mirror includes a first PMOSFET [P-channel type metal whose source is connected to the input terminal of the boosted voltage and whose drain and gate are connected to the input terminal of the reference current. -oxide-semiconductor field effect transistor] and a second PMOSFET having a source connected to the input terminal of the boosted voltage, a gate connected to the gate of the first PMOSFET, and a drain connected to the capacitor (first 2).

  In the semiconductor device having the first or second configuration, the subsequent circuit monitors whether the monitoring target current is in an overcurrent state and generates an overcurrent protection signal corresponding to the monitoring result. A configuration that is a protection circuit (third configuration) is preferable.

  In the semiconductor device having the third configuration, the overcurrent protection circuit compares the sense voltage corresponding to the monitored current with a predetermined threshold voltage to generate the overcurrent protection signal (fourth). (Configuration).

  In the semiconductor device having the fourth configuration, the overcurrent protection circuit generates a constant current generator that generates a predetermined first current, and generates a second current and a third current according to the first current. A current mirror section; a first NMOSFET [N-channel type MOSFET] whose drain and gate are connected to the input terminal of the second current; and a resistor whose one end is connected to the source of the first NMOSFET to generate the threshold voltage; A second NMOSFET having a drain connected to the input terminal of the third current and an output terminal of the overcurrent protection signal, a gate connected to the gate of the first NMOSFET, and a source connected to the input terminal of the sense voltage. It may be configured to include (fifth configuration).

  Further, in the semiconductor device having the fifth configuration, the constant current generation unit receives a supply of the smoothed boosted voltage and generates a constant voltage, and converts the constant voltage into the first current. The voltage / current conversion unit may be included (sixth configuration).

  In addition, the semiconductor device having any one of the third to sixth configurations includes a gate control circuit that generates a gate voltage upon receiving the boosted voltage, and a continuity between a power source and a load according to the gate voltage. A configuration (seventh configuration) further including an N-channel high-side switch to be blocked is preferable.

  In the semiconductor device having the seventh configuration, the overcurrent protection circuit monitors an output current flowing through the high-side switch or a mirror current corresponding to the output current as the monitoring target current, and the gate control circuit The gate signal may be controlled (eighth configuration) so that the high-side switch is forcibly turned off when the overcurrent protection signal is at a logic level at the time of overcurrent detection.

  In addition, the electronic device disclosed in this specification is configured to have a semiconductor device having an eighth configuration (ninth configuration).

  Further, the vehicle disclosed in the present specification has a configuration (tenth configuration) including a battery and an electronic device having a ninth configuration that operates by receiving supply of a power supply voltage from the battery. ing.

  According to the semiconductor device disclosed in this specification, the influence of output fluctuations in the charge pump circuit can be reduced, so that it is possible to improve the operation accuracy of the subsequent circuit that receives the boosted voltage.

Block diagram showing the overall configuration of a semiconductor device Circuit diagram showing a first embodiment of a charge pump circuit Circuit diagram showing charge pump operation of first embodiment (first phase) Circuit diagram showing charge pump operation of first embodiment (second phase) Circuit diagram showing a second embodiment of the charge pump circuit Circuit diagram showing charge pump operation of second embodiment (first phase) Circuit diagram showing charge pump operation of second embodiment (second phase) Circuit diagram showing an example of the latter stage configuration of the charge pump circuit External view showing a configuration example of a vehicle

<Semiconductor device>
FIG. 1 is a block diagram showing the overall configuration of the semiconductor device. The semiconductor device 100 of this configuration example is an in-vehicle high-side switch IC, and has a plurality of external terminals (IN pin, GND pin, OUT pin, ST pin, VBB) as means for establishing electrical connection with the outside of the device. Pin). The IN pin is an input terminal for receiving an external input of a control signal from a CMOS logic IC or the like. The GND pin is a ground terminal. The OUT pin is an output terminal to which a load (an engine control ECU [electronic control unit], an air conditioner, a body device, etc.) is externally connected. The ST pin is an output terminal for outputting a self-diagnosis signal to a CMOS logic IC or the like. The VBB pin is a power supply terminal for receiving supply of a power supply voltage Vbb (for example, 4.5V to 18V) from the battery. Note that a plurality of VBB pins may be provided in parallel (for example, 4-pin parallel) in order to flow a large current.

  The semiconductor device 100 of this configuration example includes an internal power supply circuit 1, a constant voltage generation circuit 2, an oscillation circuit 3, a charge pump circuit 4, a logic circuit 5, a gate control circuit 6, and a clamp circuit 7. , Input circuit 8, reference generation circuit 9, temperature protection circuit 10, voltage drop protection circuit 11, open protection circuit 12, overcurrent protection circuit 13, N-channel MOS field effect transistors N1 to N3, Resistors R1 and R2, a sense resistor Rs, and Zener diodes Z1 and Z2 are integrated.

  The internal power supply circuit 1 is connected between the VBB pin and the GND pin, generates a predetermined internal power supply voltage VREG from the power supply voltage Vbb, and supplies it to each part of the semiconductor device 100. The internal power supply circuit 1 is controlled to be operable according to the logic level of the enable signal EN. More specifically, the internal power supply circuit 1 is in an operating state when the enable signal EN is at a logic level (eg, high level) when enabled, and is at a logic level (eg, low level) when the enable signal EN is disabled. It becomes a stop state when it is.

  The constant voltage generation circuit 2 is connected between the VBB pin and the GND pin, and only a high voltage VH (= power supply voltage Vbb) corresponding to the power supply voltage Vbb and only a constant voltage REF (= 5 V, for example) than the high voltage VH. A low low voltage VL (= Vbb−REF) is generated and supplied to the oscillation circuit 3 and the charge pump circuit 4. Note that whether or not the constant voltage generation circuit 2 is operable is controlled according to the logic levels of the enable signal EN and the abnormality protection signal S5a. More specifically, the constant voltage generation circuit 2 has a logic level (for example, a high level) when the enable signal EN is at a logic level (for example, high level) when enabled or when the abnormality protection signal S5a has not detected an abnormality. ) When the enable signal EN is at a logic level (for example, low level) when disabled, or when the abnormality protection signal S5a is at a logic level (for example, low level) when detecting an abnormality. Stopped.

  The oscillation circuit 3 operates by receiving the high voltage VH and the low voltage VL, generates a clock signal CLK having a predetermined frequency, and outputs the clock signal CLK to the charge pump circuit 4. The clock signal CLK is a rectangular wave signal that is pulse-driven between the high voltage VH and the low voltage VL.

  The charge pump circuit 4 operates by receiving the high voltage VH and the low voltage VL, and drives the flying capacitor using the clock signal CLK, thereby generating a boosted voltage VCP higher than the power supply voltage Vbb and performing gate control. This is supplied to the circuit 6 and the overcurrent protection circuit 13.

  The logic circuit 5 operates in response to the supply of the internal power supply voltage VREG, generates a gate control signal S5b, and outputs it to the gate control circuit 6. The gate control signal S5 is a binary signal that is at a high level (= VREG) when the transistors N1 and N2 are turned on and is at a low level (= GND) when the transistors N1 and N2 are turned off. The logic circuit 5 has a function of monitoring the temperature protection signal S10, the voltage drop protection signal S11, the open protection signal S12, and the overcurrent protection signal S13, respectively, and performing an abnormality protection operation as necessary. More specifically, when any abnormality is detected in the semiconductor device 100, the logic circuit 5 stops the constant voltage generation circuit 2 with the abnormality protection signal S5a as the logic level at the time of detecting the abnormality, and the gate control signal. S5b is set to the low level to forcibly turn off both the transistors N1 and N2. The logic circuit 5 also has a function of generating the gate signal S5c of the transistor N3 according to the abnormality detection result.

  The gate control circuit 6 is connected between the application terminal of the boosted voltage VCP and the OUT pin (= application terminal of the output voltage Vout), and generates the gate voltage VG with improved current capability of the gate control signal S5b. Output to the gates of the transistors N1 and N2. The gate voltage VG is at a high level (= VCP) when the gate control signal S5b is at a high level, and is at a low level (= Vo) when the gate control signal S5b is at a low level. Note that whether or not the gate control circuit 6 can operate is controlled according to the logic level of the overcurrent protection signal S13. More specifically, the gate control circuit 6 enters an operating state when the overcurrent protection signal S13 is at a logic level (eg, low level) when no abnormality is detected, and the logic when the overcurrent protection signal S13 detects an abnormality. When it is at a level (for example, high level), it is in a stopped state.

  The clamp circuit 7 is connected between the VBB pin and the gates of the transistors N1 and N2. In an application in which an inductive load is connected to the OUT pin, when the transistor N1 is switched from on to off, the OUT pin becomes a negative voltage due to the back electromotive force of the inductive load. Therefore, a clamp circuit 7 (so-called active clamp circuit) is provided for energy absorption. The active clamp voltage represented by Vbb− (Vclp + Vgs) is preferably set to 48 V, for example (where Vbb is the power supply voltage, Vclp is the negative clamp voltage of the OUT pin, and Vgs is the gate-source voltage of the transistor N1). ).

  The input circuit 8 is a Schmitt trigger that receives an input of a control signal from the IN pin and generates an enable signal EN.

  The reference generation circuit 9 operates in response to the supply of the internal power supply voltage VREG, generates a predetermined reference voltage Vref and a reference current Iref, and supplies them to each part of the semiconductor device 100. For example, the reference voltage Vref and the reference current Iref are used to set a target value of the internal power supply voltage VREG in the internal power supply circuit 1 and to set a threshold value for abnormality detection in the various protection circuits 9 to 13. It is done.

  The temperature protection circuit 10 operates in response to the supply of the internal power supply voltage VREG, includes a temperature detection element (not shown) that detects abnormal heat generation of the transistor N1, and the detection result (= whether abnormal heat generation has occurred). Is generated and output to the logic circuit 5. The temperature protection signal S10 is, for example, a binary signal that becomes a low level (= GND) when no abnormality is detected and becomes a high level (= VREG) when an abnormality is detected.

  The voltage drop protection circuit 11 operates in response to the supply of the internal power supply voltage VREG, and the voltage drop protection signal S11 corresponding to the monitoring result of the power supply voltage Vbb or the internal power supply voltage VREG (= whether or not a voltage drop abnormality has occurred). Is output to the logic circuit 5. The voltage drop protection signal S11 is, for example, a binary signal that becomes low level (= GND) when no abnormality is detected and becomes high level (= VREG) when an abnormality is detected.

  The open protection circuit 12 operates in response to the supply of the power supply voltage Vbb and the internal power supply voltage VREG, and generates an open protection signal S12 according to the monitoring result of the output voltage Vout (= whether a load open abnormality has occurred). And output to the logic circuit 5. The open protection signal S12 is, for example, a binary signal that is at a low level (= GND) when no abnormality is detected and is at a high level (= VREG) when an abnormality is detected.

  The overcurrent protection circuit 13 is connected between the application terminal of the boost voltage VCP and the OUT pin (= application terminal of the output voltage Vout), and the monitoring result of the sense voltage Vs (= whether or not an overcurrent has occurred). ) And an overcurrent protection signal S13 corresponding to the output of the logic circuit 5 is generated. The overcurrent protection signal S13 is, for example, a binary signal that becomes low level (= GND) when no abnormality is detected and becomes high level (= VREG) when an abnormality is detected.

  The transistor N1 is a power transistor having a drain connected to the VBB pin and a source connected to the OUT pin, and is a switch element (high side) for conducting / cutting off a current path through which an output current I1 flows from the battery to the load. Function as a switch). The transistor N1 is turned on when the gate voltage VG is at a high level and turned off when the gate voltage VG is at a low level.

  Note that the lower the on-resistance of the transistor N1, the more easily an overcurrent flows at the time of grounding of the OUT pin (= at the time of a short circuit to a ground potential or a low potential terminal corresponding thereto), and abnormal heat generation is likely to occur. Therefore, the lower the on-resistance of the transistor N1, the higher the importance of the temperature protection circuit 10 and the overcurrent protection circuit 13.

  The transistor N2 is a mirror transistor connected in parallel to the transistor N1, and generates a mirror current I2 corresponding to the output current I1. The size ratio of the transistor N1 and the transistor N2 is m: 1 (where m> 1, for example, m = 1000). Therefore, the mirror current I2 has a magnitude obtained by reducing the output current I1 to 1 / m. Note that, like the transistor N1, the transistor N2 is turned on when the gate voltage VG is at a high level, and turned off when the gate voltage VG is at a low level.

  The transistor N3 is an open drain type transistor having a drain connected to the ST pin and a source connected to the GND pin. The transistor N3 is turned on when the gate signal S5c is at a high level and turned off when the gate signal S5c is at a low level. That is, the self-diagnosis signal output from the ST pin is low when the gate signal S5c is high (= when the transistor N3 is on), and when the gate signal S5c is low (= (When the transistor N3 is off).

  The resistor R1 is connected between the IN pin and the input terminal of the input circuit 8, and functions as a current limiting resistor for suppressing an excessive surge current or the like.

  The resistor R2 is connected between the input terminal of the input circuit 8 and the GND pin, and when the IN pin is in an open state, the input logic level to the input circuit 8 is low level (= logic level when disabled). It functions as a pull-down resistor for determining.

  The sense resistor Rs is connected between the source of the transistor N2 and the OUT pin, and functions as a current detection element that generates a sense voltage Vs (= I2 × Rs) corresponding to the mirror current I2.

  The Zener diode Z1 is connected between the gates of the transistors N1 and N2 and the OUT pin so that the cathode is on the gate side of the transistors N1 and N2 and the anode is on the OUT pin side. The Zener diode Z1 connected in this way limits the gate-source voltage of the transistors N1 and N2 to a predetermined upper limit value or less in a normal connection state in which a battery is connected to the VBB pin and a load is connected to the OUT pin. Functions as a clamp element (surge voltage absorption element).

  The zener diode Z2 is connected between the gates of the transistors N1 and N2 and the OUT pin so that the anode is on the gate side of the transistors N1 and N2 and the cathode is on the OUT pin side. The Zener diode Z2 connected in this way is a reverse circuit for blocking the current path from the OUT pin to the gates of the transistors N1 and N2 in a reverse connection state where a load is connected to the VBB pin and a battery is connected to the OUT pin. Functions as a connection protection element.

  As described above, the semiconductor device 100 is configured as a monolithic power IC in which CMOS logic (logic circuit 5 or the like) and a power MOS device (transistor N1 or the like) are incorporated on one chip.

<Charge Pump Circuit (First Embodiment)>
FIG. 2 is a circuit diagram showing a first embodiment of the charge pump circuit 4. The charge pump circuit 4 of this embodiment is a Dixon type (three-stage configuration) including capacitors C11 to C13, diodes D11 to D14, and inverters INV11 to INV13.

  The anode of the diode D11 is connected to the input terminal of the high voltage VH (= power supply voltage Vbb). The cathode of the diode D11 is connected to the first end of the capacitor C11 and the anode of the diode D12. The cathode of the diode D12 is connected to the first end of the capacitor C12 and the anode of the diode D13. The cathode of the diode D13 is connected to the first end of the capacitor C13 and the anode of the diode D14. The cathode of the diode D14 is connected to the output terminal of the boost voltage VCP. An output capacitor and a load (both not shown) are connected to the output terminal of the boosted voltage VCP.

  The input end of the inverter INV11 is connected to the input end of the clock signal CLK. The output terminal of the inverter INV11 is connected to the second terminal of the capacitor C11 and the input terminal of the inverter INV12. The output terminal of the inverter INV12 is connected to the second terminal of the capacitor C12 and the input terminal of the inverter INV13. The output terminal of the inverter INV13 is connected to the second terminal of the capacitor C13. The inverters INV11 to INV13 connected as described above operate by receiving the supply of the high voltage VH and the low voltage VL, and logically invert the respective input signals to generate the respective output signals.

  The charge pump circuit 4 configured as described above outputs a boosted voltage VCP higher than the high voltage VH (= power supply voltage Vbb) by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK. . Below, the operation state of each phase is demonstrated concretely separately.

  FIG. 3 is a circuit diagram (first phase) illustrating the charge pump operation of the first embodiment. Hereinafter, in order to simplify the description, the voltage drop in the diodes D11 to D14 is ignored.

  In the first phase, the clock signal CLK is set to the high level (VH). Therefore, the output signals of the inverters INV11 to INV13 are low level (VL), high level (VH), and low level (VL), respectively.

  At this time, a charging current flows through the capacitor C11 from the input terminal of the high voltage VH via the diode D11. Therefore, the capacitor C11 is charged until the voltage between both ends thereof becomes substantially the constant voltage REF (= VH−VL).

  The capacitor C12 is charged in the immediately preceding second phase until the voltage between both ends is approximately twice the constant voltage REF (= 2REF). Therefore, when the second end of the capacitor C12 is raised to the high voltage VH due to the transition to the first phase, the first end of the capacitor C12 follows the charge conservation law of the capacitor C12 and the voltage between both ends is more than the second end. To a higher voltage (= VH + 2REF).

  At this time, a charging current flows from the capacitor C12 through the diode D13 to the capacitor C13. Therefore, the capacitor C13 is charged until the voltage between both ends thereof is approximately three times the constant voltage REF (= 3REF).

  In the first phase, since the diodes D12 and D14 are both reverse-biased, current does not flow backward through the path through these elements.

  FIG. 4 is a circuit diagram (second phase) showing the charge pump operation of the first embodiment. Similar to FIG. 3, the voltage drop in the diodes D11 to D14 will be ignored below for the sake of simplicity.

  In the second phase, the clock signal CLK is set to a low level (VL). Therefore, the output signals of the inverters INV11 to INV13 are high level (VH), low level (VL), and high level (VH), respectively.

  The capacitor C11 is charged until the voltage between both ends thereof becomes substantially a constant voltage REF in the immediately preceding first phase. Therefore, when the second end of the capacitor C11 is raised to the high voltage VH due to the transition to the second phase, the first end of the capacitor C11 follows the charge conservation law of the capacitor C11 and the voltage between both ends is more than the second end. To a higher voltage (= VH + REF).

  At this time, a charging current flows from the capacitor C11 to the capacitor C12 via the diode D12. Accordingly, the capacitor C12 is charged until the voltage between both ends thereof is approximately twice the constant voltage REF (= 2REF).

  Further, the capacitor C13 is charged until the voltage between both ends thereof is almost three times the constant voltage REF (= 3REF) in the immediately preceding first phase. Therefore, when the second end of the capacitor C13 is raised to the high voltage VH due to the transition to the second phase, the first end of the capacitor C13 follows the charge conservation law of the capacitor C13, and the voltage between both ends is more than the second end. To a higher voltage (= VH + 3REF).

  At this time, an output current flows from the capacitor C13 through the diode D14 to the output terminal of the boosted voltage VCP. Therefore, the boost voltage VCP (= VH + 3REF) higher than the high voltage VH is supplied to the load connected to the subsequent stage of the charge pump circuit 4.

  In the second phase, since the diodes D11 and D13 are both reverse-biased, current does not flow backward through the path through these elements.

  Thus, in the charge pump circuit 4 of the present embodiment, the boosted voltage VCP is generated by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK.

  However, the charge pump circuit 4 of the present embodiment is inefficient because the output current can only flow through the output terminal of the boosted voltage VCP only in every cycle of the clock signal CLK. In particular, when the power is reduced (= when the power supply voltage Vbb is lowered), the boosted voltage VCP is difficult to lift, and therefore, for example, there is a possibility that the required specifications of the in-vehicle device (corresponding to power supply drop due to cranking) cannot be satisfied. is there. Therefore, in the charge pump circuit 4 of this embodiment, it is necessary to increase the number of boosting stages in order to earn the boosted voltage VCP, which may increase the circuit scale.

<Charge Pump Circuit (Second Embodiment)>
FIG. 5 is a circuit diagram showing a second embodiment of the charge pump circuit 4. The charge pump circuit 4 of this embodiment includes capacitors C21 and C22, N-channel MOS field effect transistors N21 and N22, P-channel MOS field effect transistors P21 and P22, and inverters INV21 and INV22.

  The input end of the inverter INV21 is connected to the input end of the clock signal CLK. The output terminal of the inverter INV21 is connected to the first terminal of the capacitor C21 and the input terminal of the inverter INV22. The output terminal of the inverter INV22 is connected to the first terminal of the capacitor C22. The inverters INV21 and INV22 connected in this manner operate by receiving the supply of the high voltage VH and the low voltage VL, and logically invert the respective input signals to generate the respective output signals. Therefore, the capacitors C21 and C22 are pulse-driven at their first ends in reverse phase with each other in synchronization with the clock signal CLK.

  The source of the transistor N21 is connected to the input terminal of the high voltage VH (= power supply voltage Vbb). The drain of the transistor N21 is connected to the second end of the capacitor C33. The gate of the transistor N21 is connected to the second end of the capacitor C21. The source of the transistor N22 is connected to the input terminal of the high voltage VH. The drain of the transistor N22 is connected to the second end of the capacitor C21. The gate of the transistor N22 is connected to the second end of the capacitor C22.

  The drain of the transistor P21 is connected to the drain of the transistor N21. The source of the transistor P21 is connected to the output terminal of the boosted voltage VCP. The gate of the transistor P21 is connected to the second end of the capacitor C21. The drain of the transistor P22 is connected to the drain of the transistor N22. The source of the transistor P22 is connected to the output terminal of the boost voltage VCP. The gate of the transistor P22 is connected to the second end of the capacitor C22.

  The charge pump circuit 4 configured as described above outputs a boosted voltage VCP higher than the high voltage VH (= power supply voltage Vbb) by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK. . Below, the operation state of each phase is demonstrated concretely separately.

  FIG. 6 is a circuit diagram (first phase) illustrating the charge pump operation of the second embodiment. In the following, in order to simplify the explanation, voltage drops in the transistors N21 and N22 and the transistors P21 and P22 are ignored.

  In the first phase, the clock signal CLK is set to the high level (VH). Accordingly, the output signal of the inverter INV21 is low level (VL), and the output signal of the inverter INV22 is high level (VH).

  The capacitor C22 is charged until the voltage between both ends thereof becomes substantially a constant voltage REF in the immediately preceding second phase. Therefore, when the first end of the capacitor C22 is raised to the high voltage VH due to the transition to the first phase, the second end of the capacitor C22 follows the charge conservation law of the capacitor C22 and the voltage between both ends is greater than the first end. To a higher voltage (= VH + REF).

  As a result, the gate-source voltage of the transistor N22 increases and the gate-source voltage of the transistor P22 decreases. Therefore, the transistor N22 is turned on and the transistor P22 is turned off. Accordingly, since the high voltage VH is applied to the gates of the transistors N21 and P21, the gate-source voltage of the transistor N21 decreases, and the gate-source voltage of the transistor P21 increases. Accordingly, the transistor N21 is turned off and the transistor P21 is turned on.

  At this time, a charging current flows to the capacitor C21 from the input terminal of the high voltage VH via the transistor N22. Therefore, the capacitor C21 is charged until the voltage between both ends thereof becomes substantially the constant voltage REF (= VH−VL). An output current flows from the capacitor C22 through the transistor P21 to the output terminal of the boosted voltage VCP. Therefore, the boost voltage VCP (= VH + REF) higher than the high voltage VH is supplied to the load connected to the subsequent stage of the charge pump circuit 4.

  FIG. 7 is a circuit diagram (second phase) showing the charge pump operation of the second embodiment. In the following, as in FIG. 6, the voltage drops in the transistors N21 and N22 and the transistors P21 and P22 are ignored for the sake of simplicity.

  In the second phase, the clock signal CLK is set to a low level (VL). Therefore, the output signal of the inverter INV21 is high level (VH), and the output signal of the inverter INV22 is low level (VL).

  The capacitor C21 is charged until the voltage between both ends thereof becomes substantially a constant voltage REF in the immediately preceding second phase. Accordingly, when the first end of the capacitor C21 is raised to the high voltage VH due to the transition to the first phase, the second end of the capacitor C21 has a voltage component between both ends of the capacitor C21 in accordance with the charge conservation law of the capacitor C21. To a higher voltage (= VH + REF).

  As a result, the gate-source voltage of the transistor N21 increases, and the gate-source voltage of the transistor P21 decreases. Accordingly, the transistor N21 is turned on and the transistor P21 is turned off. Accordingly, since the high voltage VH is applied to the gates of the transistors N22 and P22, the gate-source voltage of the transistor N22 decreases, and the gate-source voltage of the transistor P22 increases. Accordingly, the transistor N22 is turned off and the transistor P22 is turned on.

  At this time, a charging current flows to the capacitor C22 from the input terminal of the high voltage VH via the transistor N21. Accordingly, the capacitor C22 is charged until the voltage between both ends thereof becomes substantially the constant voltage REF (= VH−VL). An output current flows from the capacitor C21 through the transistor P22 to the output terminal of the boosted voltage VCP. Therefore, the boost voltage VCP (= VH + REF) higher than the high voltage VH is supplied to the load connected to the subsequent stage of the charge pump circuit 4.

  As described above, in the charge pump circuit 4 of the present embodiment, as in the first embodiment (FIG. 2), the boosted voltage VCP is obtained by alternately repeating the first phase and the second phase in synchronization with the clock signal CLK. Is generated.

  Here, with the charge pump circuit 4 of the present embodiment, the output current can be allowed to flow to the output terminal of the boosted voltage VCP once every ½ period of the clock signal CLK. It becomes possible to raise efficiency rather than a form (FIG. 2). In particular, since the boosted voltage VCP can be quickly raised even when the power is reduced (= when the power supply voltage Vbb is lowered), for example, the required specifications of the in-vehicle device (corresponding to the power supply drop due to cranking) can be sufficiently satisfied. It becomes possible. In addition, since it is not necessary to increase the number of boosting stages in order to obtain the boosted voltage VCP, it is possible to reduce the circuit scale.

<Second stage configuration of charge pump circuit>
FIG. 8 is a circuit diagram showing a configuration example of the subsequent stage of the charge pump circuit 4 in the semiconductor device 100. As described above, the gate control circuit 6 and the overcurrent protection circuit 13 are connected to the subsequent stage of the charge pump circuit 4. By the way, the charge pump circuit 4 generates an output fluctuation corresponding to the driving frequency of the flying capacitor when the output rises (when activated). Therefore, in the semiconductor device 100 of this configuration example, the smoothing circuit 15 is provided before the overcurrent protection circuit 13 that requires high operation accuracy.

<Smoothing circuit>
Next, the configuration and operation of the smoothing circuit 15 will be described in detail with reference to FIG. The smoothing circuit 15 of this configuration example is a circuit block (low-pass filter circuit) that smoothes the boosted voltage VCP to generate the smoothed boosted voltage VCP, and includes a current mirror 151 and a capacitor 152.

  The current mirror 151 is a circuit unit that operates by receiving the boosted voltage VCP and generates a charging current Ic that varies in the same manner as the boosted voltage VCP, and includes PMOSFETs 151a and 151b. Both sources of the PMOSFETs 151a and 151b are connected to the input terminal of the boosted voltage VCP. Both gates of the PMOSFETs 151a and 151b are connected to the drain of the PMOSFET 151a. The drain of the PMOSFET 151a is connected to the input terminal of the reference current Iref. The drain of the PMOSFET 151b is connected to the first end of the capacitor 152 and the output end of the smooth boosted voltage VCP2. The second end of the capacitor 152 is connected to the OUT pin.

  When the output of the boosted voltage VCP changes when the output of the charge pump circuit 4 rises (starts up), the charge current Ic also changes with the same behavior. On the other hand, the charging voltage Vc appearing at the first end of the capacitor 152 becomes a smoothed voltage obtained by subjecting the boosted voltage VCP to a low-pass filter process in accordance with the charging / discharging of the capacitor 152 using the charging current Ic.

  Therefore, by supplying the charging voltage Vc as the smoothed boosted voltage VCP2 to the overcurrent protection circuit 13, even when the output fluctuation of the boosted voltage VCP occurs, the power supply fluctuation of the overcurrent protection circuit 13 is suppressed. The operation accuracy can be maintained at a high level.

  Further, in the smoothing circuit 15 of this configuration example, the charging current Ic flowing from the current mirror 151 into the capacitor 152 is basically a mirror of the reference current Iref at an equal magnification. Therefore, the current consumption of the smoothing circuit 15 can be suppressed by setting the current value of the reference current Iref sufficiently small. In particular, in view of the current output capability of the charge pump circuit 4, it is very important to keep the current consumption of the smoothing circuit 15 small.

  When a simple RC filter is used as the smoothing circuit 15, the cut-off frequency fc is 1 / 2πRC. Therefore, in order to cope with a driving frequency on the order of MHz, a resistor having a very large area is required. Therefore, in view of the circuit area, it can be said that this configuration example in which the current mirror 151 and the capacitor 152 are combined is more advantageous than a simple RC filter.

<Overcurrent protection circuit>
Next, the configuration and operation of the overcurrent protection circuit 13 will be described in detail with reference to FIG. The overcurrent protection circuit 13 of this configuration example monitors whether the mirror current I2 (and thus the output current I1 that is the current to be monitored) is in an overcurrent state, and an overcurrent protection signal corresponding to the monitoring result. This is a circuit block for generating S13. The overcurrent protection circuit 13 of this configuration example includes a constant current generation unit 131, a current mirror unit 132, NMOSFETs 133 and 134, resistors 135 and 136, and a capacitor 137.

  The constant current generation unit 131 is a circuit unit that generates a predetermined first current IA, and includes a depletion type NMOSFET 131a, an enhancement type NMOSFET 131b, an operational amplifier 131c, an NMOSFET 131d, and a resistor 131e (resistance value: R131e). Including.

  The drain of the NMOSFET 131a is connected to the input terminal of the smoothed boost voltage VCP2. The gate and source of the NMOSFET 131a and the gate and drain of the NMOSFET 131b are all connected to the output terminal of the constant voltage VA. The source of the NMOSFET 131b is connected to the OUT pin.

  The NMOSFETs 131a and 131b connected as described above function as a constant voltage generation unit (so-called ED type reference voltage source) that receives the supply of the smoothed boosted voltage VCP and generates a predetermined constant voltage VA. In this constant voltage generator, since the depletion type NMOSFET 131a functions as a kind of constant current source, a constant bias current is supplied to the NMOSFET 131b. As a result, a constant constant voltage VA corresponding to the gate-source voltage appears at the drain of the NMOSFET 131b.

  Note that the bias current consumed by the constant voltage generator is designed to have a very small current value (0.1 μA) without depending on the smooth boost voltage VCP2 by appropriately designing the W / L ratio of the NMOSFETs 131a and 131b. Degree).

  The constant voltage generator is not limited to the ED type reference voltage source, and any circuit configuration may be adopted as long as necessary voltage accuracy can be obtained.

  The non-inverting input terminal (+) of the operational amplifier 131c is connected to the output terminal of the constant voltage generation unit (= the output terminal of the constant voltage VA). The inverting input terminal (−) of the operational amplifier 131c is connected to the source of the NMOSFET 131d. The output terminal of the operational amplifier 131c is connected to the gate of the NMOSFET 131d. A first end of the resistor 131e is connected to the source of the transistor 131d. A second end of the resistor 131e is connected to the OUT pin.

  The operational amplifier 131c connected as described above controls the gate of the transistor 131d so that the non-inverting input terminal (+) and the inverting input terminal (−) are imaginarily short-circuited. As a result, since the constant voltage VA is applied to the first end of the resistor 131e, a first current IA (= VA × R131e) corresponding to the constant voltage VA is generated. As described above, the operational amplifier 131c, the NMOSFET 131d, and the resistor 131e function as a voltage / current converter that converts the constant voltage VA into the first current IA.

  The current mirror unit 132 includes PMOSFETs 132a to 132c, and generates a second current IB and a third current IC corresponding to the first current IA. The sources of the PMOSFETs 132a to 132c are all connected to the input terminal of the smoothed boost voltage VCP2. The gates of the PMOSFETs 132a to 132c are all connected to the drain of the PMOSFET 132a. The drain of the PMOSFET 132a corresponds to the input terminal of the first current IA and is connected to the drain of the NMOSFET 131d. The drain of the PMOSFET 132b corresponds to the output terminal of the second current IB. The drain of the PMOSFET 132c corresponds to the output terminal of the third current IC.

  The gates of the NMOSFETs 133 and 134 are both connected to the drain of the NMOSFET 133. The drain of the NMOSFET 133 is connected to the drain of the PMOSFET 132b. The source of the NMOSFET 133 is connected to the first end of the resistor 135 (resistance value R135). A second end of the resistor 135 is connected to the OUT pin. The drain of the NMOSFET 134 is connected to the drain of the PMOSFET 132c and the output terminal of the overcurrent protection signal S13. The source of the NMOSFET 134 is connected to the application terminal for the sense voltage Vs. The output terminal of the overcurrent protection signal S13 is pulled up to the VBB pin through a series circuit including a resistor 136 and a capacitor 137.

  The NMOSFETs 133 and 134 connected as described above serve as a voltage comparison unit that compares the sense voltage Vs corresponding to the mirror current I2 with a predetermined threshold voltage Vocp (= IB × R135) to generate the overcurrent protection signal S13. Function.

  When the sense voltage Vs is lower than the threshold voltage Vocp, the conductivity of the NMOSFET 134 is higher than the conductivity of the NMOSFET 133, and the overcurrent protection signal S13 is at a low level (= logic level when no abnormality is detected). On the other hand, when the sense voltage Vs is higher than the threshold voltage Vocp, the conductivity of the NMOSFET 134 is lower than the conductivity of the NMOSFET 133, and the overcurrent protection signal S13 is at a high level (= logic level at the time of detecting an abnormality).

  As described above, the constant current generation unit 131 and the current mirror unit 132 operate by receiving the smoothed boost voltage VCP2 instead of receiving the boost voltage VCP. With such a configuration, it is possible to maintain the operation accuracy of the overcurrent protection circuit 13 at a high level even when the output fluctuation of the boosted voltage VCP occurs.

<Gate control circuit>
Next, the configuration and operation of the gate control circuit 6 will be described in detail with reference to FIG. The gate control circuit 6 of this configuration example includes a driver 61 and an NMOSFET 62.

  The driver 61 is connected between the application terminal of the boosted voltage VCP and the OUT pin, generates a gate voltage VG with an increased current capability of the gate control signal S5b, and outputs it to the gates of the transistors N1 and N2. The gate voltage VG is at a high level (= VCP) when the gate control signal S5b is at a high level, and is at a low level (= Vo) when the gate control signal S5b is at a low level.

  The drain of the NMOSFET 62 is connected to the output terminal of the gate voltage VG (= the gates of the transistors N1 and N2). The source of the NMOSFET 62 is connected to the OUT pin. The gate of the NMOSFET 62 corresponds to the input terminal of the overcurrent protection signal S13.

  In the gate control circuit 6 of this configuration example, when the overcurrent protection signal S13 is at a low level (= logic level when no abnormality is detected), the NMOSFET 62 is turned off, so that the gate voltage VG is normally applied to the transistor N1. Applied. On the other hand, when the overcurrent protection signal S13 is at a high level (= logic level at the time of detecting an abnormality), the NMOSFET 62 is turned on, so that the gate and source of the transistor N1 are short-circuited.

  As described above, the gate control circuit 6 of this configuration example outputs the gate signal VG so as to forcibly turn off the transistor N1 when the overcurrent protection signal S13 is at the high level (= the logic level at the time of abnormality detection). It has a function to control.

<Application to vehicles>
FIG. 9 is an external view showing a configuration example of a vehicle. The vehicle X of this configuration example includes a battery (not shown in the figure) and various electronic devices X11 to X18 that operate by receiving supply of the power supply voltage Vbb from the battery. In addition, about the mounting position of the electronic devices X11-X18 in this figure, it may differ from the actual for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is an electronic device that is incorporated into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.

  The electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device that includes a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

  Note that the semiconductor device 100 described above can be incorporated in any of the electronic devices X11 to X18.

<Other variations>
In the above embodiment, the on-vehicle high-side switch IC has been described as an example. However, the application target of the invention disclosed in this specification is not limited to this, and other It can be widely applied to all semiconductor devices having a charge pump circuit, including an in-vehicle IPD [intelligent power device] (in-vehicle low-side switch IC, in-vehicle power supply IC, etc.) used for the above-described applications.

  That is, the invention disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The invention disclosed in this specification can be used for in-vehicle IPD and the like.

DESCRIPTION OF SYMBOLS 1 Internal power supply circuit 2 Constant voltage generation circuit 3 Oscillation circuit 4 Charge pump circuit 5 Logic circuit 6 Gate control circuit 61 Driver 62 NMOSFET
7 Clamp circuit 8 Input circuit 9 Reference generation circuit 10 Temperature protection circuit 11 Voltage drop protection circuit 12 Open protection circuit 13 Overcurrent protection circuit 131 Constant current generator 131a NMOSFET (depletion type)
131b NMOSFET (enhancement type)
131c operational amplifier 131d NMOSFET
131e resistor 132 current mirror part 132a-132c PMOSFET
133, 134 NMOSFET
135, 136 Resistance 137 Capacitor 15 Smoothing circuit 151 Current mirror 151a, 151b PMOSFET
152 Capacitor 100 Semiconductor Device N1 N-Channel MOS Field Effect Transistor (Power Transistor)
N2 N-channel MOS field effect transistor (current detection transistor)
N3 N-channel MOS field effect transistor (signal output transistor)
R1, R2 resistance Rs sense resistance Z1, Z2 Zener diode C11-C13 capacitor D11-D14 diode INV11-INV13 inverter C21, C22 capacitor N21, N22 N-channel MOS field effect transistor P21, P22 P-channel MOS field effect transistor INV21, INV22 Inverter X Vehicle X11-X18 Electronic equipment

Claims (10)

A charge pump circuit that generates a boosted voltage higher than the power supply voltage;
A smoothing circuit that smoothes the boosted voltage to generate a smoothed boosted voltage;
A post-stage circuit that operates in response to the supply of the smoothed boost voltage;
Have
The smoothing circuit is
A current mirror that generates a charging current that varies in the same manner as the boosted voltage;
A capacitor that outputs a charging voltage corresponding to the charging current as the smoothed boost voltage;
A semiconductor device comprising: The current mirror is
A first PMOSFET having a source connected to the boost voltage input and a drain and gate connected to a reference current input;
A second PMOSFET having a source connected to the input terminal of the boosted voltage, a gate connected to the gate of the first PMOSFET, and a drain connected to the capacitor;
The semiconductor device according to claim 1, comprising:   2. The overcurrent protection circuit, wherein the subsequent circuit is an overcurrent protection circuit that monitors whether or not a monitoring target current is in an overcurrent state and generates an overcurrent protection signal according to the monitoring result. 2. The semiconductor device according to 2.   4. The semiconductor device according to claim 3, wherein the overcurrent protection circuit generates the overcurrent protection signal by comparing a sense voltage corresponding to the monitoring target current with a predetermined threshold voltage. 5. The overcurrent protection circuit is
A constant current generator for generating a predetermined first current;
A current mirror for generating a second current and a third current according to the first current;
A first NMOSFET having a drain and a gate connected to the input terminal of the second current;
A second NMOSFET having a drain connected to the input terminal of the third current and an output terminal of the overcurrent protection signal, a gate connected to the gate of the first NMOSFET, and a source connected to the input terminal of the sense voltage;
A resistor having one end connected to the source of the first NMOSFET to generate the threshold voltage;
The semiconductor device according to claim 4, comprising: The constant current generator is
A constant voltage generation unit that receives the supply of the smoothed boost voltage and generates a constant voltage;
A voltage / current converter for converting the constant voltage into the first current;
The semiconductor device according to claim 5, comprising: A gate control circuit for receiving the boosted voltage and generating a gate voltage;
An N-channel type high-side switch that conducts / cuts off between a power source and a load according to the gate voltage;
The semiconductor device according to claim 3, further comprising: The overcurrent protection circuit monitors an output current flowing through the high-side switch or a mirror current corresponding thereto as the monitoring target current,
The gate control circuit controls the gate signal to forcibly turn off the high-side switch when the overcurrent protection signal is at a logic level at the time of overcurrent detection;
The semiconductor device according to claim 7.   An electronic apparatus comprising the semiconductor device according to claim 8. Battery,
The electronic apparatus according to claim 9, wherein the electronic apparatus operates by receiving supply of a power supply voltage from the battery;
The vehicle characterized by having.

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