JP7145745B2 - switch device - Google Patents

Description

The invention disclosed in this specification relates to a switching device.

The applicant of the present application has previously proposed many new technologies regarding switch devices such as in-vehicle IPDs (intelligent power devices) (see Patent Document 1, for example).

WO2017/187785

However, in the above-described conventional switch device, there is room for further study on compatibility between rush current suppression and stable start-up.

SUMMARY OF THE INVENTION The invention disclosed in the present specification aims to provide a switch device capable of achieving both inrush current suppression and stable start-up in view of the above-described problem found by the inventors of the present application.

A switch device disclosed in this specification includes a slew rate setting unit for setting a slew rate of a driver that drives a switch element connected between an input end of a power supply voltage and an output end of an output voltage; a boosting unit that generates a boosted voltage higher than a power supply voltage and supplies it to the driver; a boosting control unit that stops the boosting unit when the output voltage is lower than a threshold voltage; and a hysteresis imparting unit that imparts a hysteresis voltage to the threshold voltage (first configuration).

In addition, in the switch device having the first configuration, the hysteresis applying unit preferably has a configuration (second configuration) that increases the hysteresis voltage as the slew rate of the driver decreases.

Further, in the switch device having the first or second configuration, the slew rate setting unit preferably uses an external element to set the slew rate of the driver (third configuration).

Further, in the switch device having any one of the first to third configurations, the slew rate setting unit preferably has a configuration (fourth configuration) that variably controls the drive current flowing through the output stage of the driver.

Further, in the switch device having any one of the first to fourth configurations, the boost control unit is configured to set the threshold voltage based on a constant voltage supplied to the boost unit (fifth configuration). do it.

Further, in the switch device having any one of the first to fifth configurations, the boost control section has a function of enhancing current supply capability to the boost section when the output voltage is higher than the threshold voltage. A configuration (sixth configuration) is preferably used.

Further, the switch device having any one of the first to sixth configurations may be configured to have an N-channel transistor as the switch element (seventh configuration).

Further, the electronic equipment disclosed in this specification includes a switch device having any one of the first to seventh configurations, and a load connected to the switch device (eighth configuration). It is said that

In the electronic device having the eighth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor (ninth configuration).

Further, the vehicle disclosed in this specification has a configuration (tenth configuration) having the electronic device having the above eighth or ninth configuration.

ADVANTAGE OF THE INVENTION According to the invention disclosed in this specification, it becomes possible to provide a switching device that can achieve both inrush current suppression and stable startup.

Diagram showing the overall configuration of a semiconductor integrated circuit device A diagram showing a configuration example of a gate control unit FIG. 11 is a diagram showing a configuration example of a slew rate setting unit; Diagram showing correlation between slew rate and inrush current FIG. 11 is a diagram showing the first embodiment of the boost control unit; Timing chart showing an example of boost control operation Diagram showing boost control failure when low slew rate is set FIG. 11 is a diagram showing a second embodiment of the boost control unit; A diagram showing a configuration example of a bias voltage source Diagram showing correlation between soft-start current and hysteresis voltage External view showing one configuration example of a vehicle

<Semiconductor integrated circuit device (overall configuration)>
FIG. 1 is a block diagram showing the overall configuration of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of the present embodiment is an automotive high-side switch IC (=in-vehicle A type of IPD).

The semiconductor integrated circuit device 1 has external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (12 V, for example) from a battery (not shown). The external terminal T2 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T3 is a signal input terminal (IN pin) for receiving external input of the external control signal Si from the ECU 2 . The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU2. An external sense resistor 4 is externally attached between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 also includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output It is formed by integrating a current detection section 80 and a signal output section 90 .

The NMOSFET 10 is a high withstand voltage (for example, 42 V withstand voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2. The NMOSFET 10 connected in this manner functions as a switch element (high side switch) for conducting/interrupting a current path from the terminal to which the power supply voltage VBB is applied to the ground terminal via the load 3 . The NMOSFET 10 is turned on when the gate drive signal G1 is at high level, and turned off when the gate drive signal G1 is at low level.

The NMOSFET 10 may be designed to have an on-resistance value of several tens of mΩ. However, the lower the on-resistance of the NMOSFET 10, the more likely overcurrent will flow when the external terminal T2 is grounded (=when the output is short-circuited to the grounded terminal or a similar low-potential terminal), resulting in abnormal heat generation. Therefore, the lower the on-resistance of the NMOSFET 10, the more important the overcurrent protection circuit 71 and temperature protection circuit 73, which will be described later.

The output current monitoring unit 20 includes NMOSFETs 21 and 21 ′ and a sense resistor 22 and generates a sense voltage Vs (=sense signal) according to the output current Io flowing through the NMOSFET 10 .

NMOSFETs 21 and 21' are both mirror transistors connected in parallel with NMOSFET 10, and generate sense currents Is and Is' according to the output current Io. The size ratio between NMOSFET 10 and NMOSFETs 21 and 21' is m:1 (where m>1). Therefore, the sense currents Is and Is' have the magnitude of the output current Io reduced by 1/m. As with the NMOSFET 10, the NMOSFETs 21 and 21' are turned on when the gate drive signal G1 is at high level and turned off when the gate voltage G2 is at low level.

The sense resistor 22 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (=Is×Rs+Vo) corresponding to the sense current Is, where Vo is applied to the external terminal T2. It is a current-to-voltage conversion element that produces an output voltage appearing.

The gate control unit 30 performs on/off control of the NMOSFETs 10 and 21 by generating a gate drive signal G1 obtained by increasing the current capability of the gate control signal S1 and outputting it to the gates of the NMOSFETs 10 and 21, respectively. The gate control unit 30 has a function of controlling the NMOSFETs 10 and 21 so as to limit the output current Io according to the overcurrent protection signal S71.

The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=the logic level for turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply section 60, so that the control logic section 40 is in an operating state to control the gate. The signal S1 becomes high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=the logic level for turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so the control logic section 40 is in a non-operating state, and gate control is performed. The signal S1 becomes low level (=GND). In addition, the control logic unit 40 monitors various abnormal protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-described abnormality protection signals. there is

The signal input unit 50 is a Schmitt trigger that receives the input of the external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60 . For example, the external control signal Si becomes high level when the NMOSFET 10 is turned on, and becomes low level when the NMOSFET 10 is turned off.

The internal power supply section 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each section of the semiconductor integrated circuit device 1 . Whether or not the internal power supply unit 60 can operate is controlled according to the external control signal Si. More specifically, the internal power supply section 60 becomes active when the external control signal Si is at high level, and becomes non-operating when the external control signal Si is at low level.

The abnormality protection unit 70 is a circuit block that detects various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a low voltage protection circuit 74. .

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality has occurred in the output current Io). For example, the overcurrent protection signal S71 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not the load 3 has an open abnormality). For example, the open protection signal S72 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (especially around the NMOSFET 10), and detects the temperature according to the detection result (=whether abnormal heat generation occurs). Generate a protection signal S73. For example, the temperature protection signal S73 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The voltage reduction protection circuit 74 generates a voltage reduction protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (=whether or not a voltage reduction abnormality has occurred). For example, the low voltage protection signal S74 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The output current detection unit 80 generates a sense current Is' (=Io/m) corresponding to the output current Io by matching the source voltage of the NMOSFET 21' with the output voltage Vo using bias means (not shown). output to the signal output unit 90.

The signal output unit 90 outputs one of the sense current Is′ (=corresponding to the detection result of the output current Io) and the fixed voltage V90 (=corresponding to an abnormality flag, not explicitly shown in the figure) to an external device based on the output selection signal S2. It is selectively output to the terminal T4. When the sense current Is' is selectively output, the output detection voltage V80 (=Is'×R4 ) is transmitted to the ECU 2 . The output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So. When reading the current value of the output current Io from the state notification signal So, the state notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Gate control part>
FIG. 2 is a block diagram showing a configuration example of the gate control section 30. As shown in FIG. The gate control unit 30 of this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), and a capacitor 37 (capacitance value: C37). , Zener diode 38 .

The gate driver 31 is connected between the output end of the charge pump 33 (=the end to which the boosted voltage VG is applied) and the external terminal T2 (=the end to which the output voltage Vo is applied), and controls the current capability of the gate control signal S1. A raised gate drive signal G1 is generated. The gate drive signal G1 becomes high level (=VG) when the gate control signal S1 is high level, and becomes low level (=Vo) when the gate control signal S1 is low level.

The oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33 . Whether or not the oscillator 32 can operate is controlled according to an enable signal Sa from the control logic unit 40 .

The charge pump 33 is an example of a booster that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using the clock signal CLK and supplies the boosted voltage VG to the gate driver 31 . Whether or not the charge pump 33 operates is controlled according to the enable signal Sb from the control logic unit 40 .

The clamper 34 is connected between the external terminal T<b>1 (=application terminal of the power supply voltage VBB) and the gate of the NMOSFET 10 . In an application in which an inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the back electromotive force of the load 3 causes the output voltage Vo to become a negative voltage (<GND). Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

The drain of NMOSFET 35 is connected to the gate of NMOSFET 10 . The source of NMOSFET 35 is connected to external terminal T2. The gate of the NMOSFET 35 is connected to the application end of the overcurrent protection signal S71. A resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35 .

The cathode of Zener diode 38 is connected to the gate of NMOSFET 10 . The anode of Zener diode 38 is connected to the source of NMOSFET 10 . The Zener diode 38 connected in this manner functions as a clamping element that limits the gate-source voltage (=VG-Vo) of the NMOSFET 10 to a predetermined value or less.

In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is raised to a high level, the gate drive signal G1 changes from a steady high level (=VG) to a predetermined time constant τ (=R36×C37). is lowered by As a result, the conductivity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71 is lowered to low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is lifted.

Thus, the gate control section 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

<Rush current suppression function (soft start function)>
Incidentally, when a capacitive load is connected as the load 3, a large current (=rush current) is required to charge the capacitance when the semiconductor integrated circuit device 1 is started (=when the NMOSFET 10 is turned on). Therefore, the overcurrent protection circuit 71 is generally not of a type that turns off the output current Io when an overcurrent is detected (=stop type), but of a type that limits the output current Io below the upper limit (=limiting type). .

However, in the latter, even if an overcurrent is detected, a large output current Io continues to flow, resulting in large heat generation. Therefore, considering the functional safety of the semiconductor integrated circuit device 1, it is desirable to introduce an inrush current suppression function (soft start function) in addition to the overcurrent protection function.

Therefore, the semiconductor integrated circuit device 1 has a slew rate of the gate driver 31 (=rising speed of the gate drive signal G1, and furthermore, an output A slew rate setting section is provided for setting the rising speed of the voltage Vo.

<Slew rate setting part>
FIG. 3 is a diagram showing a configuration example of a slew rate setting unit. The slew rate setting unit 110 of this configuration example includes an operational amplifier 111, an NMOSFET 112, a resistor 113 (resistance value: Rss), and an external terminal SS.

A power supply end of the operational amplifier 111 is connected to an application end of the internal power supply voltage Vreg. A reference potential terminal of the operational amplifier 111 is connected to the ground terminal GND. The non-inverting input terminal (+) of the operational amplifier 111 is connected to the application terminal of the soft start voltage Vss. The inverting input terminal (-) of the operational amplifier 111 and the source of the NMOSFET 112 are connected to the external terminal SS. The output terminal of the operational amplifier 111 is connected to the gate of the NMOSFET 112 . The drain of NMOSFET 112 is connected to the output end of soft start current Iss. The resistor 113 is connected between the external terminal SS and the ground terminal GND outside the semiconductor integrated circuit device 1 .

The operational amplifier 111 connected as described above controls the gate of the NMOSFET 112 so that the non-inverting input terminal (+) and the inverting input terminal (-) are imaginarily shorted. As a result, a soft start current Iss (=Vss×Rss) corresponding to its own resistance value Rss flows through the resistor 113 . That is, the soft-start current Iss increases as the resistance value Rss increases, and conversely decreases as the resistance value Rss decreases. Therefore, it is possible to arbitrarily set the soft start current Iss using the external resistor 113 . If the differential stage inside the operational amplifier 111 is a cascode circuit, the setting accuracy of the soft-start current Iss can be improved.

The soft start current Iss is supplied to the gate driver 31 as a current signal for setting the slew rate of the gate driver 31 . That is, the slew rate setting unit 110 sets the slew rate of the gate driver 31 using the soft start current Iss. The gate driver 31 includes a source current source 311 and a sink current source 312 that form its output stage, and a controller 313 that controls them.

The source current source 311 is connected between the application end of the boosted voltage VG and the application end of the gate drive signal G1, and is turned on when the gate drive signal G1 is set to high level (=VG) to drive the gate. A source current IH (=upper gate driving current) is supplied to the application terminal of the signal G1.

Note that the source current IH changes according to the soft start current Iss. For example, the larger the soft start current Iss, the larger the source current IH, so the slew rate of the gate driver 31 increases. Conversely, the smaller the soft-start current Iss, the smaller the source current IH, so the slew rate of the gate driver 31 becomes lower. In this manner, the slew rate setting unit 110 variably controls the source current IH flowing through the output stage of the gate driver 31 using the soft start current Iss.

The sink current source 312 is connected between the application terminal of the gate drive signal G1 and the external terminal T2 (=the application terminal of the output voltage Vo), and when the gate drive signal G1 is at low level (=Vo), When turned on, sink current IL (=lower side gate drive current) is drawn from the application terminal of gate drive signal G1. The sink current IL may be set to a fixed value regardless of the soft start current Iss.

The controller 313 controls the source current source 311 and the sink current source 312 according to the gate control signal S1, thereby performing on/off control of the source current IH and the sink current IL. For example, the controller 313 sets the gate drive signal G1 to high level (=VG) by turning on the source current IH and turning off the sink current IL when the gate control signal S1 is at high level. On the other hand, the controller 313 sets the gate drive signal G1 to low level (=Vo) by turning off the source current IH and turning on the sink current IL when the gate control signal S1 is at low level.

FIG. 4 is a diagram showing the correlation between the slew rate of the gate driver 31 (=rising speed of the output voltage Vo) and the inrush current flowing through the load 3 (=peak current value of the output current Io). , the external control signal Si, the output voltage Vo and the output current Io are depicted. The line types (solid line, small dashed line, large dashed line, and one-dot chain line) of the output voltage Vo and the output current Io are in one-to-one correspondence.

When the external control signal Si rises to a high level, the NMOSFET 10 turns on, so the output voltage Vo begins to rise. At this time, if the load 3 has a capacity, a large output current Io (=rush current) flows to charge the capacity.

Here, the peak current value of the output current Io becomes larger as the capacity charging period becomes shorter, and conversely becomes smaller as the capacity charging period becomes longer. Therefore, for example, by narrowing down the source current IH of the gate driver 31 to reduce the rising speed of the output voltage Vo, it is possible to lengthen the capacity charging period and suppress the peak current value of the output current Io.

The peak current value of the output current Io fluctuates according to the capacitance value of the load 3 and the voltage value of the power supply voltage VBB. Furthermore, since the source current (IH) can be arbitrarily adjusted, it is possible to flexibly cope with various applications.

In the semiconductor integrated circuit device 1, as a means for realizing its stable start-up (and power saving at start-up), the charge pump 33 is stopped when the output voltage Vo is lower than the threshold voltage Vth. department is provided.

<Boost control unit (first embodiment)>
FIG. 5 is a circuit diagram showing a first embodiment of the boost control section. The boost control unit 120 of this embodiment is a circuit unit for controlling the generation operation of the boosted voltage VG (=Vo+β, for example Vo+5V) by the charge pump 33, and includes N-channel MOS field effect transistors N1 to N5, P It includes channel type MOS field effect transistors P1-P4, diodes D1-D4, Zener diodes ZD1-ZD3, current source CS1, and level shifter LVS.

Among the components described above, the diode D4, the Zener diode ZD3, and the level shifter LVS function as components of the detection unit DET.

The constant voltage VBB_REF and the constant voltage VBBM5 shown in the figure are both reference voltages generated inside the semiconductor integrated circuit device 1, and for example, VBB_REF≈VBB, VBBM5≈VBB-5V. .

The sources and backgates of the transistors P1 and P2 are both connected to the application terminal of the power supply voltage VBB. The gates of transistors P1 and P2 are both connected to the drain of transistor P1. The drain of transistor P1 is connected to ground GND via current source CS1. The drain of the transistor P2 is connected to the application terminal of the constant voltage VBB_REF (≈VBB).

The anode of the diode D1 is connected to the application end of the constant voltage VBB_REF. The cathode of diode D1 is connected to the anode of diode D2. The cathode of diode D2 is connected to the drain of transistor N3. The source, gate and backgate of transistor N3 are all connected to the anode of diode D3. The cathode of the diode D3 is connected to the drain of the transistor N1 (the terminal to which the threshold voltage Vth is applied). The number of series stages of the diodes D1 to D3 may be appropriately set according to the required forward voltage drop α (eg, 4 V).

The sources and backgates of the transistors N1 and N2 are both connected to the application terminal of the output voltage Vo. The gates of transistors N1 and N2 are both connected to the drain of transistor N1.

The sources and back gates of the transistors P3 and P4 are both connected to the application terminal of the power supply voltage VBB. The gate of transistor P3 is connected to the drain of transistor N2. The drain of transistor P3 is connected to the gate of transistor P4. The drain of transistor P4 is connected to the application end of constant voltage VBB_REF.

The drains of the transistors N4 and N5 are both connected to the application terminal of the power supply voltage VBB. The source, gate and backgate of transistor N4 are all connected to the drain of transistor N2. The source, gate and backgate of transistor N5 are all connected to the drain of transistor P3.

The cathodes of the Zener diodes ZD1 and ZD2 are both connected to the application terminal of the power supply voltage VBB. The anode of Zener diode ZD1 is connected to the gate of transistor P3. The anode of Zener diode ZD2 is connected to the gate of transistor P4.

The cathode of Zener diode ZD3 is connected to the application end of constant voltage VBB_REF. On the other hand, the anode of Zener diode ZD3 is connected to the anode of diode D4. The cathode of diode D4 is connected to the application end of constant voltage VBBM5.

The drain of transistor P3 is connected to the input terminal of level shifter LVS. The output end of the level shifter LVS corresponds to the output end of the enable signal EN.

Of the transistors N1 to N5 described above, the transistors N1 and N2 are both enhancement type, and the transistors N3 to N5 are all depletion type. In particular, transistor N3 functions as a current limiting element. Transistors N4 and N5 also function as pull-up elements.

The upper power supply terminals of the level shifter LVS, the oscillator 32, and the charge pump 33 are all connected to the application terminal of the constant voltage VBB_REF. The lower power terminals of the level shifter LVS, the oscillator 32, and the charge pump 33 are all connected to the application terminal of the constant voltage VBBM5. Therefore, for the enable signal EN output from the level shifter LVS and the clock signal CLK output from the oscillator 32, the high level is the constant voltage VBB_REF, and the low level is the constant voltage VBBM5. Become.

When the enable signal EN is at a high level (=logic level when enabled), the clock signal CLK is output from the oscillator 32, so that the charge pump 33 generates the boosted voltage VG. That is, the high level (=boosted voltage VG) of the gate drive signal G1 is raised to a voltage value higher than the output voltage Vo corresponding to the source voltage of the NMOSFET10. Therefore, it is possible to reliably turn on the NMOSFET 10 used as a high-side switch.

FIG. 6 is a timing chart showing an example (basic operation) of the boost control operation in the first embodiment. A voltage VG (chain line) and a gate drive signal G1 (broken line) are depicted. In the following, the operation of this figure will be described with appropriate reference to FIG. 5 as well.

At time t21, when the external control signal Si rises from the low level to the high level, the NMOSFET 10 turns on, so the output voltage Vo starts rising from 0V. When the output voltage Vo is lower than a predetermined threshold voltage Vth (=VBB_REF-α), the current mirror consisting of the transistors N1 and N2 operates, so that the drain current I1 flows through the transistor N2. Therefore, the gate voltage Vx of the transistor P3 is lowered to a low level (≈Vo), turning on the transistor P3. As a result, the gate voltage Vy of the transistor P4 is raised to a high level (≈VBB), turning off the transistor P4.

The level shifter LVS outputs an output signal (=enable signal EN) obtained by level-shifting the input signal (=gate voltage Vy) and then inverting the logic level thereof. Therefore, when the gate voltage Vy becomes high level (≈VBB), the enable signal EN becomes low level (≈VBBM5). As a result, the operation of generating the clock signal CLK by the oscillator 32 is stopped, so the operation of generating the boosted voltage VG by the charge pump 33 is also stopped.

Further, when the transistor P4 is turned off, the current supply path from the application end of the power supply voltage VBB to the application end of the constant voltage VBB_REF is cut off. Therefore, the current supply capability to charge pump 33 is not enhanced.

Thus, even if the external control signal Si rises to a high level, the charge pump 33 does not start the boosting operation until Vo>Vth. Therefore, the boosted voltage VG (and thus the gate drive signal G1) rises together with the output voltage Vo while maintaining a predetermined potential difference (=the on-threshold voltage of the NMOSFET 10) from the output voltage Vo.

After that, when Vo>Vth at time t22, the current mirror consisting of the transistors N1 and N2 cannot operate, so that the drain current I1 of the transistor N2 stops flowing. Therefore, the gate voltage Vx of the transistor P3 is raised to a high level (≈VBB), turning off the transistor P3. As a result, the gate voltage Vy of the transistor P4 drops to a low level (≈VBBM5), turning on the transistor P4.

When the gate voltage Vy becomes low level (≈VBBM5), the enable signal EN becomes high level (≈VBB_REF). As a result, the oscillator 32 starts generating the clock signal CLK, and the charge pump 33 also starts generating the boosted voltage VG.

Further, when the transistor P4 is turned on, the current supply path from the power supply voltage VBB application terminal to the constant voltage VBB_REF application terminal is conducted. Therefore, the current supply capability to the charge pump 33 is enhanced.

Thus, when Vo>Vth, the charge pump 33 starts the boosting operation, so that the boosted voltage VG is raised above the output voltage Vo. However, boosted voltage VG is clamped to a predetermined target value Vo(VBB)+β by Zener diode 38 in FIG.

After that, at time t23, when the external control signal Si falls from the high level to the low level, the NMOSFET 10 is turned off, so the output voltage Vo starts to drop toward 0V. However, the boosting operation of the charge pump 33 is continued while Vo>Vth. Therefore, the boosted voltage VG is maintained at the target value Vo(VBB)+β.

On the other hand, when Vo<Vth at time t24, the boosting operation of charge pump 33 is stopped. Therefore, after this, the boosted voltage VG (and thus the gate drive signal G1) decreases along with the output voltage Vo while maintaining a predetermined potential difference (=the ON threshold voltage of the NMOSFET 10) from the output voltage Vo.

As can be seen from the above series of operations, the boost control unit 120 of this embodiment stops the boost operation of the charge pump 33 when the output voltage Vo is lower than the threshold voltage Vth. In other words, the boost control unit 120 starts the boost operation of the charge pump 33 after the output voltage Vo rises to a voltage value higher than the threshold voltage Vth.

According to such a boost control operation, it is possible to reduce current consumption when the semiconductor integrated circuit device 1 is started (=immediately after the NMOSFET 10 is turned on), and to suppress distortion of the gate drive signal G1 due to noise. Therefore, it is possible to achieve stable startup of the semiconductor integrated circuit device 1 .

In addition, since it is possible to easily set a start-up sequence (sequential start-up) such as turning on the charge pump 33 after turning on the abnormality protection section 70, it is possible to realize a safe on/off design.

However, there is a point to be noted when performing the boost control (=charge pump control according to the output voltage Vo) in combination with the above-described inrush current suppression function (soft start function). The points to be noted are examined in detail below.

FIG. 7 is a diagram showing an abnormality in boost control when a low slew rate is set, and depicts the output voltage Vo and the enable signal EN in order from the top. A solid line indicates the behavior at a high slew rate, and a broken line indicates the behavior at a low slew rate.

When the semiconductor integrated circuit device 1 is started, when the output voltage Vo becomes higher than the threshold voltage Vth (=VBB_REF-α), the enable signal EN rises to a high level, so that the charge pump 33 starts boosting operation.

At this time, in the boost control unit 120, the current supply path from the application end of the power supply voltage VBB to the application end of the constant voltage VBB_REF is turned on, and the current supply capability to the charge pump 33 is enhanced. Therefore, the constant voltage VBB_REF may rise transiently. Since the threshold voltage Vth is set based on the constant voltage VBB_REF, when the constant voltage VBB_REF rises, the threshold voltage Vth also rises with the same behavior.

Here, if the slew rate of the gate driver 31 (=the rising speed of the output voltage Vo) is high, Vo>Vth is maintained even if the constant voltage VBB_REF rises transiently, so the boosting operation of the charge pump 33 is maintained. It is never stopped (see solid line).

On the other hand, if the slew rate of the gate driver 31 is low, Vo>Vth cannot be maintained when the constant voltage VBB_REF transiently rises, so the boosting operation of the charge pump 33 unintentionally stops or is repeatedly turned on/off. (see dashed line).

In particular, in the semiconductor integrated circuit device 1 having the above-described inrush current suppression function (soft start function), the slew rate of the gate driver 31 is arbitrarily variably controlled. is not enough. In the following, we propose a new configuration that can solve the above problems.

<Boost Control Unit (Second Embodiment)>
FIG. 8 is a diagram showing a second embodiment of the boost control section 120. As shown in FIG. The boost control section 120 of the present embodiment is based on the first embodiment (FIG. 5) and has a configuration in which a hysteresis imparting section 130 is incorporated.

The hysteresis applying unit 130 is a circuit block inserted between the application end of the constant voltage VBB_REF and the diode D1 as means for applying the hysteresis voltage Vhys to the threshold voltage Vth in accordance with the soft start current Iss. It includes a voltage source E, an N-channel MOS field effect transistor N21, and a P-channel MOS field effect transistor P21.

The positive terminal of the bias voltage source E, the drain of the transistor N21, and the source and backgate of the transistor P21 are all connected to the application terminal of the constant voltage VBB_REF. The negative end of bias voltage source E is connected to the gate of transistor N21. The source and backgate of the transistor N21 and the drain of the transistor P21 are all connected to the anode of the diode D1. The gate of the transistor P21 is connected to the application end of the enable signal EN (=the output end of the detection section DET).

Note that the drain-source voltage of the transistor N21 corresponds to the hysteresis voltage Vhys applied to the threshold voltage Vth. For example, when EN=L, the transistor P21 is turned on, so Vhys≈0, and Vth=VBB_REF-α. On the other hand, when EN=H, the transistor P21 is turned off, so Vhys=VgsN+VB (where VgsN is the voltage between the gate and source of the transistor N21, and VB is the bias voltage generated by the bias voltage source E). is Vth=VBB_REF-(α+VgsN+VB).

That is, when the enable signal EN switches from low level to high level, the threshold voltage Vth is lowered from VBB_REF-α to VBB_REF-(α+VgsN+VB). Therefore, even if the constant voltage VBB_REF rises transiently, Vo>Vth is likely to be maintained, and the boosting operation of the charge pump 33 is less likely to be stopped.

In particular, bias voltage source E generates bias voltage VB corresponding to soft start current Iss generated by slew rate setting section 110 . More specifically, the bias voltage VB decreases as the soft-start current Iss increases, and increases as the soft-start current Iss decreases. That is, the hysteresis voltage Vhys is low at high slew rates and high at low slew rates.

With such a configuration, the hysteresis voltage Vhys of the boost control unit 120 can be optimized according to the slew rate of the gate driver 31, so it is possible to achieve both inrush current suppression and stable startup.

<Bias voltage source>
FIG. 9 is a diagram showing a configuration example of the bias voltage source E. In FIG. The bias voltage source E of this configuration example includes a current source CS2, N-channel MOS field effect transistors N22 and N23, a P-channel MOS field effect transistor P21, and resistors R1 to R3.

A first end of the current source CS2 is connected to the application end of the power supply voltage VBB. The second end of current source CS2 and the first end of resistor R1 are connected to the gate of transistor P22. A second end of the resistor R1 is connected to the ground end. It should be noted that the resistor R1 is preferably formed of a p+ polysilicon resistor having a small temperature characteristic.

The first terminals of the resistors R2 and R3 and the back gate of the transistor P22 are both connected to the application terminal of the constant voltage VBB_REF. A second end of resistor R2 is connected to the source of transistor P22. A second end of the resistor R3 is connected to the gate of the transistor N21. It should be noted that the resistors R2 and R3 are preferably formed of polysilicon resistors of the same process in order to cancel mutual manufacturing variations and temperature characteristics.

The drain of transistor N22 is connected to the drain of transistor P22. The drain of transistor N23 is connected to the gate of transistor N21. The gates of transistors N22 and N23 are connected to the drain of transistor N22. The sources and back gates of transistors N22 and N23 are connected to the ground terminal.

Current source CS2 generates current I1 according to soft start current Iss (=Vss/Rss). Resistor R1 converts current I1 into voltage V1 (=I1×R1). The resistor R2 generates a current I2 (=V2/R2) corresponding to the voltage V2 across it (=VBB_REF−(V1+VgsP), where VgsP is the voltage across the gate and source of the transistor P22). Transistors N22 and N23 mirror current I2 to produce current I3. Resistor R3 converts current I3 to voltage V3 (=I3×R3). Voltage V3 is applied between the gate and drain of transistor N21 as bias voltage VB. Therefore, the hysteresis voltage Vhys can be expressed by the following formula.

As can be seen from the above equation, the hysteresis voltage Vhys decreases as the resistance value Rss increases and the soft-start current Iss increases, and the hysteresis voltage Vhys decreases as the resistance value Rss decreases and the soft-start current Iss decreases. get higher That is, the hysteresis voltage Vhys is low at high slew rates and high at low slew rates.

The gate-source voltage VgsP of the transistor P22 has a negative temperature characteristic. In view of this, it is desirable to give the soft start voltage Vss a positive temperature characteristic so that the temperature characteristics cancel each other out.

FIG. 10 is a diagram showing the correlation between soft-start current Iss and hysteresis voltage Vhys. As shown in the figure, the hysteresis applying unit 130 raises the hysteresis voltage Vhys as the soft-start current Iss decreases, and lowers the hysteresis voltage Vhys as the soft-start current Iss increases. That is, the hysteresis voltage Vhys is low at high slew rates and high at low slew rates. By optimizing the hysteresis voltage Vhys of the boost control unit 120 according to the slew rate of the gate driver 31 in this way, it is possible to achieve both inrush current suppression and stable startup.

<Application to vehicles>
FIG. 11 is an external view showing one configuration example of a vehicle. A vehicle X of this configuration example is equipped with a battery (not shown in the drawing) and various electronic devices X11 to X18 that operate with power supplied from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.

<Other Modifications>
Further, in the above-described embodiments, the high-side switch ICs for automobiles have been described as an example, but the application of the invention disclosed herein is not limited to this. , and other vehicle-mounted IPDs (such as vehicle-mounted low-side switch ICs and vehicle-mounted power supply ICs), as well as semiconductor integrated circuit devices other than vehicle-mounted applications.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalence to the claims are included.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be used for an in-vehicle IPD and the like.

1 Semiconductor integrated circuit device (switch device)
2 ECUs
3 load 4 external sense resistor 10 NMOSFET (switch element)
20 output current monitoring unit 21, 21' NMOSFET
22 sense resistor 30 gate controller 31 gate driver 311 source current source 312 sink current source 313 controller 32 oscillator 33 charge pump (booster)
34 clamper 35 NMOSFET
36 resistor 37 capacitor 38 Zener diode (clamp element)
40 control logic unit 50 signal input unit 60 internal power supply unit 70 abnormality protection unit 71 overcurrent protection circuit 72 open protection circuit 73 temperature protection circuit 74 undervoltage protection circuit 80 output current detection unit 90 signal output unit 110 slew rate setting unit 111 operational amplifier 112 NMOSFETs
113 resistor 120 boost control unit 130 hysteresis applying unit CS1, CS2 current source D1-D4 diode DET detection unit E bias voltage source LVS level shifter N1-N5, N21-N23 N-channel MOS field effect transistor P1-P4, P21 P-channel type MOS Field Effect Transistor R1~R3 Resistance SS External Terminal T1~T4 External Terminal X Vehicle X11~X18 Electronic Equipment ZD1~ZD3 Zener Diode

Claims (10)

a slew rate setting unit for setting a slew rate of a driver that drives a switching element connected between an input end of a power supply voltage and an output end of an output voltage;
a boosting unit that generates a boosted voltage higher than the power supply voltage and supplies it to the driver;
a boost control unit that stops the boost unit when the output voltage is lower than a threshold voltage;
a hysteresis applying unit that applies a hysteresis voltage to the threshold voltage according to the slew rate of the driver;
A switch device comprising: 2. The switch device according to claim 1, wherein the hysteresis applying unit increases the hysteresis voltage as the slew rate of the driver decreases. 3. The switch device according to claim 1, wherein the slew rate setting section uses an external element to set the slew rate of the driver. The switch device according to any one of claims 1 to 3, wherein the slew rate setting section variably controls the drive current flowing through the output stage of the driver. 5. The switch device according to claim 1, wherein the boost control section sets the threshold voltage based on a constant voltage supplied to the boost section. 6. The step-up control section according to claim 1, wherein the step-up control section has a function of enhancing current supply capability to the step-up section when the output voltage is higher than the threshold voltage. A switch device according to any one of the preceding claims. The switch device according to any one of claims 1 to 6, wherein the switch device has an N-channel transistor as the switch element. a switch device according to any one of claims 1 to 7;
a load connected to the switch device;
An electronic device comprising: 9. The electronic device according to claim 8, wherein the load is a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor. A vehicle comprising the electronic device according to claim 8 or 9.

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