JP6968657B2 - Integrator circuit - Google Patents

Description

The invention disclosed herein relates to an integrator circuit.

FIG. 7 is a circuit diagram showing a conventional example of an integrator circuit. The integrating circuit 20 of this conventional example includes an operational amplifier 21, a resistor 22 (resistance value: R), and a capacitor 23 (capacity value: C). The first end of the resistor 22 is connected to the input end of the input voltage Vin. Both the second end of the resistor 22 and the first end of the capacitor 23 are connected to the inverting input end (−) of the operational amplifier 21. The non-inverting input end (+) of the operational amplifier 21 is connected to the applied end of the bias voltage (grounded end in the example of this figure). Both the output end of the operational amplifier 21 and the second end of the capacitor 23 are connected to the output end of the output voltage Vout. According to the integration circuit 20 of this conventional example, an output voltage Vout proportional to the integrated value of the input voltage Vin can be obtained.

FIG. 8 is a timing chart showing an example of the integration operation by the integration circuit 20, and the input voltage Vin and the output voltage Vout are drawn in order from the top. In this figure, the case where the input voltage Vin is a square wave (period: T (= high level period T1 + low level period T2), high level: + V, low level: −V) will be described as an example. ..

The output voltage Vout decreases linearly in the high level period T1 of the input voltage Vin and rises linearly in the low level period T2 of the input voltage Vin. At this time, the high level of the output voltage Vout is + (1 / RC) × V × T2. On the other hand, the low level of the output voltage Vout is − (1 / RC) × V × T1. In this way, the integrating circuit 20 can convert the square wave-shaped input voltage Vin into the triangular wave-shaped output voltage Vout.

As an example of the prior art related to the above, Patent Document 1, Patent Document 2, or Patent Document 3 can be mentioned.

JP-A-2009-302718 (particularly FIG. 3) Japanese Unexamined Patent Publication No. 8-159752 (particularly FIG. 3) Japanese Unexamined Patent Publication No. 6-350410 (particularly FIG. 1)

However, in the conventional integrating circuit 20, when the operation is stopped in a state where the node voltage Va appearing at the inverting input end (-) of the operational amplifier 21 is lower than the output voltage Vout and the output voltage Vout is discharged to 0V, the capacitor Due to the charge conservation law of 23, the node voltage Va drops to a negative potential. Therefore, in a semiconductor device in which the integrating circuit 20 is integrated, when the operation of the integrating circuit 20 is stopped (when a negative potential is generated), the parasitic element in the device becomes active, causing malfunction, latch-up, element destruction, and the like. There was a risk.

The invention disclosed herein provides an integrator circuit in which the node voltage inside the circuit does not swing significantly negatively when the output voltage is discharged, in view of the above problems found by the inventors of the present application. The purpose is to do.

The integrating circuit disclosed in the present specification includes an operational amplifier that outputs an output voltage from the output end so that the non-inverting input end and the inverting input end are imaginatively short-circuited, and an input voltage input end and the inverting input end of the operational amplifier. Conduction / cutoff between the resistor connected between the operational amplifier, the capacitor connected between the output end and the inverting input end of the operational amplifier, and the output end and the ground end of the operational amplifier according to the discharge control signal. It has a discharge switch, a short-circuit switch that conducts / cuts between the output end and the inverting input end of the operational amplifier according to the discharge control signal, and a backflow prevention diode provided on the current path via the short-circuit switch. It is said to be a configuration (first configuration).

In the integrator circuit having the first configuration, the short-circuit switch may be configured to be a CMOS analog switch (second configuration).

The integrator circuit having the first or second configuration may be configured to further have a Schmitt trigger connected between the input end of the input voltage and the resistor (third configuration).

Further, the semiconductor device disclosed in the present specification has a configuration (fourth configuration) in which an integrator circuit having any of the first to third configurations is integrated.

The semiconductor device having the fourth configuration may have a configuration (fifth configuration) having an external terminal for externally attaching the capacitor.

Further, the electronic device disclosed in the present specification has a configuration (sixth configuration) including a semiconductor device having the fourth or fifth configuration.

In the electronic device having the sixth configuration, the semiconductor device may be configured to accept the supply of the pulse width modulation signal as the input voltage (seventh configuration).

Further, the vehicle disclosed in the present specification has an electronic device having the sixth or seventh configuration and a battery for supplying electric power to the electronic device (eighth configuration). ..

According to the invention disclosed in the present specification, it is possible to provide an integrator circuit in which the node voltage inside the circuit does not greatly swing negatively when the output voltage is discharged.

A circuit diagram showing an embodiment of a semiconductor device including an integrator circuit. Correlation diagram between output voltage and node voltage Time chart showing discharge behavior (VA> Vo) of output voltage and node voltage Time chart showing discharge behavior of output voltage and node voltage (VA <Vo, no new discharge mechanism) Time chart showing discharge behavior of output voltage and node voltage (VA <Vo, with new discharge mechanism) External view showing an example of a vehicle configuration A circuit diagram showing a conventional example of an integrator circuit Timing chart showing an example of integration operation

<Semiconductor device>
FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device. The semiconductor device 1 of the present embodiment is formed by integrating the integrator circuit 10. The integrator circuit 10 converts the square wave-shaped pulse width modulation signal PWM corresponding to the input voltage Vi into a triangular wave-shaped output voltage Vo and outputs the signal. The integrator circuit 10 has an output discharge function according to the discharge control signal DCHG.

<Integration circuit>
Subsequently, with reference to FIG. 1, the internal configuration and operation of the integrating circuit 10 will be described in detail. The integrating circuit 10 of this embodiment includes an operational amplifier 11, a resistor 12, a capacitor 13, a Schmitt trigger 14, a discharge switch 15, a short-circuit switch 16, a backflow prevention diode 17, and inverters 18 and 19. ..

The operational amplifier 11 outputs an output voltage Vo from the output end so that the ground voltage GND at the non-inverting input end (+) and the node voltage VA at the inverting input end (−) are imaginatively short-circuited.

The first end of the resistor 12 is connected to the output end of the Schmitt trigger 14. The second end of the resistor 12 is connected to the inverting input end (−) of the operational amplifier 11.

The first end of the capacitor 13 is connected to the output end (= application end of the output voltage Vo) of the operational amplifier 11. The second end of the capacitor 13 is connected to the inverting input end (−) (= application end of the node voltage VA) of the operational amplifier 11. As shown in this figure, the semiconductor device 1 has an external terminal for externally attaching the capacitor 13, and the capacitor 13 is mounted as a discrete component. However, if the capacitance value of the capacitor 13 is not so large, the capacitor 13 can be integrated in the semiconductor device 1.

The first end of the Schmitt trigger 14 is connected to the input end of the input voltage Vi (= pulse width modulation signal PWM). The second end of the Schmitt trigger 14 is connected to the first end of the resistor 12. With such a configuration, the influence of noise superimposed on the pulse width modulation signal PWM can be suppressed.

The discharge switch 15 conducts / cuts off between the output end and the ground end of the operational amplifier 11 according to the discharge control signal DCHG. In the example of this figure, an N-channel type MOS field effect transistor is used as the discharge switch 15. The drain of the discharge switch 15 is connected to the output end (= application end of the output voltage Vo) of the operational amplifier 11. Both the source and the back gate of the discharge switch 51 are connected to the ground end. The gate of the discharge switch 15 is connected to the input end of the discharge control signal DCHG via the inverters 18 and 19. The discharge switch 15 is turned off when the control signal DCHG is at a low level (= logic level at the time of non-discharge), and is turned on when the control signal DCHG is at a high level (= logic level at the time of discharge).

The short-circuit switch 16 conducts / cuts off between the output end and the inverting input end (−) of the operational amplifier 11 according to the discharge control signal DCHG. The short circuit switch 16 is turned on when the discharge control signal DCHG is at a high level and is turned off when the discharge control signal DCHG is at a low level.

As the short-circuit switch 16, a CMOS analog switch can be used. More specifically, the short-circuit switch 16 includes an N-channel type MOS field-effect transistor M1 and a P-channel type MOS field-effect transistor M2. The drain of the transistor M1 and the source and back gate of the transistor M2 are both connected to the output end (= application end of the output voltage Vo) of the operational amplifier 11 via the backflow prevention diode 17. The source and back gate of the transistor M1 and the drain of the transistor M2 are both connected to the inverting input end (−) (= application end of the node voltage VA) of the operational amplifier 11. The gate of the transistor M1 is connected to the application end of the discharge control signal DCHG. The gate of the transistor M2 is connected to the output end (= application end of the inverting discharge control signal DCHGB) of the inverter 18. The transistors M1 and M2 are accompanied by body diodes D1 and D2 having the polarities shown in the figure, respectively.

The anode of the backflow prevention diode 17 is connected to the output end of the operational amplifier 11. The cathode of the backflow prevention diode 17 is connected to the short circuit switch 16. As described above, the backflow prevention diode 17 is provided on the current path via the short-circuit switch 16. The backflow prevention diode 17 has a forward bias when the node voltage VA is lower than the output voltage Vo, and a reverse bias when the node voltage VA is higher than the output voltage Vo.

In the example of this figure, the backflow prevention diode 17 is provided between the output end of the operational amplifier 11 and the short-circuit switch 16, but the insertion position of the backflow prevention diode 17 is not limited to this, and a short circuit occurs. A backflow prevention diode 17 may be provided between the switch 16 and the inverting input end (−) of the operational amplifier 11.

The inverter 18 generates an inverting discharge control signal DCHGB by logically inverting the discharge control signal DCHG. That is, the inverting discharge control signal DCHGB becomes low level when the discharge control signal DCHG is high level, and becomes high level when the discharge control signal DCHG is low level.

The inverter 19 returns the discharge control signal DCHG to the gate of the discharge switch 15 by logically inverting the inverting discharge control signal DCHGB again.

In particular, the integrating circuit 10 of the present embodiment includes a short-circuit switch 16, a backflow prevention diode 17, and inverters 18 and 19 in addition to the discharge transistor 15 as a discharge mechanism of the output voltage Vout. Hereinafter, these components 16 to 19 are collectively referred to as a "new discharge mechanism", and the significance of their introduction will be described in detail.

FIG. 2 is a correlation diagram between the output voltage Vo (horizontal axis) and the node voltage VA (vertical axis). As shown by the solid line in this figure, the relationship between the output voltage Vo and the node voltage VA can be any of VA> Vo, VA = Vo, and VA <Vo depending on the operating state of the integrating circuit 10. ..

FIG. 3 is a time chart showing the discharge behavior (when VA> Vo) of the output voltage Vo and the node voltage VA in the present embodiment, and the discharge control signal DCHG, the output voltage Vo (solid line), and the output voltage Vo (solid line) are shown in order from the top. The node voltage VA (broken line) is depicted.

When the discharge control signal DCHG is raised to a high level, the application end of the output voltage Vo is short-circuited to the ground end, so that the output voltage Vo drops to 0V. At this time, the node voltage VA does not drop to 0V but settles at a positive potential due to the charge conservation law of the capacitor 13.

As described above, when the operation of the integrating circuit 10 is stopped and the output voltage Vo is discharged to 0V in a state where the node voltage VA is higher than the output voltage Vo, the node voltage VA does not swing to a negative potential. Therefore, the parasitic element inside the semiconductor device 1 does not become active regardless of whether or not a new discharge mechanism is introduced.

FIG. 4 is a time chart showing the discharge behavior (when VA <Vo) of the output voltage Vo and the node voltage VA when it is assumed that the new discharge mechanism is not introduced in the present embodiment, and is the same as FIG. , The discharge control signal DCHG, the output voltage Vo (solid line), and the node voltage VA (dashed line) are drawn in order from the top.

When the discharge control signal DCHG is raised to a high level, the application end of the output voltage Vo is short-circuited to the ground end, so that the output voltage Vo drops to 0V. At this time, the node voltage VA drops to a negative potential lower than 0V due to the charge conservation law of the capacitor 13.

In this way, when the operation of the integrating circuit 10 is stopped and the output voltage Vo is discharged to 0V in a state where the node voltage VA is lower than the output voltage Vo, the node means that a new discharge mechanism has not been introduced. The voltage VA swings to a large negative potential. Therefore, the parasitic element inside the semiconductor device 1 becomes active, which may cause a malfunction, latch-up, or element destruction.

FIG. 5 is a time chart showing the discharge behavior (when VA <Vo) of the output voltage Vo and the node voltage VA in the present embodiment, and is the same as in FIGS. 3 and 4, in order from the top, with the discharge control signal DCHG. , Output voltage Vo (solid line) and node voltage VA (dashed line) are depicted.

When the discharge control signal DCHG is raised to a high level, the application end of the output voltage Vo is short-circuited to the ground end, so that the output voltage Vo drops to 0V. At this time, the node voltage VA tends to drop to a negative potential lower than 0V due to the charge conservation law of the capacitor 13. However, when the discharge control signal DCHG is at a high level, the short circuit switch 16 is turned on. Further, when the node voltage VA is lower than the output voltage Vo, the backflow prevention diode 17 becomes a forward bias. Therefore, since both ends of the capacitor 13 are short-circuited, the node voltage VA is limited to the voltage (= −Vf) obtained by subtracting the forward voltage drop Vf of the backflow prevention diode 17 from the output voltage Vo (= 0V). It will not decrease.

As described above, in the case of the integrating circuit 10 of the present embodiment, even when the operation of the integrating circuit 10 is stopped in a state where the node voltage VA is lower than the output voltage Vo and the output voltage Vo is discharged to 0V. , The node voltage VA does not swing to a large negative potential. Therefore, since the parasitic element inside the semiconductor device 1 is unlikely to become active, it is possible to improve the operation reliability of the semiconductor device 1.

When the discharge control signal DCHG is raised to a high level while the node voltage VA is higher than the output voltage Vo, the short-circuit switch 16 is turned on, but the backflow prevention diode 17 becomes a reverse bias. Therefore, both ends of the capacitor 13 are not short-circuited, and only the discharge operation by the discharge switch 15 is performed. That is, the discharge behavior of the output voltage Vo and the node voltage VA is the behavior shown in FIG. 3 as described above. Therefore, since the node voltage VA does not swing to a negative potential, the parasitic element inside the semiconductor device 1 does not become active.

Further, when the output voltage Vo is not discharged (DCHG = L), both the discharge switch 15 and the short-circuit switch 16 are turned off, so that the normal operation of the integrating circuit 10 is not hindered. When the node voltage VA is higher than the output voltage Vo, the parasitic diodes D1 and D2 can be forward biased even if the short-circuit switch 16 is turned off. However, at that time, since the backflow prevention diode 17 becomes a reverse bias, an unintended backflow current does not flow in the current path via the short-circuit switch 16, and the normal operation of the integrating circuit 10 is not hindered.

<Application to vehicles>
FIG. 6 is an external view showing a configuration example of the vehicle X. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving electric power from a battery (not shown). The mounting positions of the electronic devices X11 to X18 in FIG. 6 may differ from the actual mounting positions for convenience of illustration.

The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.).

The electronic device X12 is a lamp control unit that controls turning on and off such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that controls driving such as a door lock and a security alarm.

The electronic device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat as a manufacturer's option. Is.

The electronic device X17 is an electronic device optionally mounted on the vehicle X as a user option such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device provided with a high withstand voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor device 1 (or the integrating circuit 10) described above can be incorporated into any of the electronic devices X11 to X18.

<Other variants>
In the above, the integrator circuit for the electronic device mounted on the vehicle is illustrated, but the application of the present invention is not limited to this, and the integrator circuit used for other purposes is also widely applied. Is possible.

In addition to the above embodiments, the various technical features disclosed herein can be modified in various ways without departing from the gist of the technical creation. That is, it should be considered that the embodiment is exemplary and not restrictive in all respects, and the technical scope of the invention is shown by the claims rather than the description of the embodiment. It should be understood that it includes all changes that fall within the meaning and scope of the claims.

The inventions disclosed herein can be used in general for integrating circuits used in a variety of applications.

1 Semiconductor device 10 Integrator circuit 11 Operational amplifier 12 Resistance 13 Capacitor 14 Schmitt trigger 15 Discharge switch (N-channel type MOS field effect transistor)
16 Short-circuit switch (CMOS analog switch)
17 Backflow prevention diode 18, 19 Inverter M1 N-channel type MOS field-effect transistor M2 P-channel type MOS field-effect transistor D1, D2 Body diode X Vehicle X11-X18 Electronic equipment

Claims (9)

An operational amplifier that outputs an output voltage from the output end so that the non-inverting input end and the inverting input end are imaginatively short-circuited.
A resistor connected between the input end of the input voltage and the inverting input end of the operational amplifier,
A capacitor connected between the output end and the inverting input end of the operational amplifier,
A discharge switch that conducts / cuts between the output end and the ground end of the operational amplifier according to the discharge control signal.
A short-circuit switch that conducts / cuts between the output end and the inverting input end of the operational amplifier according to the discharge control signal.
A backflow prevention diode provided on the current path through the short-circuit switch, with the anode connected to the output end of the operational amplifier and the cathode connected to one end of the short-circuit switch.
A delay portion arranged between the input end of the discharge control signal and the discharge switch,
An integrator circuit characterized by having. The integrator circuit according to claim 1, wherein the delay portion is an inverter. The integrator circuit according to claim 1 or 2 , wherein the short-circuit switch is a CMOS analog switch. The integrating circuit according to claim 1 to 3 , further comprising a Schmitt trigger connected between the input end of the input voltage and the resistor. A semiconductor device in which the integrator circuit according to any one of claims 1 to 4 is integrated. The semiconductor device according to claim 5 , further comprising an external terminal for externally attaching the capacitor. An electronic device comprising the semiconductor device according to claim 5 or 6. The electronic device according to claim 7 , wherein the semiconductor device receives a supply of a pulse width modulated signal as the input voltage. The electronic device according to claim 7 or 8,
A battery that supplies power to the electronic device and
A vehicle characterized by having.

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