JP2011188045A - Amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of reducing beat noise, while fully reducing power consumption using a DC-DC converter. <P>SOLUTION: The amplifier circuit 100 includes a built-in LDO 11, a processing circuit 12, and a PWM (Pulse Width Modulation) amplifier 14. The built-in LDO 11 is driven by a voltage SPVDD and a voltage AVDD generated with a DC-DC converter 3 by dropping the voltage SPVDD, and drops the voltage SPVDD to generate a voltage CREG. The processing circuit 12 is driven by the voltage AVDD, and applies signal processing to an input signal to differentially output first signals S1P and S1N. The PWM amplifier 14 amplifies the first signals S1P and S1N in class D by pulse width modulation. The PWM amplifier 14 includes a filter 13, an input circuit 141, and an output circuit 142. The filter 13 is supplied with the first signals S1P and S1N, and attenuates frequency components in a frequency band containing the switching frequency of the DC-DC converter 3 to output second signals S2P and S2N. The input circuit 141 is driven by the voltage CREG, and amplifies the second signal S2P and S2N by pulse width modulation. The output circuit 142 is driven by the voltage SPVDD. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an amplifier circuit for amplifying a signal.

  Patent Document 1 discloses a system including a class D amplifier circuit that amplifies and outputs an input signal by a pulse width modulation (PWM) system, and a selector circuit that supplies a sound signal to the class D amplifier circuit. Is disclosed. This selector circuit inputs sound signals from a plurality of sound sources such as a CD player and an AM / FM tuner, and selects and outputs one sound signal from these sound signals. The class D amplifier circuit receives a signal supplied from the selector circuit, performs an input circuit for performing pulse width modulation on the input signal, and outputs the pulse width modulated signal after class D amplification. And an output circuit.

JP 2008-154135 A

  The maximum output power of the class D amplifier circuit depends on the drive voltage of the output circuit. Therefore, in order to obtain a sufficiently large maximum output power, it is necessary to sufficiently increase the drive voltage of the output circuit. On the other hand, from the viewpoint of reducing power consumption, it is preferable that the drive voltage of the circuits constituting the system is low. Therefore, it is desirable to drive the output circuit at a high voltage and the other circuits at a low voltage among the circuits constituting the system.

  In this case, a power supply circuit that converts a high voltage to generate a low voltage is required. As this power supply circuit, there is a linear regulator in which a ripple hardly occurs. However, since the linear regulator divides the voltage to generate a low voltage, the greater the difference between the high voltage and the low voltage, the greater the power loss in voltage conversion. That is, even if another circuit is driven with a voltage significantly lower than a high voltage using a linear regulator, it is difficult to sufficiently reduce the power consumption of the entire system.

  Therefore, it is conceivable to use a DC-DC converter having excellent voltage conversion efficiency as the power supply circuit. According to the DC-DC converter, even if the difference between the high voltage and the low voltage is large, voltage conversion can be performed with less power loss than the linear regulator. That is, if another circuit is driven with a voltage significantly lower than a high voltage using a DC-DC converter, the power consumption of the entire system can be sufficiently reduced.

  However, the output voltage of a power supply circuit that performs switching such as a DC-DC converter includes a ripple (ripple voltage) having the same frequency as the switching frequency. Further, when a circuit on a sound signal path such as a selector circuit is driven by a voltage including a ripple, a component (ripple component) derived from the ripple is superimposed on the sound signal. This component can cause noise in the audible band. For example, assume that pulse width modulation is performed on a sound signal on which a ripple component is superimposed. In this case, the pulse-width-modulated signal includes a component of the difference between the frequency of the ripple component (ripple frequency) and the frequency of the triangular wave signal (carrier wave signal) or any of its multiples (differential frequency). Become. And this component will be heard as a sound (beat noise) if a difference frequency is a frequency in an audible band.

  On the other hand, the ripple included in the output voltage of the switching regulator such as a DC-DC converter is larger than the ripple that can be included in the output voltage of the linear regulator. Therefore, if a DC-DC converter is used, beat noise will increase.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an amplifier circuit that can sufficiently reduce power consumption while suppressing beat noise.

  In order to solve the above-described problem, an amplifier circuit according to the present invention includes a switching element that repeats switching, and includes a first DC-DC converter that outputs a first voltage obtained by dropping a voltage supplied from a DC power supply. An amplifier circuit to which a voltage is supplied, a linear regulator that drops the voltage supplied from the DC power source and outputs a second voltage, and a process that performs signal processing on the input signal and outputs the first signal A circuit, a filter, an input circuit, and an output circuit, amplifying the first signal by a pulse width modulation method and outputting an output signal to the driver, the filter being supplied with the first signal, A frequency component in a frequency band including a switching frequency is attenuated to output a second signal, and the input circuit amplifies the second signal by a pulse width modulation method. A PWM amplifier configured to generate a third signal, wherein the output circuit drives the third signal to generate the output signal, the processing circuit is driven by the first voltage, and the input circuit is the second circuit The output circuit is driven by a voltage, and the output circuit is driven by a voltage supplied from the DC power supply.

According to the present invention, since most circuits (processing circuits such as a selector circuit) in the previous stage of the PWM amplifier are driven by the first voltage generated by the DC-DC converter, the power consumption can be sufficiently reduced. it can.
However, since the first voltage includes a large ripple, when the processing circuit is driven with the first voltage, a large ripple component is superimposed on the input signal or the first signal. However, this ripple component is attenuated by the filter. In the present invention, the input circuit of the PWM amplifier is driven with the second voltage that does not include a large ripple. In other words, according to the present invention, in the signal path subject to pulse width modulation, a large ripple component superimposed on the signal is attenuated, and further superposition of a large ripple component on the signal is prevented. Noise can be suppressed.

Note that “driven by voltage” for a circuit means that it is not necessary to supply a voltage other than the voltage for driving the circuit.
The DC-DC converter (switching regulator) includes a switching element that repeats switching, and generates a first voltage by dropping a voltage supplied from a DC power supply by a voltage corresponding to a switching duty ratio. Circuit. As a DC-DC converter, a pulse width modulation DC-DC converter with a constant switching frequency (switching frequency of the switching element) and a pulse frequency modulation (PFM: Pulse Frequency Modulation) DC-DC with a variable switching frequency are used. There is a converter. In the case of a pulse frequency modulation type DC-DC converter, since the frequency varies depending on the load current, a beat may be generated when a difference from the switching frequency of the PWM amplifier becomes an audible band. On the other hand, in the case of a pulse width modulation type DC-DC converter, if the difference from the switching frequency of the PWM amplifier is selected so as not to be an audible band, occurrence of beats can be avoided.
The linear regulator is a power supply circuit that generates a second voltage by dropping a voltage supplied from a DC power supply by a voltage corresponding to a difference between a reference voltage and a predetermined reference voltage. LDO is suitable as a linear regulator when the DC power source is a battery such as a lithium ion battery. LDO is a low dropout type linear regulator, and its dropout voltage is typically about 100 to 200 mV.

  In the above-described amplifier circuit, the PWM amplifier includes a triangular wave generation circuit that generates a triangular wave signal having a constant frequency, the triangular wave generation circuit is driven by the second voltage, and the input circuit is input through the filter. An integration circuit that generates an integrated signal by integrating a composite signal of the input signal and the output signal, and a signal generator that compares the integrated signal with the triangular wave signal and generates the third signal based on the comparison result And a circuit. In this case, not only the input circuit but also the triangular wave generation circuit is driven by the second voltage, so that a large ripple component is prevented from being superimposed in the path of the triangular wave signal used for pulse width modulation. Therefore, beat noise can be reduced.

  In the amplifier circuit described above, the input circuit and the output circuit are connected via a level shifter, and the level shifter adapts the level of the third signal output from the input circuit to the input level of the output circuit. And is driven by the second voltage and the voltage from the DC power source.

1 is a block diagram showing a configuration of an amplifier circuit 100 according to an embodiment of the present invention. 2 is a circuit diagram illustrating a configuration of a built-in LDO 11 included in an amplifier circuit 100. FIG. 2 is a block diagram illustrating a configuration of a processing circuit 12 included in the amplifier circuit 100. FIG. 2 is a diagram illustrating a circuit configuration of an input circuit 141 included in the amplifier circuit 100. FIG. 2 is a block diagram showing a configuration of an amplifier circuit 200 to be compared with the amplifier circuit 100. FIG.

  With reference to FIG. 1, a configuration of an amplifier circuit 100 according to an embodiment of the present invention will be described. The amplifier circuit 100 is built in a portable device such as a mobile phone, and amplifies at least one of a plurality of input signals and differentially outputs it. The plurality of input signals are all sound signals, and the output signals SPOUTP and SPOUTN of the amplifier circuit 100 are supplied to the speaker 1.

  The amplifier circuit 100 is supplied with the voltage SPVDD from the DC power supply 2 and supplied with the voltage AVDD (first voltage) from the DC-DC converter 3. The DC power source 2 is a lithium ion battery. That is, the portable device including the amplifier circuit 100 is also a battery-type device. The DC-DC converter 3 is a switching regulator (power supply circuit) of a pulse width modulation system, includes a switching element that repeats switching at a constant cycle, and drops the voltage SPVDD supplied from the DC power supply 2 to reduce the voltage AVDD. Is generated and output. The voltage AVDD includes a ripple (ripple voltage) having the same frequency as the switching frequency of the DC-DC converter 3 (switching frequency of the switching element). The voltage SPVDD is 3.7V, and the voltage AVDD is 1.8V.

  The amplifier circuit 100 includes a built-in LDO 11, a processing circuit 12, and a PWM amplifier 14. The built-in LDO 11 is a low dropout type linear regulator (power supply circuit) built in the amplifier circuit 100 and generates a voltage CREG (second voltage) by dropping the voltage SPVDD supplied from the DC power supply 2. ,Output. The dropout voltage of the built-in LDO 11 is about 100 to 200 mV, and the voltage CREG is 1.8V. That is, SPVDD> CREG = AVDD.

  The built-in LDO 11 includes an operational amplifier 111 and resistors 112 and 113, as shown in the circuit diagram of FIG. The operational amplifier 111 includes a positive output terminal, a negative input terminal, and an output terminal, and is driven by the voltage SPVDD. The resistors 112 and 113 are connected in series, and divide the voltage between the output terminal of the operational amplifier 111 and the ground to generate the reference voltage REF. This reference voltage REF is supplied to the negative input terminal of the operational amplifier 111. On the other hand, a constant reference voltage STD is supplied to the positive input terminal of the operational amplifier 111. Accordingly, a voltage CREG obtained by dropping the voltage SPVDD by a voltage corresponding to the difference between the reference voltage REF and the reference voltage STD is output from the output terminal of the operational amplifier 111. The voltage CREG may include a ripple, but its magnitude is smaller than the ripple included in the voltage AVDD.

  The processing circuit 12 in FIG. 1 performs signal processing on at least one of a plurality of input signals and outputs a first signal differentially. The plurality of input signals include a sound signal (input signal MIC1) supplied from the first microphone, a sound signal (input signal MIC2) supplied from the second microphone, and a sound signal supplied from the first line input terminal. (Input signal LIN1), sound signal supplied from the second line input terminal (input signal LIN2), and sound signal supplied from the third line input terminal (input signal LIN3).

  As illustrated in FIG. 3, the processing circuit 12 includes microphone amplifiers 121 and 122, an input selector circuit 123, volume circuits 124 to 127 and 129, and a selector circuit 128 that are driven with a voltage AVDD. Thus, the processing circuit 12 is driven with the voltage AVDD. That is, only the voltage AVDD among the voltages SPVDD, AVDD, and CREG is used for driving the processing circuit 12.

  The microphone amplifier 121 amplifies and outputs the input signal MIC1. The volume circuit 124 adjusts and outputs the volume (gain) of the output signal of the microphone amplifier 121. The microphone amplifier 122 amplifies and outputs the input signal MIC2. The volume circuit 125 adjusts and outputs the volume of the output signal of the microphone amplifier 122. The input selector circuit 123 selects and outputs one of the input signals LIN1 and LIN2. The volume circuit 126 adjusts and outputs the volume of the output signal of the input selector circuit 123. The volume circuit 127 adjusts and outputs the volume of the input signal LIN3.

  The selector circuit 128 selects and outputs one of the output signals of the volume circuits 124 to 127. The volume circuit 129 adjusts the volume of the output signal of the selector circuit 128 and outputs the first signals S1P and S1N. Instead of the processing circuit 12, another processing circuit may be adopted. For example, instead of the selector circuit 128, a mixer circuit that outputs a synthesized signal of the output signals of the volume circuits 124 to 127 may be employed. Of course, the number and type of input signals can be changed as appropriate.

  The PWM amplifier 14 in FIG. 1 is a circuit that amplifies the first signals S1P and S1N by a pulse width modulation method and generates output signals SPOUTP and SPOUTN. The filter 13, the triangular wave generation circuit 144, the level shifter 143, and the level shifter And an input circuit 141 and an output circuit 142 connected to each other through the terminal 143. The filter 13 is supplied with the first signals S1P and S1N. The filter 13 is a low-pass filter that greatly attenuates frequency components in a frequency band including the switching frequency of the DC-DC converter 3 (switching frequency of the switching element) without significantly attenuating frequency components in the audible band (audible range). Yes, the second signals S2P and S2N are output. The filter 13 is a passive filter, and it is not necessary to supply a voltage for driving the filter 13.

  The triangular wave generation circuit 144 and the input circuit 141 are driven by the voltage CREG, the output circuit 142 is driven by the voltage SPVDD, and the level shifter 143 is driven by the drive voltage (voltage CREG) of the input circuit 141 and the drive voltage (voltage SPVDD) of the output circuit 142. Driven. That is, of the voltages SPVDD, AVDD, and CREG, only the voltage CREG is used for driving the triangular wave generation circuit 144 and the input circuit 141, and only the voltage SPVDD is used for driving the output circuit 142.

  The triangular wave generation circuit 144 generates a triangular wave signal TRI having a constant frequency and amplitude. The frequency of the triangular wave signal TRI is set higher than the frequency of the second signals S2P and S2N. The input circuit 141 is a circuit that receives the second signals S2P and S2N, the output signals SPOUTP and SPOUTN, and the triangular wave signal TRI, and generates the third signals S3P and S3N by pulse width modulating the second signals S2P and S2N. Yes, as shown in FIG. 4, the integrating circuit 20 and the signal generating circuit 40 are provided.

  The integrating circuit 20 is a circuit that integrates a synthesized signal of the second signals S2P and S2N and the output signals SPOUTP and SPOUTN to generate integrated signals XP and XN, and includes resistors 21a, 21b, 22a, 22b, 26a, and 26b, and , An operational amplifier 23, capacitors 24a, 24b, 25a and 25b, and reset switches 27a and 27b.

  The operational amplifier 23 includes a positive input terminal, a negative input terminal, a negative output terminal, and a positive output terminal. The positive input terminal is supplied with the second signal S2P through the resistor 21a and the output signal SPOUTP through the resistor 22a. On the other hand, the second signal S2N is supplied to the negative input terminal via the resistor 21b and the output signal SPOUTN is supplied via the resistor 22b. Between the negative output terminal and the positive input terminal, a T-type secondary differentiation circuit and a reset switch 27a are provided in parallel. This differentiation circuit is constituted by capacitors 24a and 25a connected in series, and a resistor 26a provided between the connection point thereof and the ground. Further, a T-type secondary differentiation circuit and a reset switch 27b are provided in parallel between the positive output terminal and the negative input terminal. This differentiation circuit is composed of capacitors 24b and 25b connected in series, and a resistor 26b provided between the connection point thereof and the ground.

  The signal generation circuit 40 is a circuit that generates pulse width modulated third signals S3P and S3N based on the triangular wave signal TRI and the integration signals XP and XN, and includes comparators 41a and 41b and a timing circuit 42. . Each comparator has two input terminals, compares the voltage of one input terminal with the voltage of the other input terminal, and outputs a signal having a level corresponding to the result of the comparison. The integration signal XP is supplied to one input terminal of the comparator 41a, and the triangular wave signal TRI is supplied to the other input terminal. The integration signal XN is supplied to one input terminal of the comparator 41b, and the triangular wave signal TRI is supplied to the other input terminal. The timing circuit 42 generates pulse width modulated third signals S3P and S3N based on the output signals of the comparators 41a and 41b.

  The level shifter 143 in FIG. 1 shifts the levels of the third signals S3P and S3N output from the input circuit 141 so as to match the input level of the output circuit 142. The output circuit 142 outputs the third signals S3P and S3N whose levels are shifted by the level shifter 143 to the output terminals SPOUTP and SPOUTN.

  As described above, in the amplifier circuit 100, the processing circuit 12 is driven with the voltage AVDD (1.8V) that is sufficiently lower than the voltage SPVDD (3.7V). Further, since the configurations of the DC-DC converter 3 and the built-in LDO 11 are as described above, the power loss in the voltage conversion by the DC-DC converter 3 is far less than the power loss in the voltage conversion by the built-in LDO 11. Therefore, according to the present embodiment, the merit of low power consumption is not impaired in most circuits (= processing circuit 12) in the preceding stage of the PWM amplifier.

  Moreover, according to this embodiment, beat noise can be reduced. This point will be described by comparing the present embodiment with a comparative example. As illustrated in FIG. 5, the amplifier circuit 200 according to the comparative example does not include the built-in LDO 11 and the filter 13. In the amplifier circuit 200, the input circuit 141 is driven with the voltage AVDD. Therefore, according to the amplifier circuit 200, power consumption can be reduced as compared with the amplifier circuit 100.

  However, as described above, the voltage AVDD includes a large ripple. Therefore, when the processing circuit 12 is driven at the voltage AVDD, a large ripple component is superimposed on the input signal and the sound signals such as the first signals S1P and S1N in the processing circuit 12. In the amplifying circuit 200, neither the superposition of the ripple component nor the attenuation of the superimposed ripple component is performed in the sound signal path (processing circuit 12 to signal generation circuit 40) used for the pulse width modulation. Therefore, beat noise is generated.

  On the other hand, in the amplifier circuit 100, the ripple component superimposed on the sound signal in the processing circuit 12 is attenuated by the filter 13. Further, in the amplifier circuit 100, the integrating circuit 20 and the signal generating circuit 40 are driven by the voltage CREG that does not include a large ripple. Therefore, in these circuits, a large ripple component is not superimposed on the sound signal. In other words, in the amplifier circuit 100, the large ripple component superimposed on the sound signal is attenuated in the path of the sound signal used for pulse width modulation, and further superimposition of the large ripple component on the sound signal is prevented. Therefore, according to the amplifier circuit 100, beat noise can be suppressed.

  Further, if a circuit driven by the voltage AVDD exists in the path of the triangular wave signal TRI used for pulse width modulation (triangular wave generation circuit 144 and signal generation circuit 40), a large ripple component is superimposed on the triangular wave signal TRI in this circuit. . This can be a factor causing beat noise. Therefore, in the amplification circuit 100, the triangular wave generation circuit 144 and the signal generation circuit 40 are driven by the voltage CREG. Therefore, in these circuits, a large ripple component is not superimposed on the triangular wave signal TRI. That is, in the amplifier circuit 100, a large ripple component is prevented from being superimposed on the triangular wave signal TRI in the path of the triangular wave signal TRI. This contributes to reduction of beat noise.

If there is no need to take measures against beat noise, such as when the switching frequency of the DC-DC converter is constant and sufficiently separated from the switching frequency of the PWM amplifier, priority is given to low power consumption, and the triangular wave generation circuit 144 is integrated. The circuit 20 and the signal generation circuit 40 may be driven with the voltage AVDD.
Further, as the DC power source 2, a battery other than a lithium ion battery may be used, or a DC power source other than the battery may be used if the device including the amplifier circuit 100 does not need to be portable. Of course, the voltage SPVDD may be a voltage other than 3.7V, the voltage AVDD may be a voltage other than 1.8V, and the voltage CREG may be a voltage other than 1.8V, or CREG> AVDD may be satisfied, or CREG <AVDD may be satisfied. . However, SPVDD ≧ CREG and SPVDD> AVDD.
Further, as the DC-DC converter 3, a pulse frequency modulation type switching regulator whose switching frequency varies may be used. Further, instead of the built-in LDO 11, a linear regulator that is not a low dropout type may be used.

DESCRIPTION OF SYMBOLS 2 ... DC power supply, 3 ... DC-DC converter, 11 ... Built-in LDO (linear regulator), 12 ... Processing circuit, 13 ... Filter, 14 ... PWM amplifier, 20 ... Integration circuit, 40 ... Signal generation circuit, 100 ... Amplification Circuits 141... Input circuits 142... Output circuits 143... Level shifters 144.

Claims (3)

An amplifying circuit that includes a switching element that repeats switching, and that is supplied with the first voltage from a DC-DC converter that outputs a first voltage obtained by dropping a voltage supplied from a DC power supply,
A linear regulator that drops the voltage supplied from the DC power supply and outputs a second voltage;
A processing circuit for performing signal processing on an input signal and outputting a first signal;
A filter, an input circuit, and an output circuit, amplifying the first signal by a pulse width modulation method and outputting an output signal to the driver; the filter is supplied with the first signal, and the switching frequency of the switching element is The frequency component of the included frequency band is attenuated and a second signal is output. The input circuit amplifies the second signal using a pulse width modulation method to generate a third signal. The output circuit includes the third signal. A PWM amplifier for driving the signal to generate the output signal;
The processing circuit is driven by the first voltage;
The input circuit is driven by the second voltage;
The output circuit is driven by a voltage supplied from the DC power supply.
An amplifier circuit characterized by that. The PWM amplifier includes a triangular wave generation circuit that generates a triangular wave signal having a constant frequency,
The triangular wave generating circuit is driven by the second voltage;
The input circuit is
An integration circuit that integrates a combined signal of the input signal and the output signal input through the filter to generate an integrated signal;
The amplifier circuit according to claim 1, further comprising: a signal generation circuit that compares the integration signal and the triangular wave signal and generates the third signal based on a comparison result. The input circuit and the output circuit are connected via a level shifter,
The level shifter shifts the level of the third signal output from the input circuit to match the input level of the output circuit, and is driven by the second voltage and the voltage from the DC power supply. The amplifier circuit according to claim 1 or 2.

Images