JP7286440B2 - switch device - Google Patents

Description

The invention disclosed in this specification relates to a switching device.

The applicant of the present application has previously proposed many new technologies regarding switch devices such as in-vehicle IPDs (intelligent power devices) (see Patent Document 1, for example).

WO2017/187785

However, the conventional switch device does not have a temperature monitoring function during active clamp operation, and there is room for improvement in reliability.

In recent years, in particular, in-vehicle ICs are required to comply with ISO26262 (international standard for functional safety related to electrical/electronics in automobiles), and it is important to design even higher reliability for in-vehicle IPDs. It's becoming

SUMMARY OF THE INVENTION In view of the above-mentioned problems found by the inventors of the present application, it is an object of the invention disclosed in the present specification to provide a switch device capable of monitoring temperature during active clamping operation.

The switch device disclosed in this specification includes a switch element and an active clamper that limits the voltage across the switch element to a predetermined clamp voltage or less by preventing the switch element from being fully turned off when the switch element is turned off. and a temperature monitoring control unit that monitors the voltage across the switch element and drives the temperature detection element during operation of the active clamper (first configuration). there is

In the switch device having the first configuration, the temperature detection element is part of a temperature protection circuit that is enabled during the ON period of the switch element and disabled during the OFF period of the switch element. A configuration (second configuration) is preferable.

Further, in the switch device having the first or second configuration, the temperature monitoring control unit controls, when the first enable signal for controlling whether or not to drive the switch element is at a disabled logic level, A configuration (a third configuration) may be employed in which a rise in the voltage across the switch element is detected, and a second enable signal for controlling whether or not the temperature detection element can be driven is switched to a logic level at the time of enable. .

In the switch device having the third configuration, the temperature monitoring control unit has a gate connected to the input end of the first enable signal, and both a source and a back gate are connected to the second end of the switch element. a first NMOSFET having a gate connected to the drain of the first NMOSFET, a drain connected to the control end of the switch element, and a source and a backgate both connected to the second end of the switch element; a depletion-type third NMOSFET whose gate and source are both connected to the drain of said first NMOSFET, and whose back gate is connected to the second end of said switch element; and whose gate is It is connected to the drain of the third NMOSFET and also connected to the first end of the switch element via a first internal load, and the source is connected to the first end of the switch element via a second internal load. a PMOSFET whose back gate is connected to the first terminal of said switch element, and whose drain is connected to the ground terminal through a third internal load and also to the output terminal of said second enable signal. and; (fourth configuration).

In the switch device having the fourth configuration, the temperature monitoring control unit includes a first Zener diode having a cathode connected to the first end of the switch element and an anode connected to the gate of the PMOSFET, and a cathode is connected to the gate of the second NMOSFET and the anode is connected to the second terminal of the switch element, and the cathode is connected to the output terminal of the second enable signal and the anode is connected to the ground terminal. and a third Zener diode (fifth configuration).

In the switch device having any one of the first to fifth configurations, the active clamper includes a Zener diode having a cathode connected to the first end of the switch element and an anode connected to the anode of the Zener diode. and a transistor having a first end connected to the first end of the switch element, a second end connected to the control end of the switch element, and a control end connected to the cathode of the diode. (Sixth configuration) is preferable.

Further, the switch device having any one of the first to sixth configurations has a signal output section for selectively outputting the temperature detection signal obtained by the temperature detection element and other signals from a single external terminal. It is preferable to adopt a configuration (seventh configuration) that further includes.

Further, the electronic equipment disclosed in this specification includes a switch device having any one of the first to seventh configurations, and a load connected to the switch device (eighth configuration). It is said that

In the electronic device having the eighth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor (ninth configuration).

Further, the vehicle disclosed in this specification has a configuration (tenth configuration) having the electronic device having the above eighth or ninth configuration.

According to the invention disclosed herein, it is possible to provide a switching device capable of monitoring temperature during active clamping operation.

FIG. 1 shows a semiconductor integrated circuit device according to a first embodiment; A diagram showing a configuration example of a gate control unit Diagram showing one configuration example of an active clamper Diagram showing active clamp operation The figure which shows 2nd Embodiment of a semiconductor integrated circuit device Diagram showing a configuration example of a temperature protection circuit Diagram showing an example of temperature monitoring control during active clamp operation The figure which shows 3rd Embodiment of a semiconductor integrated circuit device External view showing one configuration example of a vehicle

<First embodiment (basic configuration)>
FIG. 1 is a diagram showing a first embodiment of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of the present embodiment is an in-vehicle high-side switch IC (=in-vehicle A type of IPD).

The semiconductor integrated circuit device 1 has external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (12 V, for example) from a battery (not shown). The external terminal T2 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T3 is a signal input terminal (IN pin) for receiving external input of the external control signal Si from the ECU 2 . The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU2. An external sense resistor 4 is externally attached between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 also includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output It is formed by integrating a current detection section 80 and a signal output section 90 .

The NMOSFET 10 is a high withstand voltage (for example, 42 V withstand voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2. The NMOSFET 10 connected in this way functions as a switch element (high side switch) for conducting/interrupting a current path from the terminal to which the power supply voltage VBB is applied to the ground terminal via the load 3 . The NMOSFET 10 turns on when the gate drive signal G1 is at high level, and turns off when the gate drive signal G1 is at low level.

The NMOSFET 10 may be designed to have an on-resistance value of several tens of mΩ when fully on. However, the lower the on-resistance of the NMOSFET 10, the more likely overcurrent will flow when the external terminal T2 is grounded (=when the output is shorted to a grounded terminal or a similar low potential terminal), resulting in abnormal heat generation. Therefore, the lower the on-resistance of the NMOSFET 10, the more important the overcurrent protection circuit 71 and temperature protection circuit 73, which will be described later.

The output current monitoring unit 20 includes NMOSFETs 21 and 21 ′ and a sense resistor 22 and generates a sense voltage Vs (=sense signal) according to the output current Io flowing through the NMOSFET 10 .

The NMOSFETs 21 and 21' are mirror transistors with their respective drains connected to the external terminal T1, and generate sense currents Is and Is' according to the output current Io. The size ratio between NMOSFET 10 and NMOSFETs 21 and 21' is m:1 (where m>1). Therefore, the sense currents Is and Is' have the magnitude of the output current Io reduced by 1/m. As with the NMOSFET 10, the NMOSFETs 21 and 21' are turned on when the gate drive signal G1 is at high level and turned off when the gate voltage G2 is at low level.

The sense resistor 22 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (=Is×Rs+Vo) corresponding to the sense current Is, where Vo is applied to the external terminal T2. It is a current-to-voltage conversion element that produces an output voltage appearing.

The gate control unit 30 generates a gate drive signal G1 with an increased current capability of the gate control signal S1 and outputs it to the gates of the NMOSFET 10 (and the NMOSFETs 21 and 21'), thereby performing on/off control of each NMOSFET. The gate control section 30 also has a function of controlling the NMOSFET 10 (and the NMOSFETs 21 and 21') so as to limit the output current Io according to the overcurrent protection signal S71.

The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=the logic level for turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply section 60, so that the control logic section 40 is in an operating state to control the gate. The signal S1 becomes high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=the logic level for turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so the control logic section 40 is in a non-operating state, and gate control is performed. The signal S1 becomes low level (=GND). In addition, the control logic unit 40 monitors various abnormal protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-described abnormality protection signals. there is

The signal input unit 50 is a Schmitt trigger that receives the input of the external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60 . For example, the external control signal Si becomes high level when the NMOSFET 10 is turned on, and becomes low level when the NMOSFET 10 is turned off.

The internal power supply section 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each section of the semiconductor integrated circuit device 1 . Whether or not the internal power supply unit 60 can operate is controlled according to the external control signal Si. More specifically, the internal power supply section 60 becomes active when the external control signal Si is at high level, and becomes non-operating when the external control signal Si is at low level.

The abnormality protection unit 70 is a circuit block for detecting various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a low voltage protection circuit 74. .

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality has occurred in the output current Io). For example, the overcurrent protection signal S71 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not the load 3 has an open abnormality). For example, the open protection signal S72 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (especially around the NMOSFET 10), and detects the temperature according to the detection result (=whether abnormal heat generation occurs). Generate a protection signal S73. For example, the temperature protection signal S73 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The voltage reduction protection circuit 74 generates a voltage reduction protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (=whether or not a voltage reduction abnormality has occurred). For example, the low voltage protection signal S74 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The output current detection unit 80 generates a sense current Is' (=Io/m) corresponding to the output current Io by matching the source voltage of the NMOSFET 21' with the output voltage Vo using bias means (not shown). output to the signal output unit 90.

The signal output unit 90 outputs one of the sense current Is′ (=corresponding to the detection result of the output current Io) and the fixed voltage V90 (=corresponding to an abnormality flag, not explicitly shown in the figure) to an external device based on the output selection signal S2. It is selectively output to the terminal T4. When the sense current Is' is selectively output, the output detection voltage V80 (=Is'×R4 ) is transmitted to the ECU 2 . The output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So. When reading the current value of the output current Io from the state notification signal So, the state notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Gate control part>
FIG. 2 is a diagram showing a configuration example of the gate control unit 30. As shown in FIG. The gate control unit 30 of this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, an active clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), and a capacitor 37 (capacitance value: C37). and Zener diode 38 .

The gate driver 31 is connected between the output end of the charge pump 33 (=the end to which the boosted voltage VG is applied) and the external terminal T2 (=the end to which the output voltage Vo is applied), and controls the current capability of the gate control signal S1. A raised gate drive signal G1 is generated. The gate drive signal G1 becomes high level (=VG) when the gate control signal S1 is high level, and becomes low level (=Vo) when the gate control signal S1 is low level.

The oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33 . Whether or not the oscillator 32 can operate is controlled according to an enable signal Sa from the control logic unit 40 .

The charge pump 33 is an example of a booster that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using the clock signal CLK and supplies the boosted voltage VG to the gate driver 31 . Whether or not the charge pump 33 operates is controlled according to the enable signal Sb from the control logic unit 40 .

The active clamper 34 is connected between the external terminal T<b>1 (=applying terminal of the power supply voltage VBB) and the gate of the NMOSFET 10 . In an application in which an inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the back electromotive force of the load 3 causes the output voltage Vo to become a negative voltage (<GND). Therefore, an active clamper 34 is provided for energy absorption.

The drain of NMOSFET 35 is connected to the gate of NMOSFET 10 . The source of NMOSFET 35 is connected to external terminal T2. The gate of the NMOSFET 35 is connected to the application end of the overcurrent protection signal S71. A resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35 .

The cathode of Zener diode 38 is connected to the gate of NMOSFET 10 . The anode of Zener diode 38 is connected to the source of NMOSFET 10 . The Zener diode 38 connected in this manner functions as a clamping element that limits the gate-source voltage (=VG-Vo) of the NMOSFET 10 to a predetermined value or less.

In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is raised to a high level, the gate drive signal G1 changes from a steady high level (=VG) to a predetermined time constant τ (=R36×C37). is lowered by As a result, the conductivity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71 is lowered to a low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is lifted.

Thus, the gate control section 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

<Active clamper>
FIG. 3 is a diagram showing a configuration example of the active clamper 34. As shown in FIG. The active clamper 34 of this configuration example includes an m-stage (eg, m=8) Zener diode array 341 , an n-stage (eg, n=3) diode array 342 , and an NMOSFET 343 .

The cathode of the Zener diode row 341 and the drain of the NMOSFET 343 are connected together with the drain of the NMOSFET 10 to the external terminal T1 (=corresponding to the first terminal connected to the application terminal of the power supply voltage VBB). The anode of Zener diode string 341 is connected to the anode of diode string 342 . The cathode of diode string 342 is connected to the gate of NMOSFET 343 . The source of the NMOSFET 343 is connected to the gate of the NMOSFET 10 (=application terminal of the gate drive signal G1). The source of the NMOSFET 10 is connected to the external terminal T2 (=corresponding to the second terminal connected to the first end of the load 3). As the load 3, an inductive load such as a coil or solenoid can be connected.

Below, the gate-source voltages of the NMOSFETs 10 and 343 are Vgs1 and Vgs2, the breakdown voltage of the Zener diode string 341 is mVZ, and the forward voltage drop of the diode string 342 is nVF. explain.

FIG. 4 is a timing chart showing the active clamping operation of the active clamper 34. From the top, the external control signal Si, the output voltage Vo (solid line), the gate drive signal G1 (broken line), and the output current Io are depicted. It is In addition, in this figure, it is assumed that an inductive load is connected as the load 3 .

At time t11, when the external control signal Si rises to a high level (=logic level for turning on the NMOSFET 10), the gate drive signal G1 rises to a high level and the NMOSFET 10 turns on, causing the output current Io to start flowing. , the output voltage Vo increases to near the power supply voltage VBB.

After that, at time t12, when the external control signal Si falls to low level (=logical level for turning off the NMOSFET 10), the gate drive signal G1 falls to low level and the NMOSFET 10 is turned off. At this time, the inductive load (coil, solenoid, etc.) connected as the load 3 continues to flow the output current Iout until the energy stored during the ON period of the NMOSFET 10 is released. As a result, the output voltage Vo drops to a negative voltage lower than the ground voltage GND.

However, due to the action of the active clamper 34, the gate-source voltage Vgs1 of the NMOSFET 10 is maintained near the on-threshold voltage Vth of the NMOSFET 10, so the NMOSFET 10 is never fully turned off. Therefore, the output current Io is discharged through the NMOSFET 10, and the output voltage Vo is limited to a lower limit voltage VBB-α (eg, VBB-50V) lower than the power supply voltage VBB by a predetermined value α (=mVZ+nVF+Vgs1+Vgs2).

That is, the active clamper 34 limits the drain-source voltage Vds (=VBB-Vo) of the NMOSFET 10 to a predetermined clamp voltage Vclp (=α) or less by preventing the NMOSFET 10 from fully turning off when the NMOSFET 10 is turned off.

The clamp voltage Vclp must be set to a voltage value higher than the maximum rated value of the power supply voltage VBB and lower than the drain-source withstand voltage of the NMOSFET 10 . Although it can be said that the higher the clamp voltage Vclp, the better the performance of the semiconductor integrated circuit device 1, the lower the clamp voltage Vclp, the better in view of the active clamp tolerance E (mJ).

The active clamp tolerance E (mJ) of the semiconductor integrated circuit device 1 is determined by the following equation from the clamp voltage Vclp (V), the output current Io (A), and the discharge time t (ms).

E (mJ) = Vclp (V) x Io (A) x t (ms)

By the way, during the active clamping operation, the back electromotive force generated in the inductive load 3 is consumed as heat, so the junction temperature Tj of the semiconductor integrated circuit device 1 rises. On the other hand, the higher the junction temperature Tj, the smaller the active clamp tolerance E. Therefore, in order to improve the reliability of the semiconductor integrated circuit device 1, it is desirable to monitor the junction temperature Tj during the active clamp operation outside the device (for example, the ECU 2).

However, since the active clamp operation is activated after the external control signal Si has fallen to the low level, the entire semiconductor integrated circuit device 1 is in the disabled state. Therefore, in this embodiment, there is no way to detect the junction temperature Tj during the active clamping operation and notify it to the outside of the device.

In the following, a second embodiment is proposed that solves the above problem and can monitor the junction temperature Tj during the active clamping operation.

<Second embodiment>
FIG. 5 is a diagram showing a second embodiment of the semiconductor integrated circuit device 1. As shown in FIG. The semiconductor integrated circuit device 1 of the present embodiment is based on the above-described first embodiment (see FIGS. 1 to 4), and has a temperature coefficient for enabling external monitoring of the junction temperature Tj during the active clamp operation. It has a monitor control unit 100 . It should be noted that the same reference numerals as in the first embodiment are assigned to the components already described, and redundant descriptions are omitted, and the temperature monitoring control unit 100 will be mainly described below.

The temperature monitoring control unit 100 monitors the drain-source voltage Vds (=VBB-Vo) of the NMOSFET 10 and detects the temperature protection circuit 73 (more precisely, the temperature detection included in the temperature protection circuit 73) during the operation of the active clamper 34. element), and includes N-channel MOS field effect transistors N1 to N6, a P-channel MOS field effect transistor P1, and Zener diodes ZD1 to ZD3. The transistors N1, N2, and P1 are all of enhancement type, and the transistors N3 to N6 are all of depletion type.

The gate of transistor N1 is connected to the input terminal of enable signal EN1. The enable signal EN1 is a logic signal for controlling whether or not the gate of the NMOSFET 10 can be driven. For example, the enable signal EN1 becomes high level (≈VG) when enabled (=when gate driving is permitted), and becomes low level (≈Vo) when disabled (=when gate driving is prohibited). The source and backgate of the transistor N1 are both connected to the external terminal T2 (=the source of the NMOSFET 10). The transistor N1 connected in this manner corresponds to an enhancement-type first NMOSFET.

The gate of the transistor N2 (=node voltage VB application terminal) is connected to the drain of the transistor N1. The drain of transistor N2 is connected to the gate of NMOSFET10. The source and backgate of the transistor N2 are both connected to the external terminal T2 (=the source of the NMOSFET 10). The transistor N2 connected in this manner corresponds to an enhancement-type second NMOSFET.

The gate and source of transistor N3 are both connected to the drain of transistor N1. A back gate of the transistor N3 is connected to the external terminal T2 (=the source of the NMOSFET 10). The transistor N3 connected in this manner corresponds to a depression-type third NMOSFET.

The drain of the transistor N4 is connected to the external terminal T1 (=drain of NMOSFET10). The source, gate and backgate of transistor N4 are all connected to the drain of transistor N3. The transistor N4 connected in this manner functions as a first internal load (current source).

The drain of the transistor N5 is connected to the external terminal T1 (=drain of NMOSFET10). The source, gate and backgate of transistor N5 are all connected to the source of transistor P1. Transistor N5 connected in this way functions as a second internal load (current source).

The drain of transistor N6 is connected to the drain of transistor P1. The source, gate and backgate of transistor N6 are all connected to the ground terminal. The transistor N6 connected in this manner functions as a third internal load (current source).

The gate of the transistor P1 (=node voltage VA application terminal) is connected to the drain of the transistor N3 and also to the source of the transistor N4. The source of transistor P1 is connected to the source of transistor N5. The back gate of the transistor P1 is connected to the external terminal T1 (=drain of the NMOSFET 10). The drain of transistor P1 is connected to the drain of transistor N6 and also to the output end of enable signal EN2. The enable signal EN2 is a logic signal for controlling whether the temperature protection circuit 73 (particularly the temperature detection element) can be driven. The enable signal EN2, for example, becomes high level (≈VZ3) when enabled (=when the temperature detection element is driven) and becomes low level (≈GND) when disabled (=when the temperature detection element is not driven). The enable signal EN2 can also be understood as a logic signal indicating that the NMOSFET 10 is on (not fully off) during the active clamp operation.

The cathode of Zener diode ZD1 is connected to external terminal T1 (drain of NMOSET 10). The anode of Zener diode ZD1 is connected to the gate of transistor P1. Zener diode ZD1 connected in this way functions as a first clamping element for limiting the difference voltage ΔV1 (=VBB−VA) between power supply voltage VBB and node voltage VA to its own breakdown voltage VZ1 or less.

The cathode of Zener diode ZD2 is connected to the gate of transistor N2. The anode of Zener diode ZD2 is connected to the source of transistor N2. The Zener diode ZD2 connected in this way functions as a second clamp element for limiting the difference voltage ΔV2 (=VB−Vo) between the node voltage VB and the output voltage Vo to the breakdown voltage VZ2 or less thereof.

The cathode of Zener diode ZD3 is connected to the output end of enable signal EN2. The anode of Zener diode ZD3 is connected to the ground terminal. The Zener diode ZD3 connected in this manner functions as a third clamping element for limiting the high level of the enable signal EN2 to its own breakdown voltage VZ3 or less.

The temperature protection circuit 73 includes a temperature detection element (not shown) as means for detecting the junction temperature Tj of the semiconductor integrated circuit device 1 (particularly around the NMOSFET 10). However, temperature protection circuit 73 is generally enabled during the ON period of NMOSFET 10 (Si=H) and disabled during the OFF period of NMOSFET 10 (Si=L). Therefore, in the conventional configuration, the junction temperature Tj cannot be monitored using the temperature protection circuit 73 while the active clamper 34 is in operation (=off period of the NMOSFET 10).

On the other hand, in the semiconductor integrated circuit device 1 of the present embodiment, by introducing the temperature monitoring control section 100, the temperature protection circuit 73 (especially the temperature detection element) can be driven while the active clamper 34 is in operation. Therefore, for example, by outputting a temperature detection signal VTj corresponding to the junction temperature Tj from the external terminal T5, the temperature can be monitored using the ECU 2 or the like.

FIG. 6 is a diagram showing a configuration example of the temperature protection circuit 73. As shown in FIG. The temperature protection circuit 73 of this configuration example includes a drive voltage source 731 , a drive current source 732 and a temperature detection element 733 .

Drive voltage source 731 generates drive voltage VREG for driving temperature detection element 733 according to enable signal EN2. More specifically, the drive voltage source 731 generates the drive voltage VREG when the enable signal EN2 is at high level (=logic level when enabled), and when the enable signal EN2 is at low level (=disabled). ), stop generating the drive voltage VREG.

Drive current source 732 generates drive current IREF for driving temperature detection element 733 according to enable signal EN2. More specifically, the drive current source 732 generates the drive current IREF when the enable signal EN2 is at high level (=logic level when enabled), and generates the drive current IREF when the enable signal EN2 is at low level (=disabled logic level). ), stops generating the drive current IREF.

The temperature detection element 733 is driven by receiving supply of the drive voltage VREG and the drive current IREF, and generates a temperature detection signal VTj corresponding to the junction temperature Tj. For example, the diode forward voltage drop Vf is generally known to have a negative temperature coefficient (eg, -2 mV/°C) with respect to the junction temperature Tj. Therefore, as the temperature detection element 733, for example, a diode (or diode string) having an anode connected to the external terminal T5 and a cathode connected to the ground terminal can be preferably used. In this figure, VTj=3Vf because a three-stage series diode array is used as the temperature detection element 733 .

In this way, by using the enable signal EN2 to turn on the drive voltage VREG and the drive current IREF of the temperature detection element 733 and generate the temperature detection signal VTj, the temperature detection signal VTj is supplied from the outside of the semiconductor integrated circuit device 1 via the external terminal T5. temperature monitoring can be performed.

FIG. 7 is a timing chart showing an example of temperature monitoring control during active clamp operation. solid line), the node voltage VA (broken line), the enable signal EN2, and the monitoring state of the temperature detection voltage VTj. In addition, in this figure, it is assumed that an inductive load is connected as the load 3 .

First, the standby period STBY (=before time t21) of the semiconductor integrated circuit device 1 will be described. Before time t21, the power supply voltage VBB has been raised, but the enable signal EN1 remains at the low level (≈Vo). Therefore, the transistor N1 is turned off, the node voltage VB becomes high level (≈Vo+VZ2), and the transistor N2 is turned on. As a result, the gate and source of the NMOSFET 10 are short-circuited and the NMOSFET 10 is turned off, so that the output voltage Vo becomes zero (≈GND). Also, at this time, the node voltage VA becomes high level (≈VBB), so the transistor P1 is turned off. As a result, the enable signal EN2 becomes low level (≈GND), and the temperature detection element 733 is disabled.

Next, the switch-on period SWON (=time t21 to t23) of the semiconductor integrated circuit device 1 will be described. At time t21, when the enable signal EN1 rises to high level (≈VG), the transistor N1 is turned on, so the node voltage VB becomes low level (≈Vo) and the transistor N2 is turned off. As a result, the gate and source of the NMOSFET 10 are opened, so that the gate driving of the NMOSFET 10 is permitted. Therefore, the NMOSFET 10 is turned on by the charging of the gate drive signal G1, so that the output voltage Vo starts rising from the zero value (≈GND).

Also, at this time, the node voltage VA drops to a predetermined clamp level (≈VBB-VZ1), so that the transistor P1 is turned on. As a result, the enable signal EN2 becomes high level (≈VZ3), and the temperature detection element 733 is enabled. Note that the entire semiconductor integrated circuit device 1 including the temperature protection circuit 73 is enabled during the switch-on period SWON. Therefore, there is no problem even if the enable signal EN2 is at high level.

After that, at time t22, when the output voltage Vo becomes higher than the clamp level (≈VBB-VZ1) of the node voltage VA, it is no longer clamped by the Zener diode ZD1. Therefore, after time t22, the node voltage VA rises to the power supply voltage VBB along with the output voltage Vo. As a result, the transistor P1 is turned off, so the enable signal EN2 becomes low level (≈GND). However, as described above, since the temperature protection circuit 73 itself is already enabled during the switch-on period SWON, there is no problem even if the enable signal EN2 becomes low level.

Next, the switch-off period SWOFF (=after time t23) of the semiconductor integrated circuit device 1 will be described. At time t23, the enable signal EN1 is lowered to low level (≈Vo), and discharging of the gate drive signal G1 is started. As a result, the NMOSFET 10 transitions from the ON state to the OFF state. At this time, the inductive load (coil, solenoid, etc.) connected as the load 3 continues to flow the output current Iout until the energy stored during the switch-on period SWON is released. As a result, output voltage Vo drops to a negative voltage lower than ground voltage GND after time t24.

However, due to the action of the active clamper 34, the gate-source voltage Vgs1 of the NMOSFET 10 is maintained near the on-threshold voltage Vth of the NMOSFET 10, so the NMOSFET 10 is never fully turned off. Therefore, the output current Io is discharged through the NMOSFET 10, and the output voltage Vo is limited to a lower limit voltage VBB-α (eg, VBB-50V) lower than the power supply voltage VBB by a predetermined value α. This point is as described in FIG. 4 above.

When the enable signal EN1 falls to low level and the transistor N1 is turned off, the source and back gate of the transistor N3 are disconnected. At this time, as the output voltage Vo applied to the back gate of the transistor N3 drops, the node voltage VA drops to the clamp level (≈VBB-VZ1). As a result, the transistor P1 is turned on and the enable signal EN2 becomes high level (≈VZ3), so that the temperature detection element 733 is enabled.

In this way, the temperature monitoring control unit 100 detects that the drain-source voltage Vds of the NMOSFET 10 has increased when the enable signal EN1 is at low level (=disabled logic level), that is, that the NMOSFET 10 is turned on. is detected (not fully turned off), and the enable signal EN2 is switched to high level (=logical level at the time of enable). As a result, the temperature detection element 733 is enabled and the temperature detection signal VTj is generated, so that the temperature can be monitored from the outside of the semiconductor integrated circuit device 1 via the external terminal T5.

At time t25, when the energy stored in the inductive load 3 is exhausted, the output voltage Vo applied to the back gate of the transistor N3 rises to the ground voltage GND, turning off the transistor N3. Become. As a result, the node voltage VA returns to the high level (≈VBB) again, turning off the transistor P1 and causing the enable signal EN2 to fall to the low level. That is, the period after time t25 can also be understood as the aforementioned standby period STBY.

<Third Embodiment>
FIG. 8 is a diagram showing a semiconductor integrated circuit device 1 according to a third embodiment. The semiconductor integrated circuit device 1 of this embodiment is based on the second embodiment (see FIGS. 5 to 7), but is provided with a dedicated external terminal T5 as an external output means for the temperature detection signal VTj. Instead, the internal configuration of the signal output section 90 is devised in order to use the existing external terminal T4. More specifically, the signal output section 90 includes selectors 91 and 92 .

The selector 91 selects and outputs the sense current Is' when the output selection signal S2 is at the logic level (for example, low level) when an abnormality is not detected, and the output selection signal S2 is at the logic level (for example, high level) when an abnormality is detected. ), the fixed voltage V90 is selectively output. Note that the fixed voltage V90 is set to a voltage value higher than the upper limit value of the output detection voltage V80 described above.

When the output selection signal SEL input to the external terminal T6 is at the first logic level (for example, low level), the selector 92 selectively outputs the output signal of the selector 71 to the external terminal T4 as the information notification signal So, and outputs When the selection signal SEL is at the second logic level (for example, high level), the temperature detection signal VTj is selectively output to the external terminal T4 as the information notification signal So.

Thus, according to the signal output unit 90 capable of selectively outputting the temperature detection signal VTj and other signals from the single external terminal T4, the output current is Since the detection result of Io, the abnormality flag, or the temperature detection signal VTj can be transmitted to the ECU 2, it is possible to contribute to a reduction in the number of external terminals. When reading the current value of the output current Io or the voltage value of the temperature detection signal VTj from the state notification signal So, the state notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Application to vehicles>
FIG. 9 is an external view showing one configuration example of the vehicle. A vehicle X of this configuration example is equipped with a battery (not shown in the drawing) and various electronic devices X11 to X18 that operate with power supplied from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalency to the claims are included.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be used for an in-vehicle IPD and the like.

1 Semiconductor integrated circuit device (switch device)
2 ECUs
3 load 4 external sense resistor 10 NMOSFET (switch element)
20 output current monitoring unit 21, 21' NMOSFET
22 sense resistor 30 gate controller 31 gate driver 32 oscillator 33 charge pump (booster)
34 Active clamper 341 Zener diode row 342 Diode row 343 NMOSFET
35 NMOSFETs
36 resistor 37 capacitor 38 Zener diode (clamp element)
40 control logic unit 50 signal input unit 60 internal power supply unit 70 abnormality protection unit 71 overcurrent protection circuit 72 open protection circuit 73 temperature protection circuit 731 drive voltage source 732 drive current source 733 temperature detection element 74 undervoltage protection circuit 80 output current detection Unit 90 Signal output unit 91, 92 Selector 100 Temperature monitoring control unit N1 to N6 N-channel MOS field effect transistor P1 P-channel MOS field effect transistor T1 to T6 External terminal X Vehicle X11 to X18 Electronic device ZD1 to ZD3 Zener diode

Claims (10)

a switch element;
an active clamper that limits the voltage across the switch element to a predetermined clamp voltage or less by preventing the switch element from being fully turned off when the switch element is turned off;
a temperature protection circuit enabled during an ON period of the switch element and disabled during an OFF period of the switch element ;
a temperature monitoring control unit that monitors the voltage across the switch element and drives the temperature detection element included in the temperature protection circuit even during operation of the active clamper in which the temperature protection circuit is disabled ;
A switch device. The temperature monitoring control unit detects that the voltage across the switch element has increased when a first enable signal for controlling whether or not the switch element can be driven is at a logic level for disabling, and 2. The switch device according to claim 1, wherein a second enable signal for controlling whether or not to drive said temperature detection element is switched to a logic level at the time of enable. a switch element;
an active clamper that limits the voltage across the switch element to a predetermined clamp voltage or less by preventing the switch element from being fully turned off when the switch element is turned off;
a temperature sensing element;
a temperature monitoring control unit that monitors the voltage across the switch element and drives the temperature detection element even during the operation of the active clamper;
has
The temperature monitoring control unit detects that the voltage across the switch element has increased when a first enable signal for controlling whether or not the switch element can be driven is at a logic level for disabling, and A switch device for switching a second enable signal for controlling whether or not to drive the temperature detection element to a logic level at the time of enable. The temperature monitoring control unit is
a first NMOSFET having a gate connected to the input end of the first enable signal and having a source and a backgate both connected to the second end of the switch element;
a second NMOSFET whose gate is connected to the drain of said first NMOSFET, whose drain is connected to the control end of said switch element, and whose source and back gate are both connected to the second end of said switch element;
a depletion-type third NMOSFET having a gate and a source both connected to the drain of the first NMOSFET and having a back gate connected to the second end of the switch element;
The gate is connected to the drain of the third NMOSFET and also connected to the first end of the switch element via a first internal load, and the source is connected to the first end of the switch element via a second internal load. The back gate is connected to the first end of the switch element, and the drain is connected to the ground terminal via the third internal load and is also connected to the output terminal of the second enable signal. a PMOSFET with;
4. A switching device according to claim 2 or claim 3, comprising: The temperature monitoring control unit is
a first Zener diode having a cathode connected to the first end of the switch element and an anode connected to the gate of the PMOSFET;
a second Zener diode having a cathode connected to the gate of the second NMOSFET and an anode connected to the second end of the switch element;
a third Zener diode having a cathode connected to the output terminal of the second enable signal and an anode connected to a ground terminal;
5. The switching device of claim 4 , further comprising: The active clamper
a Zener diode whose cathode is connected to the first end of the switch element;
a diode having an anode connected to the anode of the Zener diode;
a transistor having a first end connected to the first end of the switch element, a second end connected to the control end of the switch element, and a control end connected to the cathode of the diode;
The switch device according to any one of claims 1 to 5 , comprising: 7. The apparatus according to any one of claims 1 to 6 , further comprising a signal output section that selectively outputs a temperature detection signal obtained by said temperature detection element and other signals from a single external terminal. switch device. a switch device according to any one of claims 1 to 7;
a load connected to the switch device;
An electronic device having 9. The electronic device according to claim 8 , wherein said load is a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor. A vehicle comprising the electronic device according to claim 8 or 9.

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