JP2022142372A - Over-current protection circuit, switch device, electronic apparatus, and vehicle - Google Patents

Abstract

To provide: an over-current protection circuit in which the deviation between an over-current detection value and an over-current limit value is small; and a switch device, an electronic apparatus, and a vehicle using the over-current protection circuit.SOLUTION: In a semiconductor integrated circuit device (switch device), an over-current protection circuit 71 of an abnormality protection part that detects a variety of abnormalities in the semiconductor integrated circuit device includes limit parts (21a, 23a, 711, 712, 714, 715, 717, 35 to 37) that are configured to, when an output current Io flowing through a switch element 10 connected between a power source terminal T1 and an output terminal T2 becomes higher than a first over-current detection value, control a switch driving signal G1 to impose limits on the output current Io, and control parts (21b, 23b, 711, 713, 717, 718, 719, 31L) that are configured to, when the output current becomes higher than a second over-current detection value which is less than the first over-current detection value, rise the switch driving signal from a signal value during a full-on time.SELECTED DRAWING: Figure 6

Description

The invention disclosed in this specification relates to an overcurrent protection circuit, a switch device, an electronic device, and a vehicle using the same.

The applicant of the present application has so far proposed many new technologies regarding switch devices such as in-vehicle IPDs (intelligent power devices) (see Patent Document 1, for example).

WO2017/187785

However, the conventional switch device has room for further improvement in its overcurrent protection function (for example, the difference between the overcurrent detection value and the overcurrent limit value).

In view of the above-described problems found by the inventors of the present application, the invention disclosed in the present specification provides an overcurrent protection circuit having a small deviation between an overcurrent detection value and an overcurrent limit value, and An object of the present invention is to provide a switch device, an electronic device and a vehicle using

For example, the overcurrent protection circuit disclosed in this specification outputs a switch drive signal when an output current flowing through a switch element connected between a power supply terminal and an output terminal exceeds a first overcurrent detection value. and a limiting unit configured to limit the output current by controlling the switch drive signal when the output current exceeds a second overcurrent detection value smaller than the first overcurrent detection value. a controller configured to reduce the signal value from full-on.

Other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description and accompanying drawings that follow.

According to the invention disclosed in this specification, it is possible to provide an overcurrent protection circuit with a small deviation between an overcurrent detection value and an overcurrent limit value, a switch device, an electronic device, and a vehicle using the same. becomes possible.

FIG. 1 is a diagram showing the basic configuration of a semiconductor integrated circuit device. FIG. 2 is a diagram showing a configuration example of a gate control unit. FIG. 3 is a diagram showing a comparative example of an overcurrent protection circuit. FIG. 4 is a diagram showing a first example of overcurrent protection operation in the comparative example. FIG. 5 is a diagram showing a second example of overcurrent protection operation in the comparative example. FIG. 6 is a diagram showing a first embodiment of an overcurrent protection circuit. FIG. 7 is a diagram showing an example of overcurrent protection operation in the first embodiment. FIG. 8 is a diagram showing Vg-Id characteristics of a transistor. FIG. 9 is a diagram showing a second embodiment of an overcurrent protection circuit. FIG. 10 is a diagram showing a third embodiment of an overcurrent protection circuit. FIG. 11 is an external view showing one configuration example of a vehicle.

<Semiconductor integrated circuit device (basic configuration)>
FIG. 1 is a diagram showing the basic configuration of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of this configuration example is an in-vehicle high-side switch LSI (=in-vehicle A type of IPD).

The semiconductor integrated circuit device 1 has external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (12 V, for example) from a battery (not shown). The external terminal T2 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T3 is a signal input terminal (IN pin) for receiving external input of the external control signal Si from the ECU 2 . The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU2. An external sense resistor 4 is externally attached between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 also includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output It is formed by integrating a current detection section 80 and a signal output section 90 .

The NMOSFET 10 is a high withstand voltage (for example, 42 V withstand voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2. The NMOSFET 10 connected in this manner functions as a switch element (high side switch) for conducting/interrupting a current path from the terminal to which the power supply voltage VBB is applied to the ground terminal via the load 3 . The NMOSFET 10 is turned on when the gate drive signal G1 is at high level, and turned off when the gate drive signal G1 is at low level.

Also, the NMOSFET 10 may be designed so that the on-resistance Ron is several tens of mΩ. However, the lower the on-resistance Ron of the NMOSFET 10, the easier it is for an overcurrent to flow when the external terminal T2 is grounded (= short-circuit to a grounded terminal or a similar low-potential terminal), resulting in abnormal heat generation. Become. Therefore, as the on-resistance Ron of the NMOSFET 10 is lowered, the importance of an overcurrent protection circuit 71 and a temperature protection circuit 73, which will be described later, increases.

The output current monitoring unit 20 includes NMOSFETs 21 and 22 and a sense resistor 23 and generates a sense voltage Vs (=sense signal) corresponding to the output current Io flowing through the NMOSFET 10 .

The NMOSFETs 21 and 22 are both sense transistors that are synchronously driven with the NMOSFET 10, and generate sense currents Is and Is2 corresponding to the output current Io. The size ratio between NMOSFET 10 and NMOSFETs 21 and 22 is m:1 (where m>1). Therefore, the sense currents Is and Is2 have the magnitude of the output current Io reduced by 1/m. Like the NMOSFET 10, the NMOSFETs 21 and 22 are turned on when the gate drive signal G1 is at high level and turned off when the gate voltage G1 is at low level.

The sense resistor 23 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (=Is×Rs+Vo) corresponding to the sense current Is, where Vo is applied to the external terminal T2. It is a current-to-voltage conversion element that produces an output voltage appearing.

The gate control unit 30 performs on/off control of the NMOSFET 10 by generating a gate drive signal G1 obtained by increasing the current capability of the gate control signal S1 and outputting it to the gates of the NMOSFET 10 (and the NMOSFETs 21 and 22). The gate control section 30 has a function of controlling the NMOSFET 10 so as to limit the output current Io according to the overcurrent protection signal S71.

The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=the logic level for turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply section 60, so that the control logic section 40 is in an operating state to control the gate. The signal S1 becomes high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=the logic level for turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so the control logic section 40 is in a non-operating state, and gate control is performed. The signal S1 becomes low level (=GND). In addition, the control logic unit 40 monitors various abnormal protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-described abnormality protection signals. there is

The signal input unit 50 is a Schmitt trigger that receives the input of the external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60 . For example, the external control signal Si becomes high level when the NMOSFET 10 is turned on, and becomes low level when the NMOSFET 10 is turned off.

The internal power supply section 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each section of the semiconductor integrated circuit device 1 . Whether or not the internal power supply unit 60 can operate is controlled according to the external control signal Si. More specifically, the internal power supply section 60 becomes active when the external control signal Si is at high level, and becomes non-operating when the external control signal Si is at low level.

The abnormality protection unit 70 is a circuit block that detects various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a low voltage protection circuit 74. .

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality has occurred in the output current Io). For example, the overcurrent protection signal S71 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not the load 3 has an open abnormality). For example, the open protection signal S72 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (especially around the NMOSFET 10), and detects the temperature according to the detection result (=whether abnormal heat generation occurs). Generate a protection signal S73. For example, the temperature protection signal S73 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The voltage reduction protection circuit 74 generates a voltage reduction protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (=whether or not a voltage reduction abnormality has occurred). For example, the low voltage protection signal S74 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The output current detection unit 80 generates a sense current Is2 (=Io/m) corresponding to the output current Io by matching the source voltage of the NMOSFET 22 and the output voltage Vo using bias means (not shown). Output to the signal output unit 90 .

Based on the output switching signal S2, the signal output unit 90 outputs one of the sense current Is2 (corresponding to the detection result of the output current Io) and the fixed voltage V90 (corresponding to an abnormality flag, not explicitly shown in the figure) to an external terminal. Selectively output to T4. When the sense current Is2 is selectively output, the output detection voltage V80 (=Is2×R4) obtained by current/voltage conversion of the sense current Is2 by the external sense resistor 4 (resistance value: R4) is output to the ECU 2 as the state notification signal So. is transmitted to The output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So. When reading the current value of the output current Io from the state notification signal So, the state notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Gate control part>
FIG. 2 is a diagram showing a configuration example of the gate control unit 30. As shown in FIG. The gate control unit 30 in this figure includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), a capacitor 37 (capacitance value: C37), and a Zener diode 38 .

The gate driver 31 is connected between the output end of the charge pump 33 (=the end to which the boosted voltage VG is applied) and the external terminal T2 (=the end to which the output voltage Vo is applied), and controls the current capability of the gate control signal S1. A raised gate drive signal G1 is generated. The gate drive signal G1 becomes high level (=VG) when the gate control signal S1 is high level, and becomes low level (=Vo) when the gate control signal S1 is low level.

The oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33 . Whether or not the oscillator 32 can operate is controlled according to the enable signal SA from the control logic unit 40 .

The charge pump 33 is an example of a booster that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using the clock signal CLK and supplies the boosted voltage VG to the gate driver 31 . Whether or not the charge pump 33 operates is controlled according to the enable signal SB from the control logic unit 40 .

The clamper 34 is connected between the external terminal T<b>1 (=application terminal of the power supply voltage VBB) and the gate of the NMOSFET 10 . In an application in which an inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the back electromotive force of the load 3 causes the output voltage Vo to become a negative voltage (<GND). Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

The drain of NMOSFET 35 is connected to the gate of NMOSFET 10 . The source of NMOSFET 35 is connected to external terminal T2. The gate of the NMOSFET 35 is connected to the application end of the overcurrent protection signal S71. A resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35 .

The cathode of Zener diode 38 is connected to the gate of NMOSFET 10 . The anode of Zener diode 38 is connected to the source of NMOSFET 10 . The Zener diode 38 connected in this manner functions as a clamping element that limits the gate-source voltage (=VG-Vo) of the NMOSFET 10 to a predetermined value or less.

In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is raised to a high level, the gate drive signal G1 changes from a steady high level (=VG) to a predetermined time constant τ (=R36×C37). is lowered by As a result, the conductivity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71 is lowered to low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is lifted.

Thus, the gate control section 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

<Overcurrent protection circuit (comparative example)>
FIG. 3 is a diagram showing a comparative example of the overcurrent protection circuit 71 (an example of circuit configuration compared with various embodiments described later). The overcurrent protection circuit 71 of this comparative example is a circuit block that limits the output current Io flowing through the NMOSFET 10, and includes NMOSFETs 711 and 712, current sources 714 and 715, and a reference resistor 717.

For convenience of explanation, the NMOSFET 21, the sense resistor 23, the NMOSFET 35, the resistor 36, and the capacitor 37, which have already been described, are also treated as components of the overcurrent protection circuit 71 below.

Both of the first ends of the current sources 714 and 715 are connected to the application end of the boosted voltage VG. A second end of current source 714 is connected to the drain of NMOSFET 711 . A second end of current source 715 is connected to the drain of NMOSFET 712 . The drain of NMOSFET 712 is connected to the gate of NMOSFET 35 as the output terminal of overcurrent protection signal S71. The gates of NMOSFETs 711 and 712 are both connected to the drain of NMOSFET 711 . Both current sources 714 and 715 generate a reference current Iref.

The source of NMOSFET 711 is connected to the first end of reference resistor 717 (resistance value: Rref). The source of the NMOSFET 712 is connected to the first terminal of the sense resistor 23 (resistance value: Rs) together with the source of the NMOSFET 21 (=the output terminal of the sense current Is corresponding to the output current Io). The drain of the NMOSFET 21 is connected together with the drain of the NMOSFET 10 to the external terminal T1 (=the terminal to which the power supply voltage VBB is applied). The gate of the NMOSFET 21 is connected together with the gate of the NMOSFET 10 to the application terminal of the gate drive signal G1. The second terminals of the reference resistor 717 and the sense resistor 23 are both connected to the external terminal T2 (=the terminal to which the output voltage Vo is applied).

In the overcurrent protection circuit 71 of this comparative example, a reference voltage Vref (=Iref×Rref+Vo) is generated at the source of the NMOSFET 711 . On the other hand, a sense voltage Vs (=(Iref+Is)×Rs+Vo) is generated at the source of the NMOSFET 712 . Therefore, the overcurrent protection signal S71 becomes low level (=logical level when no abnormality is detected) when the sense voltage Vs is lower than the reference voltage Vref, and becomes high level (=logic level when the abnormality is not detected) when the sense voltage Vs is higher than the reference voltage Vref. = logic level at the time of abnormality detection). Therefore, by driving the NMOSFET 35 according to the overcurrent protection signal S71, the gate drive signal G1 can be controlled so as to limit the output current Io.

<Study on overcurrent detection value and overcurrent limit value>
4 and 5 are diagrams showing first and second examples, respectively, of the overcurrent protection operation in the comparative example of FIG. The output current Io is depicted.

Note that FIG. 4 shows the behavior when the output current Io increases while the NMOSFET 10 is on and the output current Io is limited. Therefore, in this figure, the power supply voltage VBB (for example, 12.5 V) has already been turned on, and the external control signal Si has already risen to high level.

On the other hand, in FIG. 5, as a result of the external control signal Si rising to a high level while the external terminal T2 is grounded or layer shorted (for example, 1Ω shorted), the output current Io decreases from the start of the semiconductor integrated circuit device 1. The behavior when the current limit is applied is shown.

"Overcurrent detection value" and "overcurrent limit value" in this specification are defined with reference to both figures. The "overcurrent detection value" refers to the current value of the output current Io (see Iocp_det in FIG. 4) when the output current Io increases and enters current limit while the NMOSFET 10 is on. The "overcurrent limit value" is the current value of the output current Io that is limited when the output current Io reaches the overcurrent detection value Iocp_det while the NMOSFET 10 is on (see Iocp_lmt in FIG. 4). ), or the current value of the output current Io (see Iocp_lmt in FIG. 5) that is current-limited from the start of the semiconductor integrated circuit device 1 due to a ground fault or layer short in the external terminal T2.

As shown in FIG. 4, when the output current Io is limited while the NMOSFET 10 is on, the overcurrent detection value Iocp_det deviates from the overcurrent limit value Iocp_lmt. In particular, when the ambient temperature Ta is low (for example, Ta=−40° C.), the deviation between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt becomes large.

On the other hand, as shown in FIG. 5, when the output current Io is limited from the start of the semiconductor integrated circuit device 1 due to the ground fault or layer short of the external terminal T2, the overcurrent detection value Iocp_det and the overcurrent detection value Iocp_det The deviation from the current limit value Iocp_lmt becomes smaller (Iocp_lmt≈Iocp_det in this figure).

In the following, the overcurrent protection operation of FIG. 4 will be considered in detail using mathematical formulas. As the sense current Is increases as the output current Io increases, the sense voltage Vs also increases. When the sense voltage Vs becomes higher than the reference voltage Vref, the overcurrent protection signal S71 becomes high level, and the output current Io is limited. At this time, the overcurrent detection value Iocp_det is expressed by the following equation (1).

Iocp_det = Iref × Rref × (Rs + Ron21) / (Rs × Ron10) … (1)

Ron10 and Ron21 indicate the on-resistances of NMOSFETs 10 and 21, respectively. In particular, Ron10 and Ron21 in equation (1) are on-resistances of the NMOSFETs 10 and 21 respectively in the full-on state (for example, Ron10 is several tens of mΩ, Ron21 and Rs are several hundred Ω).

From the above formula (1), before the current limit of the output current Io is applied, the temperature characteristics of the overcurrent detection value Iocp_det increase due to the influence of various parameters (Rs, Ron10, Ron21, and Iref) having temperature characteristics. .

On the other hand, when the output current Io is limited, the gate drive signal G1 is lowered and the on-resistances Ron10 and Ron21 increase (Ron21>>Rs). As a result, the overcurrent limit value Iocp_lmt is expressed by the following equation (2).

Iocp_lmt = Iref × Rref × Ron21 / (Rs × Ron10) … (2)

According to the above equation (2), only the sense resistor Rs and the reference current Iref affect the temperature characteristics of the overcurrent limit value Iocp_lmt after the output current Io is limited.

Comparing the above formulas (1) and (2), it can be seen that Iocp_det>Iocp_lmt when the output current Io is limited while the NMOSFET 10 is on. In particular, when the ambient temperature Ta is low, the on-resistance Ron10 of the NMOSFET 10 decreases, so the deviation between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt increases.

In order to realize Iocp_det=Iocp_lmt, it is necessary to increase the on-resistance Ron21 before current limitation and decrease the sense resistance Rs. That is, in (Rs+Ron21) on the right side of equation (1), the difference between the on-resistance Ron21 and the sense resistance Rs must be widened to the extent that the sense resistance Rs can be ignored.

However, if the on-resistance Ron21 before current limiting is increased, it becomes necessary to adjust the size ratio of the NMOSFETs 10 and 21 to increase the ratio of the sense current Is to the output current Io. As a result, the wiring width of the current path through which the sense current Is flows and the element width of the sense resistor Rs increase, resulting in an increase in chip area.

On the other hand, if the sense resistor Rs is made smaller, it becomes more susceptible to the influence of wiring impedance, resulting in greater variations in the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt.

It is also conceivable to lower the reference voltage Vref in order to realize Iocp_det=Iocp_lmt. However, if the reference voltage Vref is lowered, the input offset of the differential input stage (=NMOSFETs 711 and 712) of the comparator cannot be ignored, which may lead to deterioration in overcurrent detection accuracy.

Also, if the on-resistance Ron21 of the NMOSFET 21 and the sense resistor Rs are set to match the on-resistance Ron10 of the NMOSFET 10, deviation between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt is less likely to occur.

For example, if the NMOSFET 10 is a low on-resistance product (for example, Ron10=45 mΩ) corresponding to a large current output, the overcurrent detection value Iocp_det (and eventually the overcurrent limit value Iocp_lmt) is set to a relatively large current value (for example, about 20 A). ). This is because if the overcurrent detection value Iocp_det is raised, a larger sense current Is will flow, so that the sense resistance Rs can be reduced.

However, depending on the specifications of the set (ECU, etc.), even if the NMOSFET 10 is a low on-resistance product, it is desirable to set the overcurrent detection value Iocp_det (and eventually the overcurrent limit value Iocp_lmt) to a small current value (for example, about 4A). There is also a request to

In view of the above considerations, a novel embodiment is proposed that can reduce the deviation between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt.

<Overcurrent protection circuit (first embodiment)>
FIG. 6 is a diagram showing a first embodiment of the overcurrent protection circuit 71. As shown in FIG. The overcurrent protection circuit 71 of the present embodiment is based on the previous comparative example (FIG. 3) and further includes an NMOSFET 713, a current source 716, a logic 718 and a first voltage detection section 719. FIG. Further, NMOSFETs 21a and 21b are included in place of the NMOSFET 21 described above, and sense resistors 23a and 23b are included in place of the sense resistor 23 described above. Furthermore, in this figure, as components of the gate driver 31, a source current source 31H and a sink current source 31L are clearly shown.

A first end of each of the current sources 714 to 716 is connected to the application end of the boosted voltage VG. A second end of current source 714 is connected to the drain of NMOSFET 711 . A second end of current source 715 is connected to the drain of NMOSFET 712 . The drain of the NMOSFET 712 is connected to the gate of the NMOSFET 35 as the output terminal of the first overcurrent protection signal S71a (=corresponding to the first signal). A second end of current source 716 is connected to the drain of NMOSFET 713 . The drain of the NMOSFET 713 is connected to the logic 718 as the output terminal of the second overcurrent protection signal S71b (=corresponding to the second signal). Gates of the NMOSFETs 711 to 713 are all connected to the drain of the NMOSFET 711 . Current sources 714 to 716 all generate reference current Iref.

The source of NMOSFET 711 is connected to the first end of reference resistor 717 (resistance value: Rref). The source of the NMOSFET 712 is connected to the first terminal of the sense resistor 23a (resistance value: Rsa) together with the source of the NMOSFET 21a (=the output terminal of the first sense current Isa corresponding to the output current Io). The source of the NMOSFET 713 is connected to the first terminal of the sense resistor 23b (resistance value: Rsb) together with the source of the NMOSFET 21b (=the output terminal of the second sense current Isb corresponding to the output current Io). The drains of the NMOSFETs 21a and 21b are both connected together with the drain of the NMOSFET 10 to the external terminal T1 (=the terminal to which the power supply voltage VBB is applied). The gates of the NMOSFETs 21a and 21b are both connected together with the gate of the NMOSFET 10 to the application terminal of the gate drive signal G1. The second ends of the reference resistor 717 and the sense resistors 23a and 23b are all connected to the external terminal T2 (=the terminal to which the output voltage Vo is applied).

In the overcurrent protection circuit 71 of this embodiment, a reference voltage Vref (=Iref×Rref+Vo) is generated at the source of the NMOSFET 711 . On the other hand, a first sense voltage Vsa (=(Iref+Isa)×Rsa+Vo) is generated at the source of NMOSFET 712 . Therefore, when the first sense voltage Vsa is lower than the reference voltage Vref, the first overcurrent protection signal S71a becomes low level (=logical level when no abnormality is detected), and the first sense voltage Vsa is higher than the reference voltage Vref. Sometimes it becomes high level (=logical level at the time of abnormality detection). Therefore, by driving the NMOSFET 35 according to the first overcurrent protection signal S71a, the gate drive signal G1 can be controlled so as to limit the output current Io.

That is, among the components included in the overcurrent protection circuit 71, the NMOSFET 21a, the sense resistor 23a, the NMOSFETs 711 and 712, the current sources 714 and 715, the reference resistor 717, and the NMOSFET 35 have an output current Io of the first overcurrent detection value It functions as a limiter configured to limit the output current Io by controlling the gate drive signal G1 when Iocp1 is exceeded.

In terms of components, the NMOSFET 21a corresponds to a first sense transistor configured to be synchronously driven with the NMOSFET 10 by the gate drive signal G1 to generate the first sense current Isa corresponding to the output current Io. The sense resistor 23a corresponds to a first sense resistor configured to generate a first sense voltage Vsa according to the first sense current Isa. NMOSFETs 711 and 712, current sources 714 and 715, and reference resistor 717 correspond to a first comparator configured to compare the first sense voltage Vsa and the reference voltage Vref to generate a first overcurrent protection signal S71a. do. The NMOSFET 35 corresponds to an overcurrent limiting transistor connected between the gate of the NMOSFET 10 and the external terminal T2 and driven by the first overcurrent protection signal S71a.

Also, in the overcurrent protection circuit 71 of this embodiment, the second sense voltage Vsb (=(Iref+Isb)×Rsb+Vo) is generated at the source of the NMOSFET 713 . Therefore, when the second sense voltage Vsb is lower than the reference voltage Vref, the second overcurrent protection signal S71b becomes low level (=the logic level when the gate is not limited), and the second sense voltage Vsb is higher than the reference voltage Vref. When it is high, it becomes high level (=logic level at gate limit).

The second sense voltage Vsb is adjusted to have a higher voltage value than the first sense voltage Vsa. In other words, the second overcurrent detection value Iocp2 (details will be described later) used for determining whether or not to lower the gate drive signal G1 from the full-on signal value is smaller than the above first overcurrent detection value Iocp1. set to a value.

The logic 718 generates the discharge control signal DIS by performing a logic operation (for example, AND operation) on the second overcurrent protection signal S71b and the first voltage detection signal S11. For example, the logic 718 sets the discharge control signal DIS to a high level (=discharge logic level) when both the second overcurrent protection signal S71b and the first voltage detection signal S11 are at a high level, thereby When at least one of the protection signal S71b and the first voltage detection signal S11 is at low level, the discharge control signal DIS is set at low level (=logical level during non-discharge). Both the second overcurrent protection signal S71b and the first voltage detection signal S11 are pulse signals that set the internal power supply voltage Vreg to high level and the ground voltage GND to low level. On the other hand, the discharge control signal DIS is a pulse signal that sets the boosted voltage VG to high level and the output voltage Vo to low level. Therefore, logic 718 also functions as a level shifter.

The first voltage detection unit 719 generates the first voltage detection signal S11 by comparing the output voltage Vo and the first threshold voltage Vth1 (=voltage lower than the power supply voltage VBB by the set value VTH). For example, the first voltage detection signal S11 becomes low level when Vo>Vth1, and becomes high level when Vo<Vth1. It may be understood that the first voltage detection unit 719 compares the drain-source voltage Vds of the NMOSFET 10 with the set value VTH. In that case, it can be understood that the first voltage detection signal S11 becomes low level when Vds<VTH, and becomes high level when Vds>VTH.

The gate driver 31 includes a source current source 31H and a sink current source 31L, as previously described. The source current source 31H is connected between the boosted voltage VG application terminal and the gate of the NMOSFET 10, and generates a source current IH that flows into the gate of the NMOSFET 10. FIG. On the other hand, the sink current source 31L is connected between the gate of the NMOSFET 10 and the terminal to which the output voltage Vo is applied, and generates a sink current IL drawn from the gate of the NMOSFET 10. FIG. Here, it is assumed that the sink current IL is set to a current value larger than the source current IH.

During the ON period (Si=H) of the NMOSFET 10, when the discharge control signal DIS is at low level, the source current IH is turned on and the sink current IL is turned off. Therefore, the source current IH flows into the gate of the NMOSFET 10, so that the gate drive signal G1 rises and the NMOSFET 10 is brought into a full-on state (=a state in which the on-resistance Ron10 is the lowest). At this time, the NMOSFETs 21a and 21b are also in a full-on state (=a state in which the respective on-resistances Ron21a and Ron21b are the lowest).

On the other hand, when the discharge control signal DIS is at high level during the ON period (Si=H) of the NMOSFET 10, the sink current IL (>IH) is also turned on while the source current IH is on. Therefore, the differential current (=IL−IH>0) between the source current IH and the sink current IL is extracted from the gate of the NMOSFET 10, thereby lowering the gate drive signal G1 from its full-on signal value. As a result, the on-resistances Ron10, Ron21a, and Ron21b of the NMOSFETs 10, 21a, and 21b, respectively, become higher than in the normal state.

That is, among the components included in the overcurrent protection circuit 71, the NMOSFET 21b, the sense resistor 23b, the NMOSFETs 711 and 713, the current sources 714 and 716, the reference resistor 717, and the logic 718 are the first overcurrent detection It functions as a control section configured to reduce the signal value of the gate drive signal G1 from the full-on signal value when the second overcurrent detection value Iocp2, which is smaller than the value Iocp1, is exceeded.

In terms of components, the NMOSFET 21b corresponds to a second sense transistor configured to be synchronously driven with the NMOSFET 10 by the gate drive signal G1 to generate the second sense current Isb corresponding to the output current Io. The sense resistor 23b corresponds to a second sense resistor configured to generate a second sense voltage Vsb according to the second sense current Isb. NMOSFETs 711 and 713, current sources 714 and 716, and reference resistor 717 correspond to a second comparator configured to compare the second sense voltage Vsb and the reference voltage Vref to generate a second overcurrent protection signal S71b. do. The logic 718 functions as means for lowering the gate drive signal G1 from the full-on signal value in response to the second overcurrent protection signal S71b.

In the above example, only the sink current IL is turned on/off according to the discharge control signal DIS. At least one of the source current IH and the sink current IL should be controlled when lowering. For example, the source current IH may be turned off and the sink current IL may be turned on when the discharge control signal DIS is at high level. In this case, the magnitude relationship between the sink current IL and the source current IH is irrelevant.

FIG. 7 is a diagram showing an example of the overcurrent protection operation in the first embodiment, showing the behavior of the output current Io.

At time t1, when the output current Io becomes greater than the second overcurrent detection value Iocp2, the logic 718 starts limiting the gate drive signal G1 (=on/off of the sink current IL). Specifically, the logic 718 turns on the sink current IL to pull down the gate drive voltage G1 when the drain-source voltage Vds of the NMOSFET 10 is lower than the set value VTH, while the drain-source voltage Vds of the NMOSFET 10 becomes higher than the set value VTH, the sink current IL is turned off to stop lowering the gate drive voltage G1. By repeating the on/off of the sink current IL in this manner, the gate drive signal G1 is lowered from the full-on signal value so that the drain-source voltage Vds of the NMOSFET 10 matches the set value VTH.

After that, at time t2, when the output current Io becomes larger than the first overcurrent detection value Iocp1, the NMOSFET 35 is driven according to the first overcurrent protection signal S71a. G1 is controlled.

At this time, the on-resistance Ron20a of the NMOSFET 20a is higher than that in the normal state due to the above-described prior limitation of the gate drive signal G1. In other words, the on-resistance Ron20a is brought close to the resistance value Rsa of the sense resistor 23a in advance before the current limit is applied to the output current Io.

In this way, by making the drain-source voltage Vds of the NMOSFET 10 already open when the output current Io is limited, a state equivalent to that of FIG. 5 can be intentionally created. Therefore, it is possible to suppress the deviation between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt (Iocp1=Iocp_det≈Iocp_lmt in this figure) as compared with the preceding comparative example (see FIG. 3). .

FIG. 8 is a diagram showing Vg-Id characteristics of a transistor (here NMOSFET). The horizontal axis indicates the gate voltage Vg [V] applied to the transistor, and the vertical axis indicates the drain current Id [A] flowing through the transistor.

When a gate voltage Vg of 5 to 6 V is applied to the transistor as indicated by region α in the figure, the transistor is fully turned on, and a drain current Id of several tens of mA flows. On the other hand, when the gate voltage Vg is lowered to 2 to 3 V, the drain current Id is reduced to several mA, as indicated by region β in the figure. This means that the on-resistance of the transistor has been raised about ten times.

In view of the above, it is desirable to lower the gate drive signal G1 to an appropriate signal value in consideration of the Vg-Id characteristics of the NMOSFET 21a when performing the previously described pre-limitation of the gate drive signal G1.

<Overcurrent Protection Circuit (Second Embodiment)>
FIG. 9 is a diagram showing a second embodiment of the overcurrent protection circuit 71. As shown in FIG. The overcurrent protection circuit 71 of this embodiment is based on the above-described first embodiment (FIG. 6) and further includes a second voltage detection section 71A. Therefore, the same reference numerals as those in FIG. 6 are assigned to the components that have already been described to omit redundant description, and the characteristic portions of the present embodiment will be mainly described below.

The second voltage detection section 71A generates the second voltage detection signal S12 by comparing the output voltage Vo and the second threshold voltage Vth2. For example, the second voltage detection signal S12 becomes low level when Vo<Vth2, and becomes high level when Vo>Vth2. The second voltage detection signal S12 is understood as an output monitor signal for determining whether or not the output voltage Vo has risen.

The logic 718 generates the discharge control signal DIS by performing a logic operation (for example, AND operation) on the second overcurrent protection signal S71b, the first voltage detection signal S11 and the second voltage detection signal S12. For example, when the second overcurrent protection signal S71b, the first voltage detection signal S11, and the second voltage detection signal S12 are all at a high level, the logic 718 sets the discharge control signal DIS to a high level (=discharging logic level). ), and when at least one of the second overcurrent protection signal S71b, the first voltage detection signal S11, and the second voltage detection signal S12 is at a low level, the discharge control signal DIS is set at a low level (=logic level during non-discharge). and

That is, the logic 718 changes the gate drive signal G1 from the full-on signal value to A discharge control signal DIS is generated to pull down.

With such a configuration, only when the semiconductor integrated circuit device 1 has a steady output when the output voltage Vo rises (=when the NMOSFET 10 is fully on when the difference between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt increases), The aforementioned gate restrictions will apply. Conversely, the above-described gate limitation is not applied during the startup of the semiconductor integrated circuit device 1 when the output voltage Vo has not finished rising. Therefore, for example, when a load 3 (such as a bulb lamp) that requires a large rush current to be supplied at start-up is connected to the external terminal T2, the rush current is not unnecessarily limited. without hindrance.

<Overcurrent Protection Circuit (Third Embodiment)>
FIG. 10 is a diagram showing a third embodiment of the overcurrent protection circuit 71. As shown in FIG. The overcurrent protection circuit 71 of this embodiment is based on the second embodiment (FIG. 9) and further includes a temperature detector 71B. Therefore, the same reference numerals as those in FIG. 9 are assigned to the components that have already been described to omit redundant description, and the characteristic portions of the present embodiment will be mainly described below.

In the following description, the on-resistances Ron10, Ron21a, and Ron21b of the NMOSFETs 10, 21a, and 21b all have positive temperature characteristics, that is, the higher the ambient temperature Ta, the higher the on-resistances Ron10, Ron21a, and Ron21b. and

The temperature detection unit 71B generates the temperature detection signal S13 by comparing the ambient temperature Ta with a predetermined threshold value Tth. For example, the temperature detection signal S13 becomes low level when Ta>Tth, and becomes high level when Ta<Tth.

The logic 718 performs a logical operation (for example, a logical AND operation) on the second overcurrent protection signal S71b, the first voltage detection signal S11, the second voltage detection signal S12, and the temperature detection signal S13 to generate the discharge control signal DIS. to generate For example, the logic 718 sets the discharge control signal DIS to high level when the second overcurrent protection signal S71b, the first voltage detection signal S11, the second voltage detection signal S12, and the temperature detection signal S13 are all high level. (=discharge logic level), and discharge control when at least one of the second overcurrent protection signal S71b, the first voltage detection signal S11, the second voltage detection signal S12, and the temperature detection signal S13 is at low level. The signal DIS is set to low level (=logic level when not discharging).

In other words, the logic 718 only detects when the output voltage Vo is higher than the second threshold voltage Vth2, the ambient temperature Ta is lower than the threshold Tth, and the output current Io is higher than the second overcurrent detection value Iocp2. The discharge control signal DIS is generated so as to reduce the signal value of the gate drive signal G1 from the full-on signal value. To put it simply, when a sign of overcurrent is detected during steady output at a low temperature, the gate drive signal G1 is lowered from the full-on signal value.

With such a configuration, only when the ambient temperature Ta decreases (=when the on-resistance Ron21a of the NMOSFET 21a decreases and the difference between the overcurrent detection value Iocp_det and the overcurrent limit value Iocp_lmt increases), the above-described gate restrictions will apply. Conversely, when the ambient temperature Ta becomes higher than the threshold value Tth and the on-resistance Ron10 of the NMOSFET 10 originally rises, the aforementioned gate restriction is no longer applied. Therefore, the aforementioned gate limitation does not occur at high temperatures that may impair the current supply capability of the NMOSFET 10, so that the current supply to the load 3 is not unnecessarily blocked.

Although the present embodiment is based on the previously described second embodiment (FIG. 9), it may be based on the previously described first embodiment (FIG. 6). That is, the second voltage detection section 71A is not an essential component in this embodiment.

<Application to vehicles>
FIG. 11 is an external view showing one configuration example of a vehicle. A vehicle X of this configuration example is equipped with a battery (not shown in the drawing) and various electronic devices X11 to X18 that operate with power supplied from the battery.

In addition to the engine vehicle, the vehicle X includes an electric vehicle (BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or FCEV / FCV (xEV such as fuel cell electric vehicle/fuel cell vehicle).

Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 performs engine-related control (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.) or motor-related control (torque control, power regeneration control, etc.). It is an electronic control unit that performs

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamp] and DRL [daytime running lamp].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 is an electronic device built into vehicle X at the factory shipment stage as a standard equipment or manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.

<Summary>
The following provides a general description of the various embodiments described above.

For example, the overcurrent protection circuit disclosed in this specification outputs a switch drive signal when an output current flowing through a switch element connected between a power supply terminal and an output terminal exceeds a first overcurrent detection value. and a limiting unit configured to limit the output current by controlling the switch drive signal when the output current exceeds a second overcurrent detection value smaller than the first overcurrent detection value. and a control unit configured to reduce the signal value from the full-on signal value (first configuration).

In the overcurrent protection circuit having the first configuration, the control unit lowers the switch drive signal from the signal value at full-on so that the voltage across the switch element matches the set value (second configuration).

Further, in the overcurrent protection circuit having the first or second configuration, the limiter is synchronously driven with the switch element by the switch drive signal to generate a first sense current corresponding to the output current. and a first sense resistor configured to generate a first sense voltage responsive to the first sense current; comparing the first sense voltage and a reference voltage to generate a first signal; and an overcurrent limiting transistor connected between a control end of the switch element and the output terminal and configured to be driven by the first signal. You may make the structure (3rd structure) containing.

Further, in the overcurrent protection circuit having the third configuration, the control section is configured to be synchronously driven with the switch element by the switch drive signal to generate a second sense current corresponding to the output current. a second sense transistor and a second sense resistor configured to generate a second sense voltage responsive to the second sense current; comparing the second sense voltage and the reference voltage to generate a second signal; and a logic configured to lower the switch drive signal from the signal value at full-on in accordance with the second signal (fourth configuration). good.

In the overcurrent protection circuit having any one of the first to fourth configurations, the control unit controls the output voltage appearing at the output terminal to be higher than a threshold value and the output current to exceed the second overcurrent detection value. A configuration (fifth configuration) may be employed in which the switch drive signal is reduced from the signal value at full-on when the switch is turned on.

Further, in the overcurrent protection circuit having any one of the first to fifth configurations, the control unit controls the switch when the ambient temperature is lower than a threshold value and the output current exceeds the second overcurrent detection value. A configuration (sixth configuration) may be employed in which the drive signal is lowered from the signal value at full-on.

In the overcurrent protection circuit having any one of the first to sixth configurations, the control unit controls at least one of a source current flowing into the control terminal of the switch element and a sink current drawn from the control terminal. The switch drive signal may be reduced from the signal value at the time of full-on (seventh configuration).

Further, for example, the switch device disclosed in this specification includes a switch element, and an overcurrent protection circuit having any one of the first to seventh configurations and monitoring the output current flowing through the switch element. , (eighth configuration).

Further, for example, the electronic device disclosed in this specification has a configuration (ninth configuration) including the switch device of the eighth configuration and a load connected to the switch device.

Further, for example, the vehicle disclosed in this specification is configured to have the electronic device of the ninth configuration (tenth configuration).

<Other Modifications>
In the above-described embodiments, an automotive high-side switch LSI was taken as an example, but the application target of the overcurrent protection circuit disclosed in this specification is not limited to this. It can be widely applied not only to other vehicle-mounted IPDs (such as vehicle-mounted low-side switch LSIs and power supply LSIs) but also to semiconductor integrated circuit devices (for example, general-purpose power supply control circuits) for applications other than vehicle-mounted applications.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalence to the claims are included.

1 Semiconductor integrated circuit device (switch device)
2 ECUs
3 load 4 external sense resistor 10 NMOSFET (switch element)
20 Output current monitor 21, 21a, 21b NMOSFET
22 NMOSFETs
23, 23a, 23b sense resistor 30 gate controller 31 gate driver 31H source current source 31L sink current source 32 oscillator 33 charge pump (booster)
34 clamper 35 NMOSFET
36 resistor 37 capacitor 38 Zener diode (clamp element)
40 control logic unit 50 signal input unit 60 internal power supply unit 70 abnormality protection unit 71 overcurrent protection circuit 711, 712, 713 NMOSFET
714, 715, 716 current source 717 reference resistor 718 logic 719 first voltage detection section 71A second voltage detection section 71B temperature detection section 72 open protection circuit 73 temperature protection circuit 74 undervoltage protection circuit 80 output current detection section 90 signal output section T1~T4 External terminal X Vehicle X11~X18 Electronic equipment

Claims (10)

A limiter configured to limit the output current by controlling a switch drive signal when an output current flowing through a switch element connected between a power supply terminal and an output terminal exceeds a first overcurrent detection value. Department and
a controller configured to lower the switch drive signal from a signal value at full-on when the output current exceeds a second overcurrent detection value smaller than the first overcurrent detection value;
and an overcurrent protection circuit. 2. The overcurrent protection circuit according to claim 1, wherein said control unit lowers said switch drive signal from a full-on signal value so that a voltage across said switch element matches a set value. The limiting section includes: a first sense transistor configured to be synchronously driven with the switch element by the switch drive signal to generate a first sense current corresponding to the output current; a first sense resistor configured to generate a first sense voltage; a first comparator configured to compare the first sense voltage and a reference voltage to generate a first signal; 3. An overcurrent protection circuit according to claim 1 or 2, comprising an overcurrent limiting transistor connected between a control terminal and said output terminal and configured to be driven by said first signal. The control section includes: a second sense transistor configured to be synchronously driven with the switch element by the switch drive signal to generate a second sense current corresponding to the output current; a second sense resistor configured to generate a second sense voltage; a second comparator configured to compare the second sense voltage and the reference voltage to generate a second signal; 4. The overcurrent protection circuit of claim 3, comprising logic configured to responsively reduce the switch drive signal from a full-on signal value. 2. The controller reduces the switch drive signal from a full-on signal value when the output voltage appearing at the output terminal is higher than a threshold and the output current exceeds the second overcurrent detection value. 5. The overcurrent protection circuit according to any one of -4. 6. The controller according to any one of claims 1 to 5, wherein when the ambient temperature is lower than a threshold value and the output current exceeds the second overcurrent detection value, the switch drive signal is reduced from a full-on signal value. 1. The overcurrent protection circuit according to claim 1. 6. The control unit controls at least one of a source current flowing into a control terminal of the switch element and a sink current drawn from the control terminal to lower the switch drive signal from a signal value at full-on. The overcurrent protection circuit according to any one of Claims 1 to 3. a switch element;
The overcurrent protection circuit according to any one of claims 1 to 7, wherein the output current flowing through the switch element is monitored;
A switch device. a switch device according to claim 8;
a load connected to the switch device;
An electronic device having A vehicle comprising the electronic device according to claim 9 .

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