JP7398940B2 - switch device - Google Patents

Description

The invention disclosed herein relates to a switch device.

The applicant of the present application has previously proposed a number of new technologies regarding switch devices such as in-vehicle IPDs (intelligent power devices) (for example, see Patent Document 1).

International Publication No. 2017/187785

However, in the above-mentioned conventional switch device, there is room for further study regarding, for example, active clamp operation at high temperatures.

In particular, in recent years, in-vehicle ICs have been required to comply with ISO26262 (an international standard for electrical/electronic functional safety in automobiles), and higher reliability design has become important for in-vehicle IPDs as well. It has become.

In view of the above problems discovered by the inventors of the present application, the invention disclosed herein aims to provide a switch device that can optimize active clamp operation at high temperatures, for example. .

The switch device disclosed herein has a first terminal connected to a first voltage application end, a second terminal connected to a first end of a load, a second terminal connected to the second end of the load, and a second terminal connected to a first end of a load. a third terminal connected to an application terminal of two voltages; a switch element connected between the first terminal and the second terminal; and an output of the second terminal based on the first voltage in a first state. A configuration (first configuration) including a first active clamper that limits the voltage, and a second active clamper that limits the output voltage based on the second voltage reference in a second state different from the first state. ing.

In the switch device having the first configuration, the first active clamper limits the voltage across the switch element to a first clamp voltage or less, and the second active clamper limits the voltage across the switch element to a voltage below the first clamp voltage. It is preferable to adopt a configuration (second configuration) in which the voltage is limited to a second clamp voltage or less that is lower than the first clamp voltage.

Further, in the switching device having the first or second configuration, the first active clamper limits the output voltage to a first lower limit voltage or more that is lower than the first voltage by a predetermined value, and the second active clamper Preferably, the output voltage is limited to a second lower limit voltage or higher that is lower than the second voltage by a predetermined value and higher than the first lower limit voltage (third configuration).

Further, in the switch device having any one of the first to third configurations, the second active clamper includes a switch circuit that is turned on in the second state, and a cathode connected to the first end of the switch circuit and an anode. a diode connected to the third terminal; and a first Zener diode whose cathode is connected to the second end of the switch circuit and whose anode is connected to the second terminal (fourth configuration). It is better to make it .

In the switch device having a fourth configuration, the second active clamper further includes a second Zener diode having a cathode connected to the second end of the switch circuit and an anode connected to the control end of the switch element. It is preferable to adopt a configuration (fifth configuration) including the above.

Further, in the switch device having any one of the first to fifth configurations, the first active clamper includes a Zener diode having a cathode connected to the first terminal, and an anode connected to the anode of the Zener diode. A configuration including a diode, and a transistor having a first end connected to the first terminal, a second end connected to the control end of the switch element, and a control end connected to the cathode of the diode (sixth configuration).

Furthermore, in the switch device having any one of the first to sixth configurations, the first voltage may be a power supply voltage and the second voltage may be a ground voltage (seventh configuration).

Further, in the switch device having any one of the first to seventh configurations described above, the first state is a high temperature abnormality undetected state, and the second state is a high temperature abnormality detected state ( It is preferable to use the eighth configuration).

Further, the electronic device disclosed in this specification has a configuration (ninth configuration) including a switch device having any one of the above-described first to eighth configurations, and a load connected to the switch device. It is said that

In the electronic device having the ninth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor (tenth configuration).

Further, the vehicle disclosed in this specification has a configuration (eleventh configuration) including an electronic device having the ninth or tenth configuration described above.

According to the invention disclosed herein, it is possible to provide a switch device that can optimize active clamp operation at high temperatures, for example.

Block diagram showing the overall configuration of a semiconductor integrated circuit device Block diagram showing an example of the configuration of the gate control section Diagram showing an example of the configuration of the first active clamper Diagram showing the first active clamp operation Diagram showing an example of the configuration of the second active clamper Diagram showing the second active clamp operation (first example) Diagram showing the second active clamp operation (second example) External view showing an example of the configuration of a vehicle

<Semiconductor integrated circuit device (overall configuration)>
FIG. 1 is a block diagram showing the overall configuration of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of the present embodiment is an in-vehicle high-side switch IC (=in-vehicle It is a type of IPD).

Note that the semiconductor integrated circuit device 1 includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of power supply voltage VBB (for example, 12V) from a battery (not shown). The external terminal T2 is a load connection terminal or output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T3 is a signal input terminal (IN pin) for receiving an external input of an external control signal Si from the ECU 2. The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the status notification signal So to the ECU 2. Note that an external sense resistor 4 is externally connected between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 also includes an NMOSFET 10, an output current monitoring section 20, a gate control section 30, a control logic section 40, a signal input section 50, an internal power supply section 60, an abnormality protection section 70, and an output current monitoring section 20. The current detection section 80 and the signal output section 90 are integrated.

The NMOSFET 10 is a high voltage (eg, 42V) power transistor whose drain is connected to an external terminal T1 and whose source is connected to an external terminal T2. The NMOSFET 10 connected in this manner functions as a switching element (high side switch) for conducting/blocking a current path from the application end of the power supply voltage VBB to the ground end via the load 3. The NMOSFET 10 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level.

Note that the NMOSFET 10 may be designed so that the on-resistance value when fully turned on is several tens of mΩ. However, the lower the on-resistance value of the NMOSFET 10, the more likely an overcurrent will flow and abnormal heat generation will occur when the external terminal T2 has a ground fault (=when the output is shorted to the ground terminal or a similar low potential terminal). Therefore, the lower the on-resistance value of the NMOSFET 10, the more important the overcurrent protection circuit 71 and temperature protection circuit 73, which will be described later, become.

The output current monitoring section 20 includes NMOSFETs 21 and 21' and a sense resistor 22, and generates a sense voltage Vs (=corresponding to a sense signal) according to the output current Io flowing through the NMOSFET 10.

NMOSFETs 21 and 21' are both mirror transistors connected in parallel to NMOSFET 10, and generate sense currents Is and Is' according to output current Io. The size ratio between NMOSFET 10 and NMOSFETs 21 and 21' is m:1 (m>1). Therefore, the sense currents Is and Is' have the magnitude of the output current Io reduced by 1/m. Note that, like the NMOSFET 10, the NMOSFETs 21 and 21' are turned on when the gate drive signal G1 is at a high level, and turned off when the gate voltage G2 is at a low level.

The sense resistor 22 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (=Is×Rs+Vo, where Vo is connected to the external terminal T2) corresponds to the sense current Is. It is a current/voltage conversion element that generates an output voltage (which appears on the output voltage).

The gate control unit 30 performs on/off control of the NMOSFETs 10 and 21 by generating a gate drive signal G1 with increased current capability of the gate control signal S1 and outputting it to the gates of the NMOSFETs 10 and 21, respectively. Note that the gate control section 30 has a function of controlling the NMOSFETs 10 and 21 so as to limit the output current Io according to the overcurrent protection signal S71.

The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=the logic level when turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply unit 60, so the control logic unit 40 is in the operating state, and the gate control The signal S1 becomes high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=the logic level when turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so the control logic section 40 becomes inactive, and the gate control The signal S1 becomes low level (=GND). The control logic unit 40 also monitors various abnormality protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and reduced voltage protection signal S74). Note that the control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-mentioned abnormality protection signals. There is.

The signal input section 50 is a Schmitt trigger that receives an input of an external control signal Si from the external terminal T3 and transmits it to the control logic section 40 and the internal power supply section 60. Note that, for example, the external control signal Si becomes high level when turning on the NMOSFET 10, and becomes low level when turning off the NMOSFET 10.

Internal power supply section 60 generates a predetermined internal power supply voltage Vreg from power supply voltage VBB and supplies it to each section of semiconductor integrated circuit device 1 . Note that whether or not the internal power supply unit 60 is operable is controlled according to an external control signal Si. More specifically, the internal power supply section 60 is in an active state when the external control signal Si is at a high level, and is in an inactive state when the external control signal Si is at a low level.

The abnormality protection unit 70 is a circuit block that detects various abnormalities in the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a low voltage protection circuit 74. .

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality has occurred in the output current Io). Note that the overcurrent protection signal S71 becomes, for example, a low level when no abnormality is detected, and becomes a high level when an abnormality is detected.

The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not an open abnormality has occurred in the load 3). Note that the open protection signal S72 becomes, for example, a low level when no abnormality is detected, and becomes a high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (particularly around the NMOSFET 10), and adjusts the temperature according to the detection result (=whether or not abnormal heat generation is occurring). A protection signal S73 is generated. Note that the temperature protection signal S73 becomes, for example, a low level when no abnormality is detected, and becomes a high level when an abnormality is detected.

The reduced voltage protection circuit 74 generates a reduced voltage protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (=whether or not a reduced voltage abnormality has occurred). Note that the voltage reduction protection signal S74 becomes, for example, a low level when no abnormality is detected, and becomes a high level when an abnormality is detected.

The output current detection unit 80 generates a sense current Is' (=Io/m) according to the output current Io by matching the source voltage of the NMOSFET 21' and the output voltage Vo using bias means (not shown). and outputs it to the signal output section 90.

The signal output unit 90 outputs one of the sense current Is' (=corresponds to the detection result of the output current Io) and the fixed voltage V90 (=corresponds to the abnormality flag, not shown in this figure) to an external source based on the output selection signal S2. Select output to terminal T4. When the sense current Is' is selectively output, the output detection voltage V80 (=Is'×R4) obtained by converting the sense current Is' into a current/voltage using an external sense resistor 4 (resistance value: R4) is used as the status notification signal So. ) is transmitted to the ECU2. The output detection voltage V80 becomes higher as the output current Io becomes larger, and becomes lower as the output current Io becomes smaller. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So. Note that when reading the current value of the output current Io from the status notification signal So, the status notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the status notification signal So, the logic level of the status notification signal So may be determined using a threshold value that is slightly lower than the fixed voltage V90.

<Gate control section>
FIG. 2 is a block diagram showing an example of the configuration of the gate control section 30. As shown in FIG. The gate control unit 30 of this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), and a capacitor 37 (capacitance value: C37). , and a Zener diode 38.

The gate driver 31 is connected between the output end of the charge pump 33 (=the end to which the boosted voltage VG is applied) and the external terminal T2 (=the end to which the output voltage Vo is applied), and controls the current capacity of the gate control signal S1. Generate an enhanced gate drive signal G1. Note that the gate drive signal G1 becomes a high level (=VG) when the gate control signal S1 is at a high level, and becomes a low level (=Vo) when the gate control signal S1 is at a low level.

The oscillator 32 generates a clock signal CLK of a predetermined frequency and outputs it to the charge pump 33. Note that whether or not the oscillator 32 is operable is controlled according to an enable signal Sa from the control logic section 40.

The charge pump 33 is an example of a booster unit that generates a boosted voltage VG higher than the power supply voltage VBB and supplies it to the gate driver 31 by driving a flying capacitor using the clock signal CLK. Note that whether or not the charge pump 33 is operable is controlled according to an enable signal Sb from the control logic section 40.

The clamper 34 is connected between the external terminal T1 (=the end to which power supply voltage VBB is applied) and the gate of the NMOSFET 10. In an application where an inductive load 3 is connected to the external terminal T2, when switching the NMOSFET 10 from on to off, the output voltage Vo becomes a negative voltage (<GND) due to the back electromotive force of the load 3. Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

The drain of NMOSFET 35 is connected to the gate of NMOSFET 10. The source of NMOSFET 35 is connected to external terminal T2. The gate of NMOSFET35 is connected to the application terminal of overcurrent protection signal S71. Further, a resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35.

The cathode of the Zener diode 38 is connected to the gate of the NMOSFET 10. The anode of the Zener diode 38 is connected to the source of the NMOSFET 10. The Zener diode 38 connected in this manner functions as a clamp element that limits the gate-source voltage (=VG-Vo) of the NMOSFET 10 to a predetermined value or less.

In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is raised to a high level, the gate drive signal G1 changes from a normal high level (=VG) to a predetermined time constant τ (=R36×C37). It is being lowered. As a result, the conductivity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71 is lowered to a low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the degree of conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is lifted.

In this way, the gate control section 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

<First active clamper>
FIG. 3 is a diagram showing an example of the configuration of the clamper 34 (corresponding to the first active clamper). The clamper 34 of this configuration example includes an m-stage (for example, m=8) Zener diode array 341, an n-stage (for example, n=3) diode array 342, and an NMOSFET 343.

The cathode of the Zener diode array 341 and the drain of the NMOSFET 343 are connected together with the drain of the NMOSFET 10 to an external terminal T1 (corresponding to a first terminal connected to the application terminal of the power supply voltage VBB). The anode of Zener diode string 341 is connected to the anode of diode string 342. The cathode of diode string 342 is connected to the gate of NMOSFET 343. The source of the NMOSFET 343 is connected to the gate of the NMOSFET 10 (=the end to which the gate drive signal G1 is applied). The source of the NMOSFET 10 is connected to an external terminal T2 (corresponding to the second terminal connected to the first end of the load 3). Note that as the load 3, an inductive load such as a coil or a solenoid may be connected.

In the following, the gate-source voltages of the NMOSFETs 10 and 343 are Vgs1 and Vgs2, the breakdown voltage of the Zener diode string 341 is mVZ, the forward drop voltage of the diode string 342 is nVF, and the first active clamp by the clamper 34 is Explain the operation.

FIG. 4 is a timing chart showing the first active clamp operation by the clamper 34, and in order from the top, the external control signal Si, the output voltage Vo (solid line), the gate drive signal G1 (broken line), the temperature protection signal S73, Also depicted is the output current Io. In this figure, it is assumed that an inductive load is connected as the load 3.

At time t11, when the external control signal Si rises to a high level (=the logic level when turning on the NMOSFET 10), the gate drive signal G1 rises to a high level and the NMOSFET 10 turns on, so the output current Io starts flowing. , the output voltage Vo rises to near the power supply voltage VBB.

After that, at time t12, when the external control signal Si falls to a low level (=the logic level when turning off the NMOSFET 10), the gate drive signal G1 falls to a low level, and the NMOSFET 10 is turned off. At this time, the inductive load (coil, solenoid, etc.) connected as the load 3 continues to flow the output current Iout until the energy stored during the ON period of the NMOSFET 10 is released. As a result, the output voltage Vo decreases to a negative voltage lower than the ground voltage GND.

However, when the output voltage Vo becomes a negative voltage, the NMOSFET 10 is turned on by the action of the clamper 34, so that the output current Io is discharged. Therefore, the output voltage Vo is limited to a lower limit voltage VBB-α (for example, VBB-50V) which is lower than the power supply voltage VBB by a predetermined value α (=mVZ+nVF+Vgs1+Vgs2).

That is, the clamper 34 limits the output voltage Vo based on the power supply voltage VBB, thereby limiting the drain-source voltage Vds (=VBB-Vo) of the NMOSFET 10 to a predetermined clamp voltage Vclp (=α) or less.

The clamp voltage Vclp needs to be set to a voltage value higher than the maximum rated value of the power supply voltage VBB and lower than the drain-source breakdown voltage of the NMOSFET 10. Further, it can be said that the higher the clamp voltage Vclp, the better the performance of the semiconductor integrated circuit device 1, but in view of the active clamp withstand capacity E (mJ), the lower the clamp voltage Vclp is, the better.

Note that the active clamp tolerance E (mJ) of the semiconductor integrated circuit device 1 is determined from the clamp voltage Vclp (V), the output current Io (A), and the discharge time t (ms) using the following equation.

E(J)=Vclp(V)×Io(A)×t(ms)

By the way, for power ICs including IPDs, the power IC is turned on/off for multiple cycles (300 cycles or more depending on the grade) with the output terminal shorted to supply or ground via a path with inductance (for example, 5 mH). A load short circuit reliability test (AEC-Q100-012) repeated over 1 million cycles) is required.

Here, if the overcurrent limit value of the power IC is set to several tens of A to 100 A, a large amount of power of several hundred W to 1000 W is consumed. Therefore, the power IC is repeatedly turned on and off in a state in which overheating is detected (high temperature state: for example, a state in which the temperature protection signal S73 rises to a high level after time t13 in FIG. 4).

At such high temperatures, the active clamp withstand capacity E (mJ) of the semiconductor integrated circuit device 1 decreases due to the influence of heat. Therefore, in order to prevent thermal breakdown of the NMOSFET 10, etc., it is desirable to lower the clamp voltage Vclp. However, in the clamper 34 that limits the output voltage Vo based on the power supply voltage VBB, there is a limit to how much the clamp voltage Vclp can be lowered. Therefore, a second active clamper that can limit the output voltage Vo based on the ground voltage GND at high temperatures will be proposed below.

<Second active clamper>
FIG. 5 is a diagram showing a configuration example of the clamper 39 (corresponding to a second active clamper). The clamper 39 of this configuration example includes a switch circuit 391, a diode 392, and Zener diodes 393 and 394.

The switch circuit 391 is turned on/off according to the temperature protection signal S73. More specifically, the switch circuit 391 is turned on when the temperature is high (S73=H) and turned off when the temperature is not high (S73=L).

A cathode of the diode 392 is connected to a first end of the switch circuit 391. The anode of the diode 392 is connected to an external terminal T5 (corresponding to the third terminal connected to the second end of the load 3 and the end to which the ground voltage GND is applied). The cathodes of Zener diodes 393 and 394 are connected to the second end of switch circuit 391. The anode of the Zener diode 393 is connected to the external terminal T2. The anode of Zener diode 394 is connected to the gate of NMOSET10.

In the following, the second active clamp operation by the clampers 34 and 39 will be described in detail, assuming that the breakdown voltage of the Zener diode 393 is Vz and the forward voltage drop of the diode 392 is Vf.

FIG. 6A is a timing chart showing the second active clamp operation (first example) by the clampers 34 and 39, and in order from the top, the external control signal Si, the output voltage Vo, the temperature protection signal S73, and the output current Io is depicted. In this figure as well, it is assumed that an inductive load is connected as the load 3.

At time t21, when the external control signal Si is raised to a high level (=the logic level when turning on the NMOSFET 10), the NMOSFET 10 is turned on, so the output current Io starts flowing and the output voltage Vo reaches the vicinity of the power supply voltage VBB. Rise. It is assumed that at this point, no abnormal heat generation in the semiconductor integrated circuit device 1 has been detected, and the temperature protection signal S73 is at a low level (=logic level at non-high temperature).

Thereafter, at time t22, when the external control signal Si falls to a low level (=the logic level when turning off the NMOSFET 10), the NMOSFET 10 is turned off. At this time, the inductive load (coil, solenoid, etc.) connected as the load 3 continues to flow the output current Iout until the energy stored during the ON period of the NMOSFET 10 is released. As a result, the output voltage Vo decreases to a negative voltage lower than the ground voltage GND.

However, when the output voltage Vo becomes a negative voltage, the NMOSFET 10 is turned on by the action of the clamper 34, so that the output current Io is discharged. Therefore, the output voltage Vo is limited to a lower limit voltage VBB-α (for example, VBB-50V) which is lower than the power supply voltage VBB by a predetermined value α (=mVZ+nVF+Vgs1+Vgs2).

That is, the clamper 34 limits the drain-source voltage Vds (=VBB-Vo) of the NMOSFET 10 to a predetermined clamp voltage Vclp1 (=α) or less by limiting the output voltage Vo based on the power supply voltage VBB. The active clamping operation by the clamper 34 up to this point is as described above with reference to FIG. 4.

On the other hand, at time t23, when abnormal heat generation in the semiconductor integrated circuit device 1 is detected and the temperature protection signal S73 rises to a high level (=logic level at high temperature), the switch circuit 391 is turned on. As a result, a closed loop is formed via the switch circuit 391, the Zener diode 393, the load 3, and the diode 392, so the clamper 39 becomes effective. Therefore, the output voltage Vo is limited to a lower limit voltage GND-β (for example, GND-10V) that is lower than the ground voltage GND by a predetermined value β (=Vz+Vf) and higher than the above-mentioned lower limit voltage VBB-α. .

In other words, the clamper 39 clamps the drain-source voltage Vds (=VBB-Vo) of the NMOSFET 10 to a level lower than the clamp voltage Vclp1 by limiting the output voltage Vo with reference to the ground voltage GND at high temperature (S73=H). The voltage is limited to Vclp2 or less.

In this way, by introducing the clamper 39, at high temperatures (S73=H) when the active clamp withstand capacity E (mJ) of the semiconductor integrated circuit device 1 decreases, the active clamp operation based on the power supply voltage VBB is changed to the ground voltage. Automatically switches to active clamp operation based on GND. Therefore, since the clamp voltage Vclp can be lowered, it is possible to prevent thermal breakdown of the NMOSFET 10 and the like.

FIG. 6B is a timing chart showing the second active clamp operation (second example) by the clampers 34 and 39, and as in FIG. 6A mentioned above, the external control signal Si, the output voltage Vo, the temperature protection Signal S73 and output current Io are depicted. In this figure as well, it is assumed that an inductive load is connected as the load 3.

As shown in this figure, if abnormal heat generation in the semiconductor integrated circuit device 1 is detected before time t22 (S73=H), the point at which the output voltage Vo drops to a negative voltage at time t22 Then, active clamping operation by the clamper 39 is applied. Therefore, the output voltage Vo is limited to the lower limit voltage GND-β from the beginning without decreasing to the lower limit voltage VBB-α.

<Application to vehicles>
FIG. 7 is an external view showing an example of the configuration of a vehicle. The vehicle X of this configuration example is equipped with a battery (not shown in the figure) and various electronic devices X11 to X18 that operate by receiving power from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual locations for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.).

The electronic device X12 is a lamp control unit that controls turning on and off of a high intensity discharged lamp (HID), daytime running lamp (DRL), or the like.

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that controls the drive of door locks, security alarms, and the like.

Electronic equipment X16 is electronic equipment that is installed in vehicle It is.

The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an on-vehicle blower, an oil pump, a water pump, or a battery cooling fan.

Note that the semiconductor integrated circuit device 1, ECU 2, and load 3 described above can be incorporated into any of the electronic devices X11 to X18.

<Other variations>
Further, in the above embodiment, the explanation was given using an in-vehicle high-side switch IC as an example, but the application target of the invention disclosed in this specification is not limited to this, and for example, It can be widely applied not only to other vehicle-mounted IPDs (vehicle-mounted low-side switch ICs, vehicle-mounted power supply ICs, etc.), but also to semiconductor integrated circuit devices other than vehicle-mounted applications.

Further, in the above embodiment, an example was given in which the first active clamp operation and the second active clamp operation are switched depending on whether or not a temperature abnormality is detected. A clamping operation may be performed, and a second active clamping operation may be performed in a second state different from the first state.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims rather than the description of the above embodiments. It should be understood that all changes that come within the meaning and range of equivalence of the claims are included.

The invention disclosed in this specification can be used for in-vehicle IPDs and the like.

1 Semiconductor integrated circuit device (switch device)
2 ECU
3 Load 4 External sense resistor 10 NMOSFET (switch element)
20 Output current monitoring section 21, 21' NMOSFET
22 Sense resistor 30 Gate control section 31 Gate driver 32 Oscillator 33 Charge pump (boosting section)
34 Clamper (first active clamper)
341 Zener diode string 342 Diode string 343 NMOSFET
35 NMOSFET
36 Resistor 37 Capacitor 38 Zener diode (clamp element)
39 Clamper (second active clamper)
391 Switch circuit 392 Diode 393, 394 Zener diode 40 Control logic section 50 Signal input section 60 Internal power supply section 70 Abnormality protection section 71 Overcurrent protection circuit (overcurrent protection section)
72 Open protection circuit 73 Temperature protection circuit 74 Low voltage protection circuit 80 Output current detection section 90 Signal output section T1 to T5 External terminals X Vehicle X11 to X18 Electronic equipment

Claims (5)

a first terminal connected to a first voltage application terminal;
a second terminal connected to the first end of the load;
a third terminal connected to a second end of the load and a second voltage application end;
a switch element connected between the first terminal and the second terminal;
a first active clamper that limits the output voltage of the second terminal based on the first voltage reference in a first state in which a high temperature abnormality is not detected ;
a second active clamper that limits the output voltage based on the second voltage reference in a second state that is the high temperature abnormality detection state ;
has
The first active clamper includes a Zener diode having a cathode connected to the first terminal, a diode having an anode connected to the anode of the Zener diode, and a second end having a first end connected to the first terminal. a transistor connected to a control end of the switch element, the control end of which is connected to the cathode of the diode, and the output voltage is increased by limiting the voltage across the switch element to a first clamp voltage or less. limiting the voltage to a first lower limit voltage that is lower than the first voltage by a predetermined value;
The second active clamper includes a switch circuit that is turned on in the second state, a diode whose cathode is connected to the first end of the switch circuit and whose anode is connected to the third terminal, and a diode whose cathode is connected to the switch circuit. a first Zener diode connected to a second end and having an anode connected to the second terminal; a second Zener diode having a cathode connected to the second end of the switch circuit and an anode connected to the control end of the switch element; and a Zener diode, by limiting the voltage across the switch element to a second clamp voltage lower than the first clamp voltage, the output voltage is lower than the second voltage by a predetermined value. A switch device that limits the voltage to a second lower limit voltage higher than the first lower limit voltage . The switch device according to claim 1, wherein the first voltage is a power supply voltage and the second voltage is a ground voltage. An electronic device comprising the switch device according to claim 1 or 2 and a load connected to the switch device. The electronic device according to claim 3, wherein the load is a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor. A vehicle comprising the electronic device according to claim 3 or 4 .

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