JP2015004297A - Switch control circuit, ignitor, engine ignition device, and vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switch control circuit capable of suppressing heat generation at a switch element.SOLUTION: A switch control circuit includes: an output part for generating an on/off signal of a switch element; a control part for drive control of the output part according to an ignition direction signal Sc; a current detection part for detecting a current Ic flowing through the switch element; and a current limiting part for limiting the current Ic at a first upper limit value Ilmt1 before the elapse of a current maintenance period T3 after the ignition direction signal Sc is set at a logical level for turn on, e.g., high level, and limiting the current Ic at a second upper limit value Ilmt2, which is smaller than the first upper limit Ilmt1 after the elapse of the current maintenance period T3. The current limiting part includes a function for variably controlling the second upper limit value Ilmt2 according to a predetermined switching signal, e.g., a voltage monitoring signal according to a voltage value of a power supply voltage Vcc.

Description

  The present invention relates to a switch control circuit.

  In recent years, a switch control circuit incorporated in an igniter (an electronic component constituting a vehicle engine ignition device) includes an IGBT [insulated gate] according to an ignition instruction signal IGT [iginition timing signal] input from an ECU [engine control unit]. In addition to a function of turning on / off a switching element such as a bipolar transistor] or a MOSFET [metal oxide semiconductor field effect transistor], a current limiting function for limiting a current flowing through the switching element to a predetermined upper limit value or less, an ignition instruction signal IGT A timer protection function for forcibly turning off the switch element when a predetermined waiting period (for example, about 100 ms) elapses with the logic level at ON being incorporated.

Japanese Patent Laid-Open No. 9-324731 (FIG. 11, etc.)

  By the way, when the ignition instruction signal IGT is unintentionally fixed to the logic level at the time of ON due to a malfunction of the ECU or the like, the switch element remains in the ON state until the timer protection operation is activated. At this time, since the current flowing through the switch element is limited to a predetermined upper limit value or less, there is little possibility of causing a serious accident such as ignition or smoke generation of the switch element.

  However, in the conventional switch control circuit, the upper limit value of the current flowing through the switch element is set to a current value that can sufficiently maintain the ignition performance of the engine. Therefore, the power consumption of the switch element during timer protection standby is not necessarily small, and the temperature of the switch element continues to rise. When the temperature of the switch element (particularly the temperature of the back surface bonded to the frame using solder) reaches the melting point of the solder (200 to 250 ° C. for lead-free solder), the solder melts and the switch element is removed from the frame. There was a problem of peeling off.

  As a method for suppressing the temperature rise of the switch element, it is conceivable to improve the heat dissipation performance by increasing the size of the frame on which the switch element is mounted or by increasing the size of the switch element itself. However, such a method has a problem that the chip size of the switch control circuit (and hence the package size of the igniter) increases, leading to an increase in cost.

  In Patent Document 1, as a technique for suppressing heat generation of the switch element, the primary current of the ignition coil is limited to a larger first constant current control value at the beginning of energization of the switch element, and thereafter, the primary current A technique has been proposed in which two types of constant current control values are sequentially switched so as to limit the current to a smaller second constant current control value. However, there has been room for further improvement in view of the fact that the amount of heat generated (power consumption) of the switch element varies depending on the power supply voltage applied to the ignition coil.

  In view of the above-mentioned problems found by the inventors of the present application, the present invention provides a switch control circuit capable of suppressing heat generation of a switch element, and an igniter, an engine ignition device, and a vehicle using the switch control circuit. Objective.

  The switch control circuit disclosed in the present specification includes: an output unit that generates an on / off signal of a switch element; a control unit that controls driving of the output unit in response to an ignition instruction signal; and a flow that flows through the switch element A current detection unit for detecting a current; the current flowing through the switch element is limited to a first upper limit value until a predetermined current maintenance period elapses after the ignition instruction signal is set to a logic level at the time of turning on; A current limiting unit that limits a current flowing through the switch element to a second upper limit value that is smaller than the first upper limit value after the current maintaining period has elapsed, and the current limiting unit generates a predetermined switching signal. Accordingly, the second upper limit value is variably controlled (first configuration).

  The switch control circuit having the first configuration further includes a power supply voltage monitoring unit that monitors a power supply voltage, generates a voltage monitoring signal, and outputs the voltage monitoring signal as the switching signal to the current limiting unit (first operation). 2).

  In the switch control circuit having the second configuration, the current limiting unit may be configured to lower the second upper limit as the power supply voltage is higher (third configuration).

  Further, in the switch control circuit having the first to third configurations, the switch element when a predetermined standby period longer than the current maintaining period elapses while the ignition instruction signal is kept at the logic level when turned on. It is preferable to adopt a configuration (fourth configuration) having a function as a timer protection unit for forcibly turning off.

  In the switch control circuit having any one of the first to fourth configurations, the first upper limit value is set to a current value capable of maintaining the engine ignition performance, and the current maintenance period includes the ignition instruction. A configuration (fifth configuration) that is set to be equal to or greater than the maximum value that can be set as the ON period of the signal is preferable.

  Further, in the switch control circuit having any one of the first to fifth configurations, the second upper limit value may be set to a current value (sixth configuration) that can ignite the engine.

  Further, the switch control circuit having any one of the first to sixth configurations may be configured to be integrated on a semiconductor chip (seventh configuration).

  The igniter disclosed in the present specification has a configuration (eighth configuration) formed by packaging the switch element and the switch control circuit having the seventh configuration.

  The engine ignition device disclosed in the present specification includes an ignition coil, an igniter having the eighth configuration for turning on / off a current flowing in a primary coil of the ignition coil, and a secondary of the ignition coil. It is set as the structure (9th structure) which has a spark plug connected to a side coil.

  A vehicle disclosed in the present specification includes an engine ignition device having the ninth configuration, a car battery that supplies electric power to the engine ignition device, an engine control unit that controls the engine ignition device, It is set as the structure (10th structure) which has.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the switch control circuit which can suppress the heat_generation | fever of a switch element, an igniter using the same, an engine ignition device, and a vehicle.

The block diagram which shows the whole structure of the vehicle X provided with the engine ignition device 1 Plan view showing a frame mounting example in the igniter 10 Block diagram showing a first configuration example of the switch control circuit 11 Circuit diagram showing a specific circuit configuration in the first configuration example Timing chart showing an example of switch control operation Ic-Psw characteristic diagram of switch element 12 Block diagram showing a second configuration example of the switch control circuit 11 Circuit diagram showing a specific circuit configuration in the second configuration example Timing chart showing relationship between ignition instruction signal Sc and collector current Ic External view showing a configuration example of the vehicle X

<Overall configuration>
FIG. 1 is a block diagram showing an overall configuration of a vehicle X provided with an engine ignition device 1. The engine ignition device 1 is used in a form mounted on the vehicle X together with the car battery 2 and the ECU 3. In the following description, an element that functions as a resistor on an electric circuit is generalized and referred to as a “resistance element”, and an element that functions as a capacitor (including parasitic capacitance) is generalized and referred to as a “capacitance element”. There is.

  As shown in FIG. 1, the engine ignition device 1 includes an igniter 10, an ignition coil 20, and a spark plug 30.

  The igniter 10 is provided as a semiconductor integrated circuit device in which a switch control circuit 11, a switch element 12, and a resistance element 13 are packaged.

  The switch control circuit 11 is formed as an LSI chip, and has a function (gate control function) for generating a gate signal Sg of the switch element 12 in response to an ignition instruction signal Sc input from the ECU 3. Further, the switch control circuit 11 monitors the detection voltage (emitter voltage) Ve corresponding to the collector current Ic (emitter current Ie) of the switch element 12, and sets the collector current Ic below a predetermined upper limit value according to the monitoring result. It has a function to limit (current limiting function). Further, the switch control circuit 11 forcibly turns off the switch element 12 when the predetermined standby period has passed while the ignition instruction signal Sc is kept at the logic level (for example, high level) when the ignition instruction signal Sc is turned on, and the collector current Ic is changed. It also has a function to shut off (timer protection function). The configuration and operation of the switch control circuit 11 will be described later.

  Although not depicted in this figure, when it is necessary to make the igniter 10 compatible with an electronic fuel injection device (EFI), the switch control circuit 11 sends an ignition confirmation signal IGF to the ECU. A function for sending [ignition confirmation signal] may be added.

  The switch element 12 is a switch element that is turned on / off by the switch control circuit 11, and an IGBT is employed in FIG. The switch element 12 has a gate connected to the switch control circuit 11, a collector connected to the primary coil 21 of the ignition coil 20, and an emitter connected to the resistance element 13 (for example, the emitter of the IGBT and the GND frame). The wire is grounded via a resistance component). Note that a MOSFET may be employed as the switch element 12.

  The ignition coil 20 includes a primary coil 21 having a winding number N1 and a secondary coil 22 having a winding number N2 (> N1). The power supply voltage Vcc supplied from the car battery 2 is changed to a higher secondary voltage Vsp. It plays the role of converting (boosting). The first end of the primary side coil 21 and the first end of the secondary side coil 22 are both connected to the car battery 2. The second end of the primary coil 21 is connected to the collector of the switch element 12. The second end of the secondary coil 22 is connected to the spark plug 30, and the secondary voltage Vsp generated in the secondary coil 22 is supplied to the spark plug 30.

  The spark plug 30 uses the secondary voltage Vsp obtained by the ignition coil 20 to generate a spark for igniting the engine (not shown in FIG. 1) of the vehicle X.

  The car battery 2 is a power source for supplying power to various electrical components mounted on the vehicle X including the engine ignition device 1.

  The ECU 3 executes various controls related to the engine drive of the vehicle X. In particular, the ECU 3 outputs an ignition instruction signal Sc used for operation control of the igniter 10 (particularly, the switch control circuit 11) as one of the various controls. Specifically, the ECU 3 sets the ignition instruction signal Sc to a logic level (eg, high level) when the switch element 12 is turned on, and sets the ignition instruction signal Sc when the switch element 12 is turned off. A logic level (for example, a low level) is set.

<Frame mounting>
FIG. 2 is a plan view showing a frame mounting example in the igniter 10. Each of the wires W1 to W6 is a bonding wire, and is formed of a metal such as copper (Cu), aluminum (Al), or gold (Au), for example.

  The first frame FR1 is a frame connected to the car battery 2. The second frame FR2 is a frame connected to the ground terminal (GND). The third frame FR3 is a frame connected to the ECU 3. The fourth frame FR4 is a frame connected to the collector of the switch element 12. Note that the back surface of the switch element 12 electrically connected to the collector is bonded to the upper surface of the fourth frame FR4 with solder (for example, lead-free solder).

  The switch control circuit 11 includes a gate control pad 11a, an emitter voltage detection pad 11b, a grounding pad 11c, a power supply pad 11d, and a signal input pad 11e as means for establishing an electrical connection with the outside. including.

  The gate control pad 11a of the switch control circuit 11 and the gate pad 12a of the switch element 12 are connected by wire bonding using the wire W1. Therefore, the gate signal Sg is supplied from the switch control circuit 11 to the switch element 12 through the wire W1.

  The emitter voltage detection pad 11b of the switch control circuit 11 and the emitter pad 12b of the switch element 12 are connected by wire bonding using the wire W2. Therefore, the detection voltage Ve is output from the emitter of the switch element 12 to the switch control circuit 11 through the wire W2.

  The emitter pad 12b of the switch element 12 is also connected to the second frame FR2 by wire bonding using the wire W3. Therefore, the emitter current Ie output from the emitter of the switch element 12 flows to the second frame FR2 via the wire W3.

  The resistance component of the wire W3 is used as the resistance element 13 described above. In that case, the resistance value, temperature characteristic, and the like of the resistance element 13 are determined by the type of metal forming the wire W3, its shape, and the like. The resistance value RE of the wire W3 can be several mΩ to several tens mΩ. Therefore, even if the emitter current Ie flowing through the resistance element 13 is several A to several tens A, the detection voltage Ve can be suppressed to several mV to several tens of mV, which hinders the operation of the switch element 12 (self-cutting). It is hard to produce.

  Note that the form in which the wire W3 is bonded to the ground end is not limited to the form described above. For example, it may be bonded to the grounding pad 11 c of the switch control circuit 11.

  The grounding pad 11c of the switch control circuit 11 is connected to the second frame FR2 by wire bonding using the wire W4.

  The power supply pad 11d of the switch control circuit 11 is connected to the first frame FR1 by wire bonding using the wire W5. Accordingly, power is supplied from the car battery 2 to the switch control circuit 11 through the wire W5.

  The signal input pad 11e of the switch control circuit 11 is connected to the third frame FR3 by wire bonding using the wire W6. Accordingly, the ignition instruction signal Sc is supplied from the ECU 3 to the switch control circuit 11 through the wire W6.

<Switch control circuit (first configuration example)>
FIG. 3 is a block diagram illustrating a first configuration example of the switch control circuit 11. The switch control circuit 11 of the first configuration example includes a control unit 111, a totem pole output unit 112, an oscillation unit 113, a current detection unit 114, and a current limiting unit 115 as main circuit elements.

  The control unit 111 has a function as a pre-driver unit that generates drive signals (gate signals GH and GL) of the totem pole output unit 112 in response to the ignition instruction signal Sc input from the ECU 3 via the signal input pad 11e. ing. The control unit 111 includes a timer 111a (counter) that counts the number of pulses of the clock signal CLK, and also has a function as a timer protection unit that forcibly turns off the switch element 12 according to the count value CT. ing. Furthermore, the control unit 111 also has a function as a heat generation suppression unit that generates a heat generation suppression signal ST according to the count value CT. The heat generation suppression signal ST is input to the current limiter 115 and is used as a mask signal for a second current limit signal Sd2 described later.

  The totem pole output unit 112 includes a P-channel MOS field effect transistor MH and an N-channel MOS field effect transistor ML (corresponding to an upper transistor and a lower transistor) forming a CMOS [Complementary MOS] structure, a current limiting resistor RH, and Includes RL. The source of the transistor MH is connected to the application terminal (corresponding to the upper power supply terminal) of the power supply voltage Vcc through the power supply pad 11d. The drain of the transistor MH is connected to the first end of the current limiting resistor RH. The second end of the current limiting resistor RH and the first end of the current limiting resistor RL are connected to each other, and the connection node is connected to the gate of the switch element 12 through the gate control pad 11a. The second end of the current limiting resistor RL is connected to the drain of the transistor ML. The source of the transistor ML is connected to the ground terminal (corresponding to the lower power supply terminal) via the ground pad 11c. The gates of the transistors MH and ML are connected to the application terminals of the gate signals GH and GL, respectively. When the current limiting resistors RH and RL are replaced with a single current limiting resistor, a single current limiting resistor may be inserted between the connection node of the transistors MH and ML and the gate of the switch element 12.

  The oscillation unit 113 outputs a clock signal CLK having a predetermined frequency to the control unit 111.

  The current detection unit 114 detects the state of the collector current Ic (emitter current Ie) by monitoring the detection voltage Ve input via the emitter voltage detection pad 11b, and the first current limit signal Sd1 according to the detection result. And a second current limiting signal Sd2. The first current limiting signal Sd1 is at a low level when the collector current Ic is smaller than the first upper limit value Ilmt1, and is at a high level when the collector current Ic is larger than the first upper limit value Ilmt1. On the other hand, the second current limiting signal Sd2 becomes low level when the collector current Ic is smaller than the second upper limit value Ilmt2 (<Ilmt1), and becomes high level when the collector current Ic is larger than the second upper limit value Ilmt2. .

  The current limiter 115 appropriately adjusts the high level of the gate signal Sg during the ON period of the switch element 12 according to the current limit signals Sd1 and Sd2 and the heat generation suppression signal ST, thereby changing the collector current Ic to the first upper limit value. It is limited to Ilmt1 or less or the second upper limit value Ilmt2. The configuration and operation of the current limiting unit 115 will be described in detail later.

  FIG. 4 is a circuit diagram showing a specific circuit configuration in the first configuration example. In the switch control circuit 11 of the first configuration example, the current detection unit 114 includes comparators CMP1 and CMP2. The non-inverting input terminals (+) of the comparators CMP1 and CMP2 are both connected to the application terminal of the detection voltage Ve. The inverting input terminal (−) of the comparator CMP1 is connected to the application terminal of the threshold voltage Vth1 corresponding to the first upper limit value Ilmt1. The inverting input terminal (−) of the comparator CMP2 is connected to an application terminal for a threshold voltage Vth2 (<Vth1) corresponding to the second upper limit value Ilmt2.

  The output terminal of the comparator CMP1 corresponds to the output terminal of the first current limit signal Sd1. The first current limit signal Sd1 is at a low level when the detection voltage Ve is lower than the threshold voltage Vth1, and is at a high level when the detection voltage Ve is higher than the threshold voltage Vth1. On the other hand, the output terminal of the comparator CMP2 corresponds to the output terminal of the second current limiting signal Sd2. The second current limit signal Sd2 is at a low level when the detection voltage Ve is lower than the threshold voltage Vth2, and is at a high level when the detection voltage Ve is higher than the threshold voltage Vth2.

  The current limiting unit 115 includes resistors R1 and R2, N-channel MOS field effect transistors M1 and M2, and AND gates A1 and A2. The first ends of the resistors R1 and R2 are both connected to the gate of the switch element 12. The second ends of the resistors R1 and R2 are connected to the drains of the transistors M1 and M2, respectively. The sources of the transistors M1 and M2 are both connected to the ground terminal. The resistance values of the resistors R1 and R2 are R1> R2. The on-resistance values of the transistors M1 and M2 are assumed to be negligibly lower than the resistance values of the resistors R1 and R2.

  The gate of the transistor M1 is connected to the application end of the first current limiting signal Sd1. Accordingly, the transistor M1 is turned on when the first current limit signal Sd1 is at a high level, and is turned off when the first current limit signal Sd1 is at a low level. On the other hand, the gate of the transistor M2 is connected to the application end of the masked second current limit signal Sd2 '(corresponding to the second current limit signal Sd2 subjected to the mask process using the heat generation suppression signal ST). Accordingly, the transistor M2 is turned on when the masked second current limit signal Sd2 'is at a high level, and turned off when the masked second current limit signal Sd2' is at a low level.

  The AND gate A1 performs a logical product operation of the second current limit signal Sd2 and the heat generation suppression signal ST to generate a masked second current limit signal Sd2 '. Accordingly, when the heat generation suppression signal ST is at a high level, the second current limit signal Sd2 is directly output as a masked second current limit signal Sd2 ′, while when the heat generation suppression signal ST is at a low level, The masked second current limit signal Sd2 ′ is fixed at a low level without depending on the second current limit signal Sd2.

  When both the transistors M1 and M2 are turned off in a state where the gate signal Sg is at a high level (a state where both the gate signals GH and GL are at a low level), a current flows through the resistors R1 and R2. Since both paths are cut off, the high level of the gate signal Sg is substantially the power supply voltage Vcc.

  On the other hand, when the transistor M1 is turned on and the transistor M2 is turned off, a resistance voltage dividing circuit is formed by the current limiting resistor RH and the resistor R1, so that the high level of the gate signal Sg is lowered by one step from the power supply voltage Vcc. The first limit level V1 (= {R1 / (RH + R1)} × Vcc). Therefore, the continuity of the switch element 12 is reduced, and the collector current Ic flowing through the switch element 12 is reduced.

  When the transistor M1 is turned off and the transistor M2 is turned on, a resistance voltage dividing circuit is formed by the current limiting resistor RH and the resistor R2, so that the high level of the gate signal Sg is further increased from the first limiting level V1. The second limit level V2 is lowered by one step (= {R2 / (RH + R2)} × Vcc). Accordingly, since the conductivity of the switch element 12 is further lowered, the collector current Ic flowing through the switch element 12 is further reduced.

  FIG. 5 is a timing chart showing an example of the switch control operation. In order from the top, the ignition instruction signal Sc, the gate signals GH and GL, the gate signal Sg, the collector voltage Vc, the secondary voltage Vsp, and the current limit signals Sd1 and Sd2 The clock signal CLK, the count value CT of the timer unit 111a, the heat generation suppression signal ST, the collector current Ic, and the back surface temperature TP of the switch element 12 are depicted.

  At time t1, when the ignition instruction signal Sc is switched to the logic level (high level) when it is on, both the gate signals GH and GL are lowered to the low level, so that the transistor MH is turned on and the transistor ML is turned off. Become. As a result, the gate signal Sg becomes high level (approximately the power supply voltage Vcc), and the switch element 12 is turned on. Therefore, the collector current Ic (emitter current Ie) flows from the car battery 2 through the primary coil 21 of the ignition coil 20, the switch element 12, and the resistance element 13 to the ground terminal, and flows to the primary coil 21. Energy is stored. Further, after time t1, the timer 111a starts pulse counting of the clock signal CLK. The count value CT of the timer 111a may be reset to a zero value at the pulse edge (rising edge or falling edge) of the ignition instruction signal Sc.

  Thereafter, at time t3, when the ignition instruction signal Sc is switched to a logic level (for example, low level) at the time of off, the gate signals GH and GL are both raised to high level, so that the transistor MH is turned off and the transistor ML Is turned on. As a result, the gate signal Sg becomes a low level (almost the ground voltage GND), and the switch element 12 is turned off. At this time, a large counter electromotive force is generated in the primary coil 21 due to the self-induction action, and the collector voltage Vc rapidly increases. Further, a larger electromotive force is generated in the secondary coil 22 according to the turn ratio (N2 / N1) due to the mutual induction action with the primary coil 21. Due to the electromotive force of the secondary coil 22 generated in this way, a very high secondary voltage Vsp (10,000 volts or more) is applied to the spark plug 30, and a spark is generated to ignite the engine. .

  At times t1 to t3, the high level period T1 of the ignition instruction signal Sc is as short as about several ms, and the collector current Ic does not exceed the first upper limit value Ilmt1, so the first current limit signal Sd1 is maintained at the low level. ing. Therefore, the high level of the gate signal Sg is not lowered to the first limit level V1 according to the first current limit signal Sd1. In addition, since the count value CT has not reached the threshold value Nx (corresponding to the current maintaining period T3) from time t1 to time t3, the heat generation suppression signal ST is at a low level (logical level when masking the second current limit signal Sd2). Is maintained. Therefore, even if the collector current Ic exceeds the second upper limit value Ilmt2 at the time t2 and the second current limit signal Sd2 rises to the high level, the high level of the gate signal Sg is accordingly increased to the second limit level V2 (< V1) is not pulled down.

  On the other hand, after time t4, the ignition instruction signal Sc is fixed at a high level, and at time t6, the collector current Ic reaches the first upper limit value Ilmt1. As a result, the first current limit signal Sd1 rises to a high level after time t6, and the high level of the gate signal Sg is lowered to the first limit level V1 with an appropriate time constant, so that the collector current Ic is reduced to the first upper limit value Ilmt1. Limited to Note that, from time t4 to t6, the count value CT does not reach the threshold value Nx, and the heat generation suppression signal ST is maintained at a low level, so that the second current limit signal Sd2 rises to a high level at time t5. However, the high level of the gate signal Sg is not lowered to the second limit level V2 accordingly.

  Further, at time t7, when the count value CT reaches the threshold value Nx, the heat generation suppression signal ST rises to a high level under the determination that the predetermined current maintenance period T3 has elapsed while the ignition instruction signal Sc remains at a high level. The mask of the second current limit signal Sd2 is released. As a result, after time t7, the high level of the gate signal Sg is lowered from the first limit level V1 to the lower second limit level V2 with an appropriate time constant, so that the collector current Ic is further higher than the first upper limit value Ilmt1. It is limited to a low second upper limit value Ilmt2. Therefore, after time t7, it is possible to reduce power consumption and suppress continuous heat generation so that the back surface temperature TP of the switch element 12 does not reach the melting point MP of the solder. As the collector current Ic decreases to the second upper limit value Ilmt2, the first current limit signal Sd1 falls to a low level at time t7.

  Further, when the count value CT reaches the threshold value Ny (> Nx) at time t8, the switch element is determined based on the determination that the predetermined standby period T2 (about 100 ms) has elapsed while the ignition instruction signal Sc remains at the high level. An abnormality protection operation (timer protection operation) is performed in which the collector current Ic is cut off by forcibly turning off 12. That is, at time t8, the gate signals GH and GL are both raised to a high level without waiting for the falling edge of the ignition instruction signal Sc, and the gate signal Sg is lowered to a low level (substantially the ground voltage GND). .

  In the switch control circuit 11 of the first configuration example, the first upper limit value Ilmt1 is a current value that can sufficiently maintain the engine ignition performance required for the engine ignition device 1 (depending on the circuit constant of the ignition coil 30). It is desirable to set to about 10-15A. Further, it is desirable to set the current maintaining period T3 to be equal to or greater than the maximum value (10 ms to 30 ms) that can be set as the high level period T1 of the ignition instruction signal Sc.

  According to such a setting, as long as the high level period T1 of the ignition instruction signal Sc is normal and the ignition timing (the falling edge of the ignition instruction signal Sc) has arrived before the current maintenance period T3 has elapsed, the collector Since the current Ic is not lowered to the second upper limit value Ilmt2, it is possible to suppress the heat generation of the switch element 12 while maintaining the ignition performance of the engine.

  On the other hand, if the ignition timing does not arrive before the current maintenance period T3 elapses, the collector current Ic is lowered to the second upper limit value Ilmt2 after the current maintenance period T3 elapses, so that the continuous temperature rise of the switch element 12 is suppressed. This makes it possible to prevent the solder from melting.

  If the engine needs to be ignited during timer protection operation (time t8) as the specification of the engine ignition device 1, the second upper limit value Ilmt2 is a current value that can ignite the engine (the circuit constant of the ignition coil 30). However, it is desirable to set it to about 5-8A. According to such a setting, it is possible to ignite the engine during the timer protection operation while suppressing the temperature rise of the switch element 12 as much as possible.

<Dependence of Ic-Psw characteristics on power supply voltage>
FIG. 6 is a diagram illustrating the power supply voltage dependency of the Ic-Psw characteristic in the switch element 12. Since the collector of the switch element 12 is connected to the application terminal of the power supply voltage Vcc via the primary winding 21 of the ignition coil 20, the collector-emitter voltage VCE of the switch element 12 varies according to the power supply voltage Vcc. To do. Accordingly, since the power consumption Psw (= Ic × VCE) of the switch element 12 also varies according to the power supply voltage Vcc, the Ic-Psw characteristic of the switch element 12 has a dependency on the power supply voltage Vcc.

  Specifically, as shown in FIG. 6, the higher the power supply voltage Vcc, the larger the amount of change in power consumption Psw with respect to the amount of change in collector current Ic (the slope of Psw with respect to Ic). That is, when the power supply voltage Vcc is high, the power consumption Psw can be greatly reduced by reducing the collector current Ic. On the other hand, as the power supply voltage Vcc is lowered, the power consumption Psw is less likely to decrease even if the collector current Ic is lowered.

  In the following, a detailed description will be given of the switch control circuit 11 of the second configuration example to which further improvements are added in view of the above knowledge.

<Switch control circuit (second configuration example)>
FIG. 7 is a block diagram illustrating a second configuration example of the switch control circuit 11. The switch control circuit 11 of the second configuration example has basically the same configuration as the previous first configuration example, and is characterized in that a power supply voltage monitoring unit 116 is added. Therefore, the same components as those in the first configuration example are denoted by the same reference numerals as those in FIG. 2, and redundant descriptions are omitted. In the following, the characteristic portions of the second configuration example are mainly described.

  The power supply voltage monitoring unit 116 monitors the power supply voltage Vcc that affects the Ic-Psw characteristics of the switch element 12 and generates a voltage monitoring signal SV. The voltage monitoring signal SV is input to the current limiting unit 115, and is used as a switching signal (selection signal) for variably controlling the second upper limit value Ilmt2 according to the voltage value of the power supply voltage Vcc.

  FIG. 8 is a circuit diagram showing a specific circuit configuration in the second configuration example. In the switch control circuit 11 of the second configuration example, the current detection unit 114 is a component for outputting the three systems of the second current limit signal Sd2 (H, M, L) as the second current limit signal Sd2. As an alternative, three comparators CMP2 (H, M, L) are included instead of the previous comparator CMP2.

  The non-inverting input terminal (+) of the comparator CMP2H is connected to the application terminal for the detection voltage Ve. An inverting input terminal (−) of the comparator CMP2H is connected to an application terminal of a threshold voltage Vth2H (<Vth1) corresponding to the upper limit value Ilmt2H (<Ilmt1). The output terminal of the comparator CMP2H corresponds to the output terminal of the second current limit signal Sd2H. The second current limit signal Sd2H is at a low level when the detection voltage Ve is lower than the threshold voltage Vth2H, and is at a high level when the detection voltage Ve is higher than the threshold voltage Vth2H.

  The non-inverting input terminal (+) of the comparator CMP2M is connected to the application terminal of the detection voltage Ve. An inverting input terminal (−) of the comparator CMP2M is connected to an application terminal of a threshold voltage Vth2M (<Vth2H) corresponding to the upper limit value Ilmt2M (<Ilmt2H). The output terminal of the comparator CMP2M corresponds to the output terminal of the second current limit signal Sd2M. The second current limit signal Sd2M is at a low level when the detection voltage Ve is lower than the threshold voltage Vth2M, and is at a high level when the detection voltage Ve is higher than the threshold voltage Vth2M.

  The non-inverting input terminal (+) of the comparator CMP2L is connected to the application terminal of the detection voltage Ve. An inverting input terminal (−) of the comparator CMP2L is connected to an application terminal of a threshold voltage Vth2L (<Vth2L) corresponding to the upper limit value Ilmt2L (<Ilmt2M). The output terminal of the comparator CMP2L corresponds to the output terminal of the second current limit signal Sd2L. The second current limit signal Sd2L is at a low level when the detection voltage Ve is lower than the threshold voltage Vth2L, and is at a high level when the detection voltage Ve is higher than the threshold voltage Vth2L.

  The current limiter 115 replaces the previous resistor R2 as a component for variably controlling the second upper limit value Ilmt2 to three stages Ilmt2 (H, M, L) according to the voltage monitoring signal SV (a, b). Three resistors R2 (H, M, L), three N-channel MOS field effect transistors M2 (H, M, L) in place of the transistor M2, and three in place of the AND gate A1. An AND gate A1 (H, M, L) is included.

  The first ends of the resistors R2 (H, M, L) are all connected to the gate of the switch element 12. The second end of the resistor R2 (H, M, L) is connected to the drain of the transistor M2 (H, M, L), respectively. The sources of the transistors M2 (H, M, L) are all connected to the ground terminal. The resistance value of the resistor R2 (H, M, L) is R2H> R2M> R2L. The on-resistance value of the transistor M2 (H, M, L) is assumed to be negligibly lower than the resistance value of the resistor R2 (H, M, L).

  The gate of the transistor M2H is connected to the application end of the masked second current limit signal Sd2H ′ (corresponding to the second current limit signal Sd2H subjected to the mask process using the heat generation suppression signal ST). Accordingly, the transistor M2H is turned on when the masked second current limit signal Sd2H 'is at a high level, and turned off when the masked second current limit signal Sd2H' is at a low level.

  The gate of the transistor M2M is connected to the application terminal of the masked second current limit signal Sd2M ′ (corresponding to the second current limit signal Sd2M masked by the heat generation suppression signal ST and the voltage monitoring signal SVa). Yes. Accordingly, the transistor M2M is turned on when the masked second current limit signal Sd2M 'is at a high level, and turned off when the masked second current limit signal Sd2M' is at a low level.

  The gate of the transistor M2L is connected to the application terminal of the masked second current limit signal Sd2L ′ (corresponding to the second current limit signal Sd2L masked by the heat generation suppression signal ST and the voltage monitoring signal SVb). Yes. Accordingly, the transistor M2L is turned on when the masked second current limit signal Sd2L 'is at a high level, and turned off when the masked second current limit signal Sd2L' is at a low level.

  The AND gate A1H generates a mask-processed second current limit signal Sd2H ′ by performing an AND operation between the second current limit signal Sd2H and the heat generation suppression signal ST. Therefore, when the heat generation suppression signal ST is at a high level, the second current limit signal Sd2H is directly output as a masked second current limit signal Sd2H ′, while when the heat generation suppression signal ST is at a low level, The masked second current limit signal Sd2H ′ is fixed at a low level without depending on the second current limit signal Sd2H.

  The AND gate A1M generates a second current limit signal Sd2M ′ that has been masked by performing a logical product operation of the second current limit signal Sd2M, the heat generation suppression signal ST, and the voltage monitoring signal SVa. Therefore, when both the heat generation suppression signal ST and the voltage monitoring signal SVa are at a high level, the second current limit signal Sd2M is directly output as a masked second current limit signal Sd2M ′, while the heat generation suppression signal ST. When at least one of the voltage monitoring signal SVa is at a low level, the masked second current limit signal Sd2M ′ is fixed at a low level without depending on the second current limit signal Sd2M.

  The AND gate A1L performs a logical product operation of the second current limit signal Sd2L, the heat generation suppression signal ST, and the voltage monitoring signal SVb to generate the masked second current limit signal Sd2L ′. Therefore, when both the heat generation suppression signal ST and the voltage monitoring signal SVb are at a high level, the second current limit signal Sd2L is directly output as the masked second current limit signal Sd2L ′, while the heat generation suppression signal ST. When at least one of the voltage monitoring signal SVb is at a low level, the masked second current limit signal Sd2L ′ is fixed at a low level without depending on the second current limit signal Sd2L.

  In a state where the gate signal Sg is at a high level (a state where both the gate signals GH and GL are at a low level), the transistor M2H is turned on, and the other transistors (M1, M2M, M2L) are all off. In this case, since a resistance voltage dividing circuit is formed by the current limiting resistor RH and the resistor R2H, the high level of the gate signal Sg is {R2H / (RH + R2H)} × Vcc.

  When the transistor M2M is turned on and all of the other transistors (M1, M2H, M2L) are turned off, a resistance voltage dividing circuit is formed by the current limiting resistor RH and the resistor R2M. The high level of Sg is {R2M / (RH + R2M)} × Vcc.

  When the transistor M2L is turned on and all of the other transistors (M1, M2H, M2M) are turned off, a resistance voltage dividing circuit is formed by the current limiting resistor RH and the resistor R2L. The high level of Sg is {R2L / (RH + R2L)} × Vcc.

  The power supply voltage monitoring unit 116 includes resistors R3x to R3z and comparators CMP3a and CMP3b. The resistors R3x to R3z are connected in series between the application terminal of the power supply voltage Vcc and the application terminal of the ground voltage GND, and generate resistors VDa and VDb (where VDa <VDb) of the power supply voltage Vcc. A ladder circuit is formed.

  The comparator CMP3a compares the divided voltage VDa applied to the non-inverting input terminal (+) and the threshold voltage Vth3 applied to the inverting input terminal (−) to generate a voltage monitoring signal SDa. The voltage monitoring signal SDa is at a high level when the divided voltage VDa is higher than the threshold voltage Vth3, and is at a low level when the divided voltage VDa is lower than the threshold voltage Vth3.

  The comparator CMP3b compares the divided voltage VDb applied to the non-inverting input terminal (+) and the threshold voltage Vth3 applied to the inverting input terminal (−) to generate the voltage monitoring signal SDb. The voltage monitoring signal SDb is at a high level when the divided voltage VDb is higher than the threshold voltage Vth3, and is at a low level when the divided voltage VDb is lower than the threshold voltage Vth3.

  Hereinafter, the variable control of the second upper limit value Ilmt2 will be specifically described with different cases depending on the level of the power supply voltage Vcc.

  First, a case where a power supply voltage Vcc (for example, Vcc = 16 V) at which both voltage monitoring signals SDa and SDb are at a high level is applied will be described. In this case, the masking of the second current limit signal Sd2 (M, L) by the voltage monitoring signals SDa and SDb is released. Therefore, after the current maintaining period T3 has elapsed, the collector current Ic is limited to the upper limit value Ilmt2L (the smallest current value in three stages) according to the second current limit signal Sd2L (the solid line of the collector current Ic in FIG. 9). See). Note that the first current limit signal Sd1 and the second current limit signal Sd2 (H, M) are also at the high level when the current maintaining period T3 has elapsed, but both are at the low level as the collector current Ic is reduced. Therefore, finally, only the on / off control of the transistor M2L according to the second current limiting signal Sd2L is effective.

  Next, a case where a power supply voltage Vcc (for example, Vcc = 14 V) at which the voltage monitoring signal SDa becomes high level and the voltage monitoring signal SDb becomes low level is applied will be described. In this case, the masking of the second current limiting signal Sd2M by the voltage monitoring signal SDa is released, while the masking of the second current limiting signal SdL by the voltage monitoring signal SDb is not released. Therefore, after the current maintenance period T3 has elapsed, the collector current Ic is limited to the upper limit value Ilmt2M (an intermediate current value in three stages) in accordance with the second current limit signal Sd2M (the broken line of the collector current Ic in FIG. 9). See). Note that the first current limit signal Sd1 and the second current limit signal Sd2H are also at the high level at the time when the current maintenance period T3 has elapsed, but since both become the low level as the collector current Ic is lowered, Specifically, only the on / off control of the transistor M2M according to the second current limit signal Sd2M is effective.

  Next, a case where a power supply voltage Vcc (for example, Vcc ≦ 10 V) at which both voltage monitoring signals SDa and SDb are at a low level is applied will be described. In this case, the masking of the second current limit signal Sd2 (M, L) by the voltage monitoring signals SDa and SDb is not released. On the other hand, the second current limiting signal Sd2H is not subject to masking by the voltage monitoring signals SDa and SDb. Therefore, after the current maintaining period T3 has elapsed, the collector current Ic is limited to the upper limit value Ilmt2H (the largest current value in three stages) according to the second current limit signal Sd2H (one point of the collector current Ic in FIG. 9). See chain line). Note that the first current limit signal Sd1 is also at the high level at the time when the current maintaining period T3 has elapsed, but it is at the low level as the collector current Ic is lowered. Only the on / off control of the transistor M2H according to the above becomes effective.

  As described above, in the switch control circuit 11 of the second configuration example, the current limiting unit 115 is configured to lower the second upper limit value Ilmt2 as the power supply voltage Vcc is higher (see FIG. 9). With such a configuration, when the power supply voltage Vcc is high, the collector current Ic is greatly reduced to effectively suppress the heat generation of the switch element 12, while the lowering of the power supply voltage Vcc reduces the amount of reduction of the collector current Ic. This makes it possible to maintain a current value that can ignite the engine.

  In the above description, the configuration in which the second upper limit value Ilmt2 is variably controlled using the voltage monitoring signal SV generated by the power supply voltage monitoring unit 116 as a switching signal has been described as an example. However, the generation subject of the switching signal is limited to this. For example, the second upper limit value Ilmt2 may be variably controlled in accordance with a switching signal from the ECU 3.

<Vehicle>
FIG. 10 is an external view showing a configuration example of the vehicle X. The vehicle X in this configuration example includes on-vehicle devices X11 to X17 and a battery (corresponding to the car battery 2 in FIG. 1, not shown in FIG. 10) that supplies power to these on-vehicle devices X11 to X17. Yes.

  The in-vehicle device X11 is an engine control unit (corresponding to the ECU 3 in FIG. 1) that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.). The engine ignition device 1 mounted on the vehicle X is controlled by the engine control unit.

  The in-vehicle device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The in-vehicle device X13 is a transmission control unit that performs control related to the transmission.

  The in-vehicle device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power Steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The in-vehicle device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The in-vehicle device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment item or a manufacturer option product such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, and an air conditioner.

  The in-vehicle device X17 is an electronic device that is arbitrarily attached to the vehicle X by the user, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

<Other variations>
The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used for an igniter, for example.

1 Engine ignition device 2 Car battery 3 ECU
10 igniter 11 switch control circuit 11a gate control pad 11b emitter voltage detection pad 11c grounding pad 11d power supply pad 11e signal input pad 111 control unit (pre-driver unit, timer protection unit, heat generation suppression unit)
111a timer 112 totem pole output unit 113 oscillating unit 114 current detecting unit 115 current limiting unit 116 power supply voltage monitoring unit 12 switch element 12a gate pad 12b emitter pad 13 resistance element 20 ignition coil 21 primary side coil 22 secondary side coil 30 ignition plug W1-W6 wire (bonding wire)
FR1 to FR4 frame MH P-channel MOS field effect transistor (upper transistor)
ML N-channel MOS field effect transistor (lower transistor)
RH, RL Current limiting resistor CMP1, CMP2 (H, M, L), CMP3 (a, b) Comparator R1, R2 (H, M, L), R3 (x, y, z) Resistor M1, M2 (H, M, L) N-channel MOS field effect transistor A1 (H, M, L) AND gate X Vehicle X11-X17 In-vehicle device

Claims (10)

An output for generating an on / off signal of the switch element;
A control unit that performs drive control of the output unit in response to an ignition instruction signal;
A current detector for detecting a current flowing through the switch element;
The current flowing through the switch element is limited to the first upper limit value until the predetermined current maintenance period elapses after the ignition instruction signal is set to the logic level at the time of ON, and after the current maintenance period elapses, A current limiting unit that limits a current flowing through the switch element to a second upper limit value smaller than the first upper limit value;
Have
The switch control circuit, wherein the current limiting unit has a function of variably controlling the second upper limit value according to a predetermined switching signal.   The switch control circuit according to claim 1, further comprising a power supply voltage monitoring unit that monitors a power supply voltage, generates a voltage monitoring signal, and outputs the voltage monitoring signal as the switching signal to the current limiting unit.   The switch control circuit according to claim 2, wherein the current limiter lowers the second upper limit value as the power supply voltage is higher.   The control unit functions as a timer protection unit that forcibly turns off the switch element when a predetermined standby period longer than the current maintenance period has elapsed while the ignition instruction signal is kept at the logic level at the time of ON. The switch control circuit according to claim 1, further comprising:   The first upper limit value is set to a current value that can maintain engine ignition performance, and the current maintenance period is set to be equal to or greater than a maximum value that can be set as an ON period of the ignition instruction signal. The switch control circuit according to any one of claims 1 to 4.   The switch control circuit according to claim 1, wherein the second upper limit value is set to a current value that can ignite the engine.   7. The switch control circuit according to claim 1, wherein the switch control circuit is integrated on a semiconductor chip. A switch element;
A switch control circuit according to claim 7;
An igniter characterized by being packaged. Ignition coil,
The igniter according to claim 8 for turning on / off a current flowing through a primary side coil of the ignition coil,
A spark plug connected to the secondary coil of the ignition coil;
An engine ignition device comprising: The engine ignition device according to claim 9,
A car battery for supplying electric power to the engine ignition device;
An engine control unit for controlling the engine ignition device;
The vehicle characterized by having.

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