JP6272442B2 - Switching power supply device, semiconductor device, TV - Google Patents

Description

  The present invention relates to a control circuit for a switching regulator. The present invention also relates to a switching power supply device.

<First Background Technology>
Power transistors are used in switching regulators, motor drivers, and various other electronic circuits. FIG. 1 is a circuit diagram showing a configuration example of a step-up switching regulator having a power transistor.

  The switching regulator 2r includes a control circuit 100r, an inductor L1, a rectifying diode D1, and an output capacitor C1.

The control circuit 100r includes a switching transistor M1, which is a power transistor, a pulse signal generation unit 10, and a driver circuit 20r. The output voltage _VOUT of the switching regulator 2r is divided by resistors R1 and R2. The pulse signal generator 10 receives the feedback voltage V _FB corresponding to the output voltage _VOUT of the switching regulator 2r, and generates a pulse signal S _PWM whose duty ratio is adjusted so that the feedback voltage V _FB approaches the target level. . The driver circuit 20r switches the switching transistor M1 based on the pulse signal _{S PWM.}

In order to switch the switching transistor M1 on and off, it is necessary to switch the level of the voltage (gate signal V _G ) of the control terminal (gate) between two levels of high level (power supply voltage) and low level (ground voltage). is there.

<Second Background Technology>
Conventionally, a switching power supply apparatus that performs PWM [pulse width modulation] type switching control in a heavy load region and a PFM [pulse frequency modulation] type switching control in a light load region has been disclosed and proposed.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2008-92712 A

<First issue>
The driver circuit 20r is configured as an inverter having a high side transistor M2 and a low side transistor M3. In this configuration, the transition time (rise time T _R ) when the gate signal V _G rises from the low level to the high level depends on the current capability, that is, the size of the high side transistor M2, and the gate signal V _G is changed from the high level. The transition time (fall time T _F ) when falling to the low level is determined depending on the current capability of the low-side transistor M3.

The efficiency of the switching regulator 2r increases as the transition times T _R and T _F are shorter. On the other hand, the transition time _T R, the _{T F} becomes shorter, high-frequency electromagnetic noise (EMI: Electro-Magnetic Interference) becomes a problem. That is, efficiency and electromagnetic noise are in a trade-off relationship.

  Generally, electromagnetic wave noise can be measured only when the switching regulator 2r is mounted on a set. As a result of the measurement, if the EMI regulations are not satisfied, as a countermeasure against EMI, the set designer needs to make great efforts such as correcting the control circuit 100r, the inductor L1, and the peripheral printed circuit board.

In the control circuit 100r of Fig. 1, the transition time _T R, _{T F} of the gate signal _{V G} is thus determined by the ability of the transistors M2, M3. While a great deal of labor is required for EMI countermeasures, the control circuit 100r is required to have versatility to operate without any problem even if it is mounted in any set. Therefore, since the conventional control circuit 100r is designed with long transition times T _R and T _F so as not to generate electromagnetic wave noise, it is necessary to sacrifice efficiency.

  The present invention has been made in view of the above problems, and one of the exemplary purposes of an aspect thereof is to provide a switching regulator capable of optimizing the balance between efficiency and EMI for each mounted set.

<Second problem>
According to the second background art, the efficiency of the switching power supply device can be increased in a wide load region from the heavy load region to the light load region (see FIG. 11).

  However, in the switching control of the PFM method, the switching frequency fluctuates, so when the switching frequency overlaps the frequency band of an audio signal or a radio signal, a switching power supply device is installed so that an audio output or radio communication is hindered. There was a risk of damaging the performance of the selected application.

  In addition, in an application that uses a rectangular-wave-like switch voltage obtained in the process of generating a desired output voltage from an input voltage using a switching power supply device in a subsequent circuit (for example, a charge pump circuit), the switching frequency changes. As a result, the operation of the subsequent circuit may become unstable, and it has been difficult to adopt the conventional technology that performs the PFM switching control in the light load region in order to improve the efficiency.

  In view of the above-mentioned problems found by the inventors of the present application, the present invention realizes high efficiency in a wide load region from a heavy load region to a light load region without causing a change in switching frequency. An object of the present invention is to provide a switching power supply device that can be used.

  One embodiment of the present invention relates to a control circuit for a switching regulator. The control circuit includes a switching transistor, a pulse signal generation unit that generates a pulse signal whose duty ratio is adjusted so that a feedback voltage corresponding to the output voltage of the switching regulator matches a predetermined reference voltage, A driver circuit for driving the switching transistor; and a setting terminal for setting a transition time of the gate signal of the switching transistor. The driver circuit includes a high side transistor provided between the power supply terminal of the control circuit and the gate of the switching transistor, a low side transistor provided between the gate of the switching transistor and the ground terminal, and between the power supply terminal and the gate. A high-side variable current source provided in series with the high-side transistor, and at least one of a low-side variable current source provided in series with the low-side transistor between the gate and the ground terminal, and in response to an instruction to the setting terminal A slew rate control unit that controls a current value of at least one of the side variable current source and the low side variable current source. The control circuit is integrated on one semiconductor substrate.

  The current flowing through the high-side transistor or the low-side transistor is defined by the current generated by the high-side variable current source or the low-side variable current source. The rise time and fall time of the gate signal change depending on the current flowing through the high side transistor and the low side transistor, respectively. According to the control circuit of this aspect, since the transition time of the gate signal can be changed in a state where the switching regulator is mounted on the set, the maximum efficiency can be realized within a range satisfying the EMI specifications for each set.

  The slew rate control unit may include a reference current source that generates a reference current according to a circuit component connected to the setting terminal. At least one of the high-side variable current source and the low-side variable current source may be configured to generate a current proportional to the reference current.

  The slew rate control unit may include an input transistor provided on a current path according to the reference current. At least one of the high-side variable current source and the low-side variable current source may include an output transistor connected to form a current mirror circuit with the input transistor.

  An adjustment resistor may be externally attached to the setting terminal. The reference current source includes an NPN-type first bipolar transistor whose emitter is connected to a setting terminal, and a PNP-type transistor whose emitter is connected to the base of the first bipolar transistor and a predetermined reference voltage is input to the base. A current that flows through the first bipolar transistor may be output as a reference current.

  A control signal indicating the transition time of the gate signal of the switching transistor can be input to the setting terminal, and the reference current source may generate a reference current corresponding to the control signal.

  Another aspect of the present invention is a switching regulator. This switching regulator includes the above-described control circuit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  The switching power supply according to an aspect of the present invention includes a plurality of output transistors connected in parallel to each other, and a plurality of the plurality of output transistors at a predetermined frequency so as to generate a desired output voltage from an input voltage and supply the output voltage to a load. A control unit that generates an ON / OFF control signal for the output transistor, and the control unit is configured to determine an output transistor to be driven based on the weight of the load (first configuration). Yes.

  In the switching power supply device having the first configuration, the control unit increases the size of the transistor as the load is heavier, and decreases the size of the transistor as the load is lighter. It is good to make it the structure (2nd structure) which determines.

  In the switching power supply device having the first or second configuration, the plurality of output transistors may be configured to have different sizes (third configuration).

  Further, in the switching power supply device having any one of the first to third configurations, the control unit monitors a rectangular wave-like switch voltage generated by on / off controlling the output transistor to be driven, and A configuration (fourth configuration) may be adopted in which the output transistor to be driven is determined based on a comparison result between the switch voltage detected when the output transistor to be driven is turned on and a predetermined threshold voltage. .

  Further, in the switching power supply device having the fourth configuration, the control unit compares the switch voltage with a first threshold voltage to generate a first comparison signal, the switch voltage, A second comparator for generating a second comparison signal by comparing with a second threshold voltage lower than the first threshold voltage; and latching the first comparison signal when the output transistor to be driven is turned on A first latch, a second latch that latches the second comparison signal when the output transistor to be driven is turned on, the first comparison signal latched by the first latch, and the second latch And a determination unit that determines the output transistor to be driven based on the latched second comparison signal (fifth configuration).

  Further, in the switching power supply device having the fifth configuration, when the switch voltage is higher than the first threshold voltage, the determination unit is configured to increase the transistor size by one step from the current level. When the switch voltage is lower than the second threshold voltage, the transistor size is set to 1 from the current state, so that when the switch voltage is lower than the second threshold voltage, the transistor size is maintained as it is. It is preferable to adopt a configuration (sixth configuration) for determining the output transistor to be driven so as to reduce the level.

  In the switching power supply device having the sixth configuration, the control unit amplifies a difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage to generate an error signal, and the predetermined amplifier An oscillator that generates a clock signal and a slope signal at a frequency of, a comparator that generates a comparison signal by comparing the error signal and the slope signal, and an on / off function that receives the comparison signal and the clock signal. An SR flip-flop that generates a control signal, and a signal gate unit that receives the output of the determination unit and supplies the ON / OFF control signal only to the output transistor to be driven (seventh configuration) It is good to.

  In the switching power supply device having any one of the first to seventh configurations, a charge for boosting the output voltage using a rectangular wave switch voltage generated by on / off controlling the output transistor to be driven. A configuration further including a pump circuit (eighth configuration) is preferable.

  In addition, the switching power supply device having any one of the first to eighth configurations further includes a plurality of drivers that increase the current capability of the on / off control signal and supply the plurality of output transistors (a ninth configuration). Configuration).

  Further, in the switching power supply device having the ninth configuration, each of the plurality of drivers includes a plurality of unit drivers that are connected in parallel to the control terminals of the corresponding output transistors and individually controlled to be operated or not. A configuration (tenth configuration) is preferable.

  Further, in the switching power supply device having the tenth configuration, each of the plurality of unit drivers may have a configuration (eleventh configuration) formed by transistors of the same size.

  The switching power supply device having the tenth or eleventh configuration further includes an enable logic unit (a twelfth configuration) that generates an enable signal for each of the plurality of unit drivers in accordance with a slew rate adjustment signal. Good.

  In the switching power supply device having the ninth configuration, the plurality of output transistors include a main transistor externally attached to the semiconductor device and a sub-transistor built in the semiconductor device, wherein the main transistor is The on-resistance value may be smaller than that of the sub-transistor, and the sub-transistor may have a gate capacitance value smaller than that of the main transistor (a thirteenth configuration).

  In the switching power supply device having the thirteenth configuration, the control unit is configured to drive the main transistor in a heavy load region and to drive the sub-transistor in a light load region (fourteenth configuration). It is good to.

  In addition, a television according to an aspect of the present invention includes a tuner unit that selects a broadcast signal of a desired channel from a received signal, a decoder unit that generates a video signal and an audio signal from the broadcast signal selected by the tuner, Operation of each of the above-described units is comprehensively performed, a display unit that outputs the video signal as video, a speaker unit that outputs the audio signal as audio, an operation unit that receives a user operation, an interface unit that receives an external input signal, and the like. A control unit for controlling, and a power supply unit for supplying power to each of the units, the power supply unit including the switching regulator or a switching power supply device having any one of the first to fourteenth configurations. A configuration (a fifteenth configuration) is preferable.

  According to an aspect of the present invention, it is possible to optimize the balance between efficiency and EMI for each set.

  In addition, according to an aspect of the present invention, it is possible to provide a switching power supply device that can realize high efficiency in a wide load region from a heavy load region to a light load region without causing a change in switching frequency. It becomes.

It is a circuit diagram which shows the structural example of the pressure | voltage rise type switching regulator which has a power transistor. It is a circuit diagram which shows the structure of the electronic device carrying the switching regulator which concerns on embodiment. FIGS. 3A and 3B are circuit diagrams illustrating a configuration example of the driver circuit. It is a circuit diagram which shows the structure of the control circuit which concerns on a modification. The figure which shows 1st Embodiment of a switching power supply device Diagram showing an example of output transistor switching control The figure which shows the example of 1 structure of the control part 13. The figure which shows the mutual relationship of signal S1-S3 The figure which shows the relationship between switch voltage Vsw and output transistor switching control The figure which shows 2nd Embodiment of a switching power supply device The figure which shows an example of PWM / PFM switching control Diagram for explaining slew rate of output transistor The figure which shows 3rd Embodiment of a switching power supply device Diagram showing an example of adjusting the slew rate The figure which shows one structural example of the driver 12k (however, k = x, y, z) Diagram showing how through current occurs between drivers of different sizes The figure which shows 4th Embodiment of a switching power supply device The figure which shows an example of main / sub switching control Block diagram showing one configuration example of a television equipped with a switching regulator Front view of a TV with a switching regulator Side view of a TV with a switching regulator Rear view of a TV with a switching regulator

<Variable slew rate control>
The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. Further, the embodiments are examples, not limiting the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  FIG. 2 is a circuit diagram illustrating a configuration of the electronic device 1 in which the switching regulator 2 according to the embodiment is mounted.

  The electronic device 1 is a device operating on a commercial AC power source such as a display device such as a liquid crystal display or a plasma display, a DVD or a Blu-ray disc, a recorder or a player having a hard disk, or a notebook PC, digital camera, digital video camera, It is a battery-driven device such as a mobile phone terminal or PDA (Personal Digital Assistant), and includes a circuit block that requires a high power supply voltage. As such a circuit block, a liquid crystal driver, LED (Light Emitting Diode), etc. are illustrated, and it is shown as the load 3 in FIG.

The electronic device 1 includes a step-up switching regulator 2 for supplying a power supply voltage to the load 3. The input voltage _VIN is input to the input line P1 of the switching regulator 2. The switching regulator 2 boosts the input voltage _VIN and outputs the output voltage _VOUT to the output line P2.

  The switching regulator 2 is a step-up DC / DC converter, and includes a control IC 100 and an output circuit 102. The output circuit 102 includes an inductor L1, a rectifier diode D1, and an output capacitor C1. Since the topology of the output circuit 102 is general, description thereof is omitted.

  The control circuit 100 includes a switching transistor M1, a pulse signal generation unit 10, and a driver circuit 20, and is integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

A switching terminal (SW terminal) of the control circuit 100 is connected to the inductor L1. The switching transistor M1 is provided between the SW terminal and the ground terminal. The output voltage _VOUT of the switching regulator 2 is _divided by the first resistor R1 and the second resistor R2, and a feedback voltage _VFB is generated. A feedback voltage V _FB proportional to the output voltage _VOUT is input to the feedback terminal (FB terminal) of the control circuit 100.

The pulse signal generation unit 10 generates a pulse signal S _PWM whose duty ratio is adjusted such that the feedback voltage V _FB matches a predetermined reference voltage V _REF . The pulse signal generation unit 10 may be configured using a known pulse width modulator, pulse frequency modulator, or the like, and is not particularly limited.

The driver circuit 20 drives the switching transistor M1 according to the pulse signal _SPWM . Setting terminal ADJ of the control circuit 100 is provided to set the transition time of the gate signal V _G of the switching transistor M1. In the control circuit 100 of FIG. 2, both the rise time T _R and the fall time T _F of the gate signal V _G can be set from the outside.

  The driver circuit 20 includes a high-side transistor M2, a low-side transistor M3, a high-side variable current source 22, a low-side variable current source 24, and a slew rate control unit 30.

The high side transistor M2 is provided between the power supply terminal _PVDD to which the power supply voltage V _DD of the control circuit 100 is supplied and the gate of the switching transistor M1. The low side transistor M3 is provided between the gate of the switching transistor M1 and the ground terminal.

The high-side variable current source 22 is provided in series with the high-side transistor M2 between the power supply terminal _PVDD and the gate of the switching transistor M1. The low-side variable current source 24 is provided in series with the low-side transistor M3 between the gate of the switching transistor M1 and the ground terminal. The pulse signal S _PWM is input to the gates of the high-side transistor M2 and the low-side transistor M3. High-side transistor M2 and the low-side transistor M3, complementarily turned on in response to the pulse signal S _PWM, off is switched.

Slew rate control unit 30, depending on the electrical state of setting terminal ADJ, controls the level of current I _L of the high-side variable current source 22 of the current amount I _H and the low-side variable current source 24.

  FIGS. 3A and 3B are circuit diagrams illustrating a configuration example of the driver circuit 20. The slew rate control unit 30 in FIG. 3A includes a reference current source 32 and transistors M11 to M13.

The reference current source 32 generates a reference current I _REF corresponding to the state of the setting terminal ADJ. An adjustment resistor R _ADJ can be externally attached to the setting terminal ADJ. The reference current source 32 includes a first bipolar transistor Q1, a second bipolar transistor Q2, a band gap reference circuit 34, and resistors R11 and R12. The band gap reference circuit 34 generates a predetermined reference voltage V _BGR . The reference voltage V _BGR is divided by resistors R11 and R12.

The emitter of the NPN-type first bipolar transistor Q1 is connected to the setting terminal ADJ. The emitter of the PNP-type second bipolar transistor Q2 is connected to the base of the first bipolar transistor Q1. The _divided reference voltage V _BGR ′ is input to the base of the second bipolar transistor Q2. A circuit for supplying the emitter current of the second bipolar transistor Q2 and the base current of the first bipolar transistor Q1 is connected to the emitter of the second bipolar transistor Q2, but the configuration is not particularly limited and is not shown in the figure. ing.

Assuming that the base-emitter voltage Vbe of the first bipolar transistor Q1 and the second bipolar transistor Q2 is equal, the voltage of the setting terminal ADJ becomes equal to the reference voltage V _BGR ′. Therefore, the reference current I _REF given by the following formula (1) flows through the adjustment resistor R _ADJ via the first bipolar transistor Q1.
I _REF = V _BGR '/ R _ADJ (1)
The reference current source 32 outputs the current flowing through the first bipolar transistor Q1 as the reference current _IREF .

The high-side variable current source 22 generates a current _{I H} that is proportional to the reference current _{I REF.} Transistor M11 slew rate control unit 30 is arranged on a path of the reference current _{I REF} of the collector side of the first bipolar transistor Q1. The high-side variable current source 22 includes a transistor M14 that forms a current mirror circuit together with the input transistor M11. Thus, the transistor M14, the reference current _{I REF} current _{I H} that is proportional to flow.

Similarly the low-side variable current source 24 generates a current _{I L} which is proportional to the reference current _{I REF.} The transistor M12 forms a current mirror circuit together with the transistor M11, and generates a current I _REF ′ corresponding to the reference current IREF. The transistor M13 is provided on the path of the current I _REF ′. Low-side variable current source 24 includes a transistor M15 connected to form a current mirror circuit with transistor M13. Thus the transistors M15, the reference current _{I REF} 'current _{I L} which is proportional to flow (extension have reference current _{I REF} is).

FIG. 3B shows another configuration example of the reference current source 32. The reference current source 32 includes a third transistor Q3 and an operational amplifier 36. The third transistor Q3 is provided on the path of the adjustment resistor R _ADJ , and its control terminal (base) is connected to the output terminal of the operational amplifier 36. The reference voltage V _BGR ′ is input to one input terminal (non-inverting input terminal) of the operational amplifier 36, and the other input terminal (inverting input terminal) is connected to the connection point of the third transistor Q3 and the resistor R _ADJ . Is fed back. Also with this configuration, the reference current I _REF of the formula (1) is generated.

  The above is the configuration of the control circuit 100. Next, the operation will be described.

The switching transistor M1, the gate signal _{V G} is turned on when the off high level (power supply voltage _{V DD)} at a low level (ground voltage). The driver circuit 20, when switched to turn on the switching transistor M1 from off, the low-side transistor M3 turned off, the high-side transistor M2 turned on, charging the gate of the switching transistor M1, raising the gate signal V _G. Rise rate at this time (slew rate), the higher current value I _H of the high-side variable current source 22 is larger faster transition time T _R becomes shorter.

The driver circuit 20 to the contrary, when the switches turn off the switching transistor M1 from on, and the low-side transistor M3 turned on, the high-side transistor M2 off and discharges the gate of the switching transistor M1, to lower the gate signal V _G. Lowering speed at this time (slew rate) becomes faster as the current value I _L of the low-side variable current source 24 is large, the transition time T _F becomes shorter.

As described above, the current values I _H and I _L of the high-side variable current source 22 and the low-side variable current source 24 can be changed according to the electrical state of the setting terminal ADJ. Therefore, according to the control circuit 100 of FIGS. 2 and 3, the transition times T _R and T _F of the gate signal V _G can be changed.

A designer of the electronic device 1 equipped with the switching regulator 2 connects an adjustment resistor R _ADJ having a certain value to the setting terminal ADJ, and operates the switching regulator 2. If the specification of EMI is satisfied at this time, the adjustment resistor R _ADJ can be replaced with one having a smaller resistance value, and the transition times T _R and T _F of the gate signal V _G can be shortened to increase the efficiency. On the other hand, if the EMI specification is not satisfied at a certain resistance value, the EMI can be reduced by exchanging the adjustment resistor R _ADJ with a larger one and lengthening the transition times T _R and T _F of the gate signal V _G.

In this way, according to the control circuit 100, since the transition times T _R and T _F of the gate signal V _G can be changed even after the control circuit 100 is manufactured, each set has a range that satisfies the EMI specifications. Maximum efficiency can be achieved.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

FIG. 4 is a circuit diagram showing a configuration of a control circuit 100a according to a modification. The control circuit 100a includes an interface circuit 40, a memory 42, and a slew rate control unit 30a. For example, a control signal S _ADJ instructing the transition times T _R and T _F of the gate signal V _G of the switching transistor M1 can be input to the setting terminal ADJ. The interface circuit 40 writes the received control signal S _ADJ into a memory 42 such as a register or a nonvolatile memory. Slew rate control unit 30a in response to the control signal _{S ADJ,} the high-side variable current source 22, the current amount of the low-side variable current source 24 _I H, sets the _{I L.}

For example, the slew rate control unit 30a includes a reference current source 32a that generates a reference current I _REF corresponding to the control signal S _ADJ . The configuration of the reference current source 32a is not particularly limited. The configuration of the slew rate control unit 30a other than the reference current source 32a may be the same as that shown in FIG.

  Also in the modified example of FIG. 4, the same effect as that of the control circuit 100 of FIG.

A control voltage indicating the current amounts I _H and I _L may be input to the setting terminal ADJ from the outside. In this case, the slew rate control unit may generate a reference current proportional to the control voltage. Specifically, an adjustment resistor R _ADJ is built in the control circuit 100 in the slew rate control unit of FIGS. 3A and 3B, and a reference voltage V _BGR or V _BGR ′ is externally connected to the setting terminal ADJ instead. It is sufficient to input from.

In the embodiment, the rise time T _R and fall time T _F, a case has been described to control in accordance with an instruction for a common single setting terminal ADJ, may be set them independently. In the control circuit 100 of FIG. 3A, two pairs of the setting terminal ADJ and the reference current source 32 are provided, the current value I _H of the high-side variable current source 22 is set using one, and the other is used. it may be set current value I _L of the low-side variable current source 24.

In the control circuit 100a of FIG. 4, the control signal _{S ADJ,} including second data for specifying the first data and the fall time _{T F} specifies the rise time _{T R,} the reference current source 32a may be provided two . Then, a reference current corresponding to the first data is generated by the first reference current source 32a, the current value I _H of the high-side variable current source 22 is set, and the second data is converted by the second reference current source 32a. generating a reference current corresponding, it may set the current value I _L of the low-side variable current source 24.

In the embodiment, a case has been described that allows changing both the rise time T _R and fall time T _F, may be changed only one. If the only changeable rise time T _R, omit the low-side variable current source 24, or may be fixed to the current value I _L to the low-side variable current source 24 generates. On the other hand, when only the fall time _TF can be changed, the high-side variable current source 22 may be omitted or the current value I _H generated by the high-side variable current source 22 may be fixed.

  In the circuit diagram shown in the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a bipolar transistor can be appropriately replaced. Further, a configuration in which the NPN type and the PNP type, the N channel and the P channel are replaced, and the top and bottom are reversed is also effective.

  Although the step-up switching regulator has been described as an example in the embodiment, the present invention can be applied to a step-down type or a step-up / step-down type, and these are also included in the scope of the present invention.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

<Switching power supply>
[First Embodiment]
FIG. 5 is a diagram illustrating a first embodiment of the switching power supply device. In addition to the semiconductor integrated circuit device 110, the switching power supply device 101 according to the first embodiment includes a coil L1, a Schottky barrier diode D1, a capacitor C1, and resistors R1 and R2 as discrete elements connected thereto. A step-up switching regulator having

  Outside the semiconductor integrated circuit device 110, the first end of the coil L1 is connected to the application end of the input voltage Vin. The second end of the coil L1 is connected to the switch terminal T1 (application end of the switch voltage Vsw) of the semiconductor integrated circuit device 110, and is also connected to the anode of the Schottky barrier diode D1. The cathode of the Schottky barrier diode D1 is connected to the application terminal of the output voltage Vout. The capacitor C1 is connected between the application terminal of the output voltage Vout and the ground terminal. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal. A connection node between the resistor R1 and the resistor R2 is connected to the feedback terminal T1 (application terminal of the feedback voltage Vfb) of the semiconductor integrated circuit device 110. The load Z is connected between the application terminal of the output voltage Vout and the ground terminal.

  The semiconductor integrated circuit device 110 is a so-called switching power supply IC, and includes output transistors 11a to 11c, drivers 12a to 12c, and a control unit 13. In addition to the circuit block described above, a protection circuit block or the like may be appropriately incorporated in the semiconductor integrated circuit device 110.

  The output transistors 11a to 11c are all N-channel MOS (metal oxide semiconductor) field effect transistors. The drains of the output transistors 11a to 11c are all connected to the switch terminal T1. The sources of the output transistors 11a to 11c are all connected to the ground terminal. The gates of the output transistors 11a to 11c are connected to the output terminals of the drivers 12a to 12c, respectively. Thus, the output transistors 11a to 11c are connected in parallel to each other.

  The output transistors 11a to 11c are designed to have different sizes (occupied area on the semiconductor chip). More specifically, when the size of the output transistor 11a is defined as “× 1”, the size of the output transistor 11b is “× 2” and the size of the output transistor 11c is “× 4”. With such a configuration, when the output transistors 11a to 11c are viewed as one output transistor by switching which of the output transistors 11a to 11c is to be driven (on / off control target), The size can be switched in seven ways.

  If any one of the output transistors 11a to 11c is turned on and the other transistors are turned off, output transistors having a size of “× 1”, “× 2”, and “× 4” as a whole can be realized. If the output transistors 11a and 11b are turned on at the same time and the output transistor 11c is turned off, an output transistor having a size of “× 3” as a whole can be realized. If the output transistors 11a and 11c are simultaneously turned on and the output transistor 11b is turned off, an output transistor having a size of “× 5” as a whole can be realized. If the output transistors 11b and 11c are turned on at the same time and the output transistor 11a is turned off, an output transistor having a size of “× 6” as a whole can be realized. If all the output transistors 11a to 11c are turned on simultaneously, an output transistor having a size of “× 7” as a whole can be realized. However, the sizes of the output transistors 11a to 11c are not limited to the above, and may be designed to be the same size.

  The drivers 12a to 12c generate gate signals Ga to Gc in which the current capabilities of the on / off control signals Sa to Sc input from the control unit 13 are increased, and supply the gate signals Ga to Gc to the output transistors 11a to 11c, respectively.

  The control unit 13 generates on / off control signals Sa to Sc of the output transistors 11 a to 11 c at a predetermined switching frequency so as to generate a desired output voltage Vout from the input voltage Vin and supply it to the load Z. The control unit 13 has a function of determining an output transistor to be driven based on the weight of the load Z. In order to know the weight of the load Z, the controller 13 monitors the output current Iout flowing through the load Z or a current or voltage equivalent thereto (switch current Isw or switch voltage Vsw appearing at the switch terminal T1). And it is sufficient. Alternatively, the control unit 13 may be configured to receive an information signal regarding the weight of the load Z from a main controller (not shown) of an application in which the switching power supply device 101 is mounted in order to know the weight of the load Z.

  First, the basic operation (DC / DC conversion operation) of the switching power supply apparatus 101 having the above configuration will be described. In the following, for the sake of convenience, the case where only the output transistor 11a is a drive target will be described as an example. However, the reference numerals in the text are “11b”, “11c”, “ 11a and 11b "," 11a and 11c "," 11b and 11c ", or" 11a to 11c ".

  When the output transistor 11a is turned on, the switch current Isw directed to the ground terminal flows through the coil L1 via the output transistor 11a, and the electric energy is stored. Note that if the charge has already been accumulated in the capacitor C1 during the ON period of the transistor 11a, the output current Iout flows from the capacitor C1 to the load Z. At this time, since the potential of the switch terminal T1 drops to almost the ground potential via the transistor 11a, the Schottky barrier diode D1 is in a reverse bias state, and no current flows from the capacitor C1 toward the transistor 11a. On the other hand, when the transistor 11a is turned off, the electric energy accumulated therein is released by the back electromotive voltage generated in the coil L1. At this time, since the Schottky barrier diode D1 is in a forward bias state, the current flowing through the Schottky barrier diode D1 flows into the load Z as the output current Iout and also flows into the ground terminal through the capacitor C1. C1 will be charged. By repeating the above operation, the output voltage Vout obtained by boosting the input voltage Vin is supplied to the load Z.

  As described above, the semiconductor integrated circuit device 110 boosts the input voltage Vin to generate the output voltage Vout by driving the coil L1, which is an energy storage element, by on / off control of the transistors 11a to 11c. It functions as a component of the regulator.

Next, output transistor switching control of the control unit 13 will be described. In the light load region where the switch current Isw is small, the loss due to charging / discharging of the parasitic capacitance Cgs associated between the gate and source of the output transistor rather than the loss due to the on-resistance Ron of the output transistor (= Isw ² × Ron). (= F × Cgs × Vgs ² ) is more dominant (f is the switching frequency, and Vgs is the gate-source voltage of the output transistor). Therefore, it is desirable to use a small-sized output transistor having a small parasitic capacitance Cgs in the light load region. On the other hand, in the heavy load region where the switch current Isw is large, the loss due to the on-resistance Ron of the output transistor becomes more dominant. Therefore, it is desirable to use a large-sized output transistor having a small on-resistance Ron.

  In view of the above knowledge, the control unit 13 increases the size of the transistor as the load Z is heavier (the switch current Isw is larger), and decreases the size of the transistor as the load Z is lighter (the switch current Isw is smaller). The output transistor to be driven is determined.

  FIG. 6 is a diagram illustrating an example of output transistor switching control. The horizontal axis in FIG. 6 represents the switch current Isw (equivalent to the output current Iout), and the vertical axis represents the efficiency η of the switching power supply device 1. The first threshold current I1 to the sixth threshold current I6 are set to satisfy I1 <I2 <I3 <I4 <I5 <I6.

  As shown in FIG. 6, when the switch current Isw is smaller than the first threshold current I1, only the output transistor 11a is driven and an output transistor of size “× 1” is realized. When the switch current Isw is larger than the first threshold current I1 and smaller than the second threshold current I2, only the output transistor 11b is driven and an output transistor of size “× 2” is realized. When the switch current Isw is larger than the second threshold current I2 and smaller than the third threshold current I3, the output transistors 11a and 11b are driven, and an output transistor of size “× 3” is realized. When the switch current Isw is larger than the third threshold current I3 and smaller than the fourth threshold current I4, only the output transistor 11c is driven, and an output transistor of size “× 4” is realized. When the switch current Isw is larger than the fourth threshold current I4 and smaller than the fifth threshold current I5, the output transistors 11a and 11c are driven and an output transistor of size “× 5” is realized. When the switch current Isw is larger than the fifth threshold current I5 and smaller than the sixth threshold current I6, the output transistors 11b and 11c are driven, and an output transistor of size “× 6” is realized. When the switch current Isw is larger than the sixth threshold current I6, the output transistors 11a to 11c are all driven, and an output transistor of size “× 7” is realized.

  Thus, if the configuration is such that the size of the output transistor is switched according to the weight of the load Z, high efficiency is realized in a wide load region from the heavy load region to the light load region without causing fluctuations in the switching frequency. It becomes possible.

  In the above description, the switch current Isw is monitored and the output transistor switching control is described as an example. However, the control unit 13 sets the switch voltage Vsw to be monitored instead of the switch current Isw. It is also possible. Below, the structure which monitors switch voltage Vsw and performs switching control of an output transistor is demonstrated.

  FIG. 7 is a diagram illustrating a configuration example of the control unit 13 that monitors the switch voltage Vsw and performs switching control of the output transistor. The control unit 13 of this configuration example includes an error amplifier 130, an oscillator 131, a comparator 132, an RS flip-flop 133, comparators 134 and 135, D flip-flops 136 and 137, a determination unit 138, a signal Gate portion 139.

  The error amplifier 130 has a feedback voltage Vfb (divided voltage of the output voltage Vout) applied to the inverting input terminal (−) and a predetermined reference voltage Vref (target of the output voltage Vout) applied to the non-inverting input terminal (+). The error signal ERR is generated by amplifying the difference from the set value). The voltage value of the error signal ERR increases as the feedback voltage Vfb is lower than the reference voltage Vref.

  The oscillator 131 generates a rectangular wave clock signal CLK and a sawtooth (or triangular) slope signal SLP at a predetermined switching frequency f.

  The comparator 132 compares the error signal ERR applied to the inverting input terminal (−) with the slope signal SLP applied to the non-inverting input terminal (+), and compares the comparison signal PWM (pulse with a duty corresponding to the comparison result). Width modulation signal). The comparison signal PWM is at a low level when the error signal ERR is higher than the slope signal SLP, and is at a high level when it is low. Therefore, the ON duty of the comparison signal PWM (the ratio of the ON period of the output transistor to the switching period) varies according to the voltage value of the error signal ERR.

  The RS flip-flop 133 outputs an on / off control signal SW from the output terminal (Q) based on the comparison signal PWM input to the reset input terminal (R) and the clock signal CLK input to the set input terminal (S). To do. The on / off control signal SW is set to a high level at the rising edge of the clock signal CLK, and is reset to a low level at the rising edge of the comparison signal PWM.

  The comparator 134 compares the switch voltage Vsw applied to the non-inverting input terminal (+) and the first threshold voltage Vth1 applied to the inverting input terminal (−) to generate the first comparison signal S1. The first comparison signal S1 is at a high level when the switch voltage Vsw is higher than the first threshold voltage Vth1, and is at a low level when it is low.

  The comparator 135 compares the switch voltage Vsw applied to the non-inverting input terminal (+) and the second threshold voltage Vth2 (however, Vth2 <Vth1) applied to the inverting input terminal (−) to perform a second comparison. A signal S2 is generated. The second comparison signal S2 is at a high level when the switch voltage Vsw is higher than the second threshold voltage Vth2, and is at a low level when it is low.

  The D flip-flop 136 latches the first comparison signal S1 applied to the data input terminal (D) at the rising edge of the clock signal CLK (or its delay signal). That is, the D flip-flop 136 functions as a first latch that latches the first comparison signal S1 when the output transistor to be driven is turned on. That is, the first comparison signal S1 latched by the D flip-flop 136 corresponds to a comparison result between the low level (= Ron × Isw) of the switch voltage Vsw and the first threshold voltage Vth1.

  The D flip-flop 137 latches the second comparison signal S2 applied to the data input terminal (D) at the rising edge of the clock signal CLK (or its delay signal). That is, the D flip-flop 137 functions as a second latch that latches the second comparison signal S2 when the output transistor to be driven is turned on. That is, the second comparison signal S2 latched by the D flip-flop 137 corresponds to a comparison result between the low level (= Ron × Isw) of the switch voltage Vsw and the second threshold voltage Vth2.

  Based on the first comparison signal S1 latched by the D flip-flop 136 and the second comparison signal S2 latched by the D flip-flop 137, the determination unit 138 determines a switching signal S3 for determining an output transistor to be driven. And output to the signal gate unit 139.

  Specifically, when the low level of the switch voltage Vsw is higher than the first threshold voltage Vth1, that is, when both the first comparison signal S1 and the second comparison signal S2 are at the high level, the size of the transistor is set to the current state. The UP instruction switching signal S3 is generated so as to be larger by one level (see the upper stage in FIG. 8 or the timings (1) and (2) in FIG. 9). Further, when the low level of the switch voltage Vsw is lower than the first threshold voltage Vth1 and higher than the second threshold voltage Vth2, that is, the first comparison signal S1 is at a low level and the second comparison signal S2 is at a high level. In some cases, the KEEP instruction switching signal S3 is generated so as to maintain the transistor size at the current level (see the middle stage of FIG. 8 or timings (3) and (4) of FIG. 9). When the low level of the switch voltage Vsw is lower than the second threshold voltage Vth2, that is, when both the first comparison signal S1 and the second comparison signal S2 are at the low level, the transistor size is set to one level from the current level. A DOWN instruction switching signal S3 is generated so as to be small (see the lower part of FIG. 8 or the timings (5) and (6) of FIG. 9).

  The signal gate unit 139 switches the supply destination of the on / off control signal SW in accordance with the switching signal S3 input from the determination unit 138. For example, when the UP instruction switching signal S3 is input when the output transistor of size “× 3” is realized, the on / off control signal SW is realized so as to realize the output transistor of size “× 4”. The supply destination of is changed. On the other hand, when the DOWN instruction switching signal S3 is input when the output transistor of size “× 3” is realized, the on / off control signal SW is realized so as to realize the output transistor of size “× 2”. The supply destination of is changed. Further, when the KEEP instruction switching signal S3 is input when the output transistor of size “× 3” is realized, the supply destination of the on / off control signal SW is maintained without being changed.

  Even when the output signal of another size is realized and the switching signal S3 of the UP instruction, the DOWN instruction, or the KEEP instruction is input, the ON / OFF is basically based on the same concept as described above. The supply destination of the off control signal SW is determined. However, if the UP instruction switching signal S3 is input when the output transistor of size “× 7” is realized, the size cannot be further increased, and therefore the supply destination of the on / off control signal SW is Maintained without change. Similarly, when the DOWN instruction switching signal S3 is input when the output transistor of size “× 1” is realized, the size cannot be further reduced, and the supply destination of the on / off control signal SW Is maintained without change.

  When only the output transistor 11a is driven and an output transistor of size “× 1” is realized, the on / off control signal SW is output as the on / off control signal Sa, and the on / off control signal Sb. And Sc are fixed at a low level. When only the output transistor 11b is driven and an output transistor of size “× 2” is realized, the on / off control signal SW is output as the on / off control signal Sb, and the on / off control signals Sa and Sc. Is fixed at a low level. When the output transistors 11a and 11b are driven and a size “× 3” output transistor is realized, the on / off control signal SW is output as the on / off control signals Sa and Sb, and the on / off control signal is output. Sc is fixed at a low level. When only the output transistor 11c is driven and an output transistor of size “× 4” is realized, the on / off control signal SW is output as the on / off control signal Sc, and the on / off control signals Sa and Sb are output. Is fixed at a low level. When the output transistors 11a and 11c are driven and an output transistor of size “× 5” is realized, the on / off control signal SW is output as the on / off control signals Sa and Sc, and the on / off control signal is output. Sb is fixed at a low level. When the output transistors 11b and 11c are driven and an output transistor of size “× 6” is realized, the on / off control signal SW is output as the on / off control signals Sb and Sc, and the on / off control signal is output. Sa is fixed at a low level. When the output transistors 11a to 11c are all driven and a size “× 7” output transistor is realized, the on / off control signal SW is output as the on / off control signals Sa to Sc.

  As described above, the control unit 13 of this configuration example monitors the rectangular wave-like switch voltage Vsw generated by controlling the output transistor to be driven on / off, and when the output transistor to be driven is turned on. The output transistor to be driven is determined based on the comparison result between the detected switch voltage Vsw (ie, the low level of the switch voltage Vsw) and the predetermined threshold voltages Vth1 and Vth2. By adopting such a configuration, it is possible to appropriately switch the size of the output transistor according to the weight of the load Z while having a very simple circuit configuration.

[Second Embodiment]
FIG. 10 is a diagram illustrating a second embodiment of the switching power supply device. The switching power supply device 101 of the second embodiment has a configuration substantially similar to that of the first embodiment, and is characterized by further including a charge pump circuit 120. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 5, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The charge pump circuit 120 is a circuit block that generates the second output voltage Vout2 by boosting the output voltage Vout using the switch voltage Vsw, and includes capacitors 121 and 122 and diodes 123 and 124.

  A first end of the capacitor 121 is connected to an application end of the switch voltage Vsw. The second end of the capacitor 121 is connected to the cathode of the diode 123 and the anode of the diode 124. The anode of the diode 123 is connected to the application terminal for the output voltage Vout. The cathode of the diode 124 is connected to the application terminal of the second output voltage Vout2. The capacitor 122 is connected between the application terminal of the second output voltage Vout2 and the ground terminal.

  During the low level period of the switch voltage Vsw, a charging current flows from the application terminal of the output voltage Vout to the application terminal of the switch voltage Vsw via the diode 123 and the capacitor 121. At this time, the voltage across the capacitor 121 is substantially the output voltage Vout. Thereafter, when the first end of the capacitor 121 is pulled up to the vicinity of the input voltage Vin in the high level period of the switch voltage Vsw, the second end of the capacitor 121 is also pulled up to (Vout + Vin) according to the charge conservation law of the capacitor 121, The capacitor 122 is charged via the diode 124. By repeating the above operation, a second output voltage Vout2 obtained by further boosting the output voltage Vout is generated.

  With the switching power supply device 101 of the second embodiment, the switching frequency can be kept constant when the efficiency is improved in a wide load region, and thus the charge pump circuit 120 that uses the switch voltage Vsw operates stably. It becomes possible to make it.

[Third Embodiment]
Next, attention is paid to the slew rate of the output transistor as a circuit characteristic related to the efficiency of the switching power supply device. FIG. 12 is a diagram for explaining the slew rate of the output transistor. In order to increase the efficiency of the switching power supply device, it is necessary to shorten the rise time tr and fall time tf of the switch voltage Vsw by setting the slew rate of the output transistor large. However, when the slew rate of the output transistor is set to be large, the amount of electromagnetic noise (EMI [electro-magnetic interference] noise) generated increases. For this reason, it is important to adjust the slew rate of the output transistor to an optimum value in consideration of the trade-off between the efficiency of the switching power supply device and the amount of electromagnetic noise generated.

  FIG. 13 is a diagram illustrating a third embodiment of the switching power supply device. In addition to the semiconductor integrated circuit device 110, the switching power supply device 101 of the third embodiment includes a coil L1, a Schottky barrier diode D1, a capacitor C1, and resistors R1 and R2 as discrete elements connected thereto. A step-up switching regulator having Note that the connection relationship of the discrete elements is the same as that of the first embodiment and the second embodiment, and thus redundant description is omitted.

  The semiconductor integrated circuit device 110 is a so-called switching power supply IC, and includes an output transistor 11, a driver 12, a control unit 13, and an enable logic unit 14. In addition to the circuit block described above, a protection circuit block or the like may be appropriately incorporated in the semiconductor integrated circuit device 110.

  The output transistor 11 is an N-channel MOS field effect transistor. The drain of the output transistor 11 is connected to the switch terminal T1. The source of the output transistor 11 is connected to the ground terminal. The gate of the output transistor 11 is connected to the output terminal of the driver 12.

  The driver 12 generates a gate signal G in which the current capability of the on / off control signal S input from the control unit 13 is increased, and supplies this to the output transistor 11. The driver 12 includes unit drivers 12x to 12z. The unit drivers 12x to 12z are connected in parallel to the signal output terminal of the control unit 13 and the gate of the output transistor 11, respectively. The unit drivers 12x to 12z are individually controlled to be operable according to enable signals ENx to Enz input from the enable logic unit 14. The unit drivers 12x to 12z are formed by transistors of the same size. In such a configuration, by switching which of the unit drivers 12x to 12z is operated, the current capacity of the driver 12 (and hence the slew rate of the output transistor 11) is changed to three types (× 1, × 2, x3) (see FIG. 14).

  The control unit 13 generates an on / off control signal S for the output transistor 11 at a predetermined switching frequency so as to generate a desired output voltage Vout from the input voltage Vin and supply it to the load Z.

  The enable logic unit 14 generates enable signals ENx to ENz for the unit drivers 12x to 12z in accordance with a slew rate adjustment signal ADJ input from the outside of the semiconductor integrated circuit device 110. The enable signals ENx to ENz are set to a high level when the operations of the drivers 12x to 12z are permitted, and are set to a low level when the operations of the drivers 12x to 12z are prohibited.

  In the switching power supply device 101 according to the third embodiment, the current capability (drive capability) of the driver 12 can be variably controlled in accordance with the slew rate adjustment signal ADJ. It is possible to adjust the slew rate of the output transistor 11 to an optimum value in consideration of the trade-off between the efficiency of the switching power supply device 101 and the amount of electromagnetic wave noise generated without remaking the circuit device 110.

  FIG. 15 is a diagram illustrating a configuration example of the driver 12k (where k = x, y, z). The driver 12k of this configuration example includes a P-channel MOS field effect transistor K1, an N-channel MOS field effect transistor K2, an OR gate K3, an AND gate K4, and NOT gates K5 and K6.

  The source of the transistor K1 is connected to a power supply voltage application terminal. The drains of the transistors K1 and K2 are both connected to the application terminal for the gate signal G. The source of the transistor K2 is connected to the ground terminal. The gate of the transistor K1 is connected to the output terminal of the OR gate K3. The gate of the transistor K2 is connected to the output terminal of the AND gate K4. The first input terminal of the OR gate K3 and the first input terminal of the AND gate K4 are both connected to the output terminal of the NOT gate K5. The input terminal of the NOT gate K5 is connected to the application terminal of the on / off control signal S. The second input terminal of the OR gate K3 is connected to the output terminal of the NOT gate K6. The second input terminal of the AND gate K4 and the input terminal of the NOT gate K6 are both connected to the application terminal of the enable signal ENk.

  When the enable signal ENk input to the driver 12k is at a high level (logic level when operation is permitted), both the OR gate K3 and the AND gate K4 receive the ON / OFF control signal S logically inverted by the NOT gate K5. Through output is enabled. Therefore, if the on / off control signal S is at a high level, the transistor K1 is turned on and the transistor K2 is turned off, so that the gate signal G is at a high level. On the other hand, if the on / off control signal S is at a low level, the transistor K1 is turned off and the transistor K2 is turned on, so that the gate signal G is at a low level.

  On the other hand, when the enable signal ENk input to the driver 12k is at a low level (logic level when the operation is prohibited), the OR gate K3 outputs a high level regardless of the on / off control signal S, and AND The gate K4 outputs a low level. Accordingly, the transistors K1 and K2 are both turned off, so that the gate signal G is in a high impedance state.

  As described above, with the driver 12k of this configuration example, enable control can be realized with a simple circuit configuration.

  Next, the reason why the sizes of the transistors forming the unit drivers 12x to 12z are the same will be described. FIG. 16 is a diagram illustrating how a through current is generated between drivers having different sizes. The transistors M11 and M12 forming the unit driver 12m are smaller in size than the transistors N11 and N12 forming the unit driver 12n, and the on / off state is switched earlier according to the on / off control signal S. . The unit drivers 12m and 12n are both in the operation permitted state.

  For example, when the on / off control signal S is switched from the high level to the low level, the transistors M11 and M12 forming the unit driver 12m are switched from the off state to the on state and from the on state to the off state without delay, respectively. On the other hand, the transistors N11 and N12 forming the unit driver 12n are switched from the off state to the on state and from the on state to the off state, respectively, later than the transistors M11 and M12. When the ON / OFF switching timing shift causes a simultaneous ON period of the transistor M11 and the transistor N12, an excessive through current is generated in a path from the power supply voltage application terminal to the ground terminal via the transistors M11 and N12. May flow, causing destruction of the device, smoke or fire.

  On the other hand, in the switching power supply device 101 of the third embodiment, since the sizes of the transistors forming the unit drivers 12x to 12z are the same, the above ON / OFF switching timing shift does not occur. Generation of a through current can be avoided in advance.

  In the third embodiment, a configuration having one output transistor 11 and one driver 12 is given as an example. However, the first embodiment (or the second embodiment) and the third embodiment are combined. When applying, according to FIG. 5, a plurality of sets of output transistors and drivers are provided in parallel, and the plurality of drivers are individually connected in parallel to the control terminals of the corresponding output transistors. What is necessary is just to set it as the structure (namely, the structure which applied 3rd Embodiment about each of several drivers) including the several unit driver by which operation availability is controlled.

[Fourth Embodiment]
FIG. 17 is a diagram illustrating a fourth embodiment of the switching power supply device. In addition to the semiconductor integrated circuit device 210, the switching power supply device 201 of the fourth embodiment includes N-channel MOS field effect transistors Tr1 and Tr2 (hereinafter referred to as main transistors Tr1 and Tr2) as discrete elements attached to the semiconductor integrated circuit device 210. , A step-down switching regulator having a coil L2, a capacitor C2, and resistors R3 and R4.

  The semiconductor correction circuit device 210 is provided with external terminals T11 to T16 in order to establish an electrical connection with the outside. Outside the semiconductor integrated circuit device 210, the external terminal T11 is connected to the application terminal of the input voltage Vin and the drain of the main transistor Tr1. The external terminal T12 is connected to the gate of the main transistor Tr1. The external terminal T13 (application end of the switch voltage Vsw) is connected to the source of the main transistor Tr1, the drain of the main transistor Tr2, and the first end of the coil L2. The external terminal T14 is connected to the gate of the main transistor Tr2. The external terminal T15 is connected to the source of the main transistor Tr2 and the ground terminal. The second end of the coil L2 is connected to the application end of the output voltage Vout. The capacitor C2 is connected between the application terminal of the output voltage Vout and the ground terminal. The resistors R3 and R4 are connected in series between the application terminal of the output voltage Vout and the ground terminal. A connection node between the resistor R3 and the resistor R4 is connected to the external terminal T16 (application terminal of the feedback voltage Vfb) of the semiconductor integrated circuit device 210. The load Z is connected between the application terminal of the output voltage Vout and the ground terminal.

  The semiconductor integrated circuit device 210 is a so-called switching power supply IC, and includes N-channel MOS field effect transistors 211 and 212 (hereinafter referred to as sub-transistors 211 and 212), main drivers 213 and 214, sub-drivers 215 and 216, A main controller 217, a sub-controller 218, and a load detection unit 219. In addition to the circuit block described above, a protection circuit block or the like may be appropriately incorporated in the semiconductor integrated circuit device 210.

  The drain of the sub-transistor 211 is connected to the external terminal T11. The source of the sub-transistor 211 is connected to the external terminal T13. That is, the main transistor Tr1 and the subtransistor 211 are connected in parallel to each other.

  The drain of the sub-transistor 212 is connected to the external terminal T13. The source of the sub-transistor 212 is connected to the external terminal T15. That is, the main transistor Tr2 and the sub-transistor 212 are connected in parallel with each other.

  It is assumed that the main transistors Tr1 and Tr2 have smaller on-resistance values than the sub-transistors 211 and 212, and the sub-transistors 211 and 212 have smaller gate capacitance values than the main transistors Tr1 and Tr2.

  The main drivers 213 and 214 generate a main gate signal corresponding to the main control signal input from the main controller 217, and supply the main gate signal to the main transistors Tr1 and Tr2.

  The sub-drivers 215 and 216 generate a sub-gate signal corresponding to the sub-control signal input from the sub-controller 218 and supply it to the sub-transistors 211 and 212, respectively. Note that the sub-drivers 215 and 216 have a small size with a small driving capability compared to the main drivers 213 and 214.

  The main controller 217 generates a main control signal at a predetermined switching frequency so as to drive the main transistors Tr1 and Tr2 in the heavy load mode.

  The sub controller 218 generates a sub control signal at a predetermined switching frequency so as to drive the sub transistors 211 and 212 in the light load mode.

  The load detection unit 219 controls the main controller 217 and the sub controller 218 to detect the weight of the load Z and switch between the heavy load mode and the light load mode. In order to know the weight of the load Z, the load detection unit 219 monitors the output current Iout flowing through the load Z or an equivalent current or voltage (switch current Isw and switch voltage Vsw appearing at the switch terminal T1). What is necessary is just composition. Alternatively, the load detection unit 219 may be configured to receive an information signal regarding the weight of the load Z from a main controller (not shown) of an application in which the switching power supply device 201 is mounted in order to know the weight of the load Z.

  The main controller 217, the sub controller 218, and the load detection unit 219 may be formed as a single control unit as shown in FIGS.

  In the switching power supply 201 having the above configuration, when the main transistors Tr1 and Tr2 or the subtransistors 211 and 212 are turned on / off in a complementary manner (exclusive), a rectangular wave pulse voltage Vsw is generated at the external terminal T13. Is done. By smoothing the pulse voltage Vsw, the load Z is supplied with the output voltage Vout obtained by stepping down the input voltage Vin. Note that the term “complementary (exclusive)” used in this specification means that the on / off states of the main transistors Tr1 and Tr2 or the subtransistors 211 and 212 are completely reversed. In addition, it includes a case where a predetermined delay is given to the on / off transition timing of both transistors from the viewpoint of preventing a through current (when a simultaneous on prevention period of both transistors is provided).

  As described above, the semiconductor integrated circuit device 210 reduces the input voltage Vin by driving the coil L2, which is an energy storage element, by on / off control of the main transistors Tr1 and Tr2 or the subtransistors 211 and 212. It functions as one component of the step-down switching regulator that generates the output voltage Vout.

  Next, the operation mode switching control (main / sub switching control) of the load detection unit 219 will be described. As described above, it is desirable to use a small-sized output transistor with a small gate capacitance in a light load region, and conversely, a large-sized output transistor with a small on-resistance value should be used in a heavy load region. desirable.

  In view of the above knowledge, the load detection unit 219 sets the main transistors Tr1 and Tr2 as driving targets in the heavy load region, and sets the sub-transistors 211 and 212 as driving targets in the light load region.

  FIG. 18 is a diagram illustrating an example of main / sub switching control, in which the system load state and operation mode (main / sub) are depicted in order from the top.

  As shown in FIG. 18, in the heavy load region (time t1 to t2), the main transistors Tr1 and Tr2 having smaller on-resistance values than the sub-transistors 211 and 212 are driven, while the light load region (time t1) Before and after time t2, the sub-transistors 211 and 212 having a smaller gate capacity than the main transistors Tr1 and Tr2 are to be driven.

  As described above, if the output transistor is switched according to the weight of the load Z, the light load can be changed from the heavy load region without causing the change of the switching frequency as in the first embodiment (FIG. 5). It is possible to achieve high efficiency in a wide load range up to the range.

<Application to TV>
FIG. 19 is a block diagram illustrating a configuration example of a television equipped with a switching power supply device. 20A to 20C are a front view, a side view, and a rear view of a television on which a switching power supply device is mounted, respectively. The television X of this configuration example includes a tuner unit X1, a decoder unit X2, a display unit X3, a speaker unit X4, an operation unit X5, an interface unit X6, a control unit X7, and a power supply unit X8. Have.

  The tuner unit X1 selects a broadcast signal of a desired channel from a reception signal received by an antenna X0 externally connected to the television X.

  The decoder unit X2 generates a video signal and an audio signal from the broadcast signal selected by the tuner X1. The decoder unit X2 also has a function of generating a video signal and an audio signal based on an external input signal from the interface unit X6.

  The display unit X3 outputs the video signal generated by the decoder unit X2 as a video.

  The speaker unit X4 outputs the audio signal generated by the decoder unit as audio.

  The operation unit X5 is one of human interfaces that accept user operations. As the operation unit X5, a button, a switch, a remote controller, or the like can be used.

  The interface unit X6 is a front end that receives an external input signal from an external device (such as an optical disk player or a hard disk drive).

  The control unit X7 comprehensively controls the operations of the respective units X1 to X6. As the control unit X7, a CPU [central processing unit] or the like can be used.

  The power supply unit X8 supplies power to the units X1 to X7. As the power supply unit X8, the switching regulator 2 and the switching power supply devices 101 and 201 described above can be preferably used.

<Other variations>
In the above embodiment, the step-up and step-down switching power supply devices have been described as examples. However, the application target of the present invention is not limited to this, and the step-up / step-down switching power supply device is also applicable. It can be widely applied.

  Further, various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, mutual replacement of a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The switching power supply device disclosed in this specification can be used as a power supply for various applications such as LCD-TV, PDP-TV, DVD recorder, and BD recorder.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, Q1 ... 1st bipolar transistor, M1 ... Switching transistor, 2 ... Switching regulator, Q2 ... 2nd bipolar transistor, M2 ... High side transistor, 3 ... Load, M3 ... Low side transistor, 10 ... Pulse signal generation part , 20 ... driver circuit, 22 ... high-side variable current source, 24 ... low-side variable current source, 30 ... slew rate control unit, 32 ... reference current source, 100 ... control circuit.

101, 201 Switching power supply device 110, 210 Semiconductor integrated circuit device (switching power supply IC)
11, 11a, 11b, 11c Output transistor (NMOSFET)
12, 12a, 12b, 12c Driver 12x, 12y, 12z, 12k Unit driver 13 Control unit 130 Error amplifier 131 Comparator 132 Oscillator 133 RS flip-flop 134, 135 Comparator 136, 137 D flip-flop 138 Judgment unit 139 Signal gate unit 14 Enable Logic Unit 120 Charge Pump Circuit 121, 122 Capacitor 123, 124 Diode 211, 212 N-channel MOS Field Effect Transistor (Sub)
213, 214 Main driver (upper / lower)
215, 216 Sub-driver (upper / lower)
217 Main controller 218 Sub-controller 219 Load detection unit L1, L2 Coils C1, C2 Capacitors R1, R2, R3, R4 Resistance D1 Schottky barrier diode Tr1, Tr2 N-channel MOS field effect transistor (main)
Z load T1 switch terminal T2 feedback terminal T3 slew rate adjustment terminal T11 to T16 external terminals K1, M11, N11 P-channel MOS field effect transistors K2, M12, N12 N-channel MOS field effect transistors K3 OR gate K4 AND gate K5, K6 NOT gate X TV X0 antenna X1 tuner unit X2 decoder unit X3 display unit X4 speaker unit X5 operation unit X6 interface unit X7 control unit X8 power supply unit

Claims (7)

A plurality of first transistors connected in parallel to each other;
A plurality of second transistors connected in parallel to each other;
An on / off control signal for each of the plurality of first transistors and the plurality of second transistors is generated at a predetermined frequency so as to generate a desired output voltage from an input voltage and supply it to a load. A control unit;
A load detector that is built in the semiconductor device and detects the weight of the load by monitoring a switch voltage appearing at a connection node between the plurality of first transistors and the plurality of second transistors;
Have
The controller is configured to turn on / off the plurality of first transistors and the plurality of second transistors in a complementary manner based on the weight of the load detected by the load detector . Determining a transistor and a second transistor ;
Wherein the plurality of first transistor includes a first main transistor which is external to said semiconductor device, a first sub-transistor incorporated in the semiconductor device, and
The first main transistor has a smaller on-resistance than the first sub-transistor, the first sub-transistor is minor gate capacitance value than the first main transistor,
The switching power supply device , wherein the switch voltage is input to the load detector from one end of the first sub-transistor inside the semiconductor device. The plurality of second transistors include a second main transistor externally attached to the semiconductor device, and a second sub-transistor built in the semiconductor device,
2. The switching power supply according to claim 1 , wherein the second main transistor has a smaller on-resistance value than the second sub-transistor, and the second sub-transistor has a smaller gate capacitance value than the second main transistor. apparatus. 3. The switching power supply device according to claim 2 , wherein each of the first main transistor, the second main transistor, the first sub-transistor, and the second sub-transistor is an N-channel type. The controller is configured to drive the first main transistor and the second main transistor in a heavy load region, and to drive the first sub-transistor and the second main transistor in a light load region. The switching power supply device according to claim 2 or 3 . Built in the semiconductor device,
A first main driver for driving the first main transistor;
A first sub-driver for driving the first sub-transistor;
A second main driver for driving the second main transistor;
A second sub-driver for driving the second sub-transistor;
The switching power supply device according to any one of claims 2 to 4 , further comprising: A first external terminal to a fifth external terminal;
A first sub-transistor connected between the first external terminal and the third external terminal;
A second sub-transistor connected between the third external terminal and the fifth external terminal;
A first sub-driver that generates a first sub-drive signal corresponding to the first sub-control signal and supplies the first sub-drive signal to the first sub-transistor;
A second sub-driver that generates a second sub-drive signal according to a second sub-control signal and supplies the second sub-drive signal to the second sub-transistor;
A first main driver that generates a first main drive signal according to a first main control signal and supplies the first main drive signal to the external first main transistor connected in parallel with the first sub-transistor from the second external terminal;
A second main driver that generates a second main drive signal corresponding to the second main control signal and supplies the second main drive signal to the external second main transistor connected in parallel with the second sub-transistor from the fourth external terminal;
A main controller for generating the first main control signal and the second main control signal so that the first main transistor and the second main transistor are complementarily turned on / off in the heavy load mode;
A sub-controller that generates the first sub-control signal and the second sub-control signal so as to complementarily turn on / off the first sub-transistor and the second sub-transistor in the light load mode;
Monitoring the switch voltage appearing at a connection node between the first sub-transistor and the second sub-transistor to detect the weight of the load and to switch between the heavy load mode and the light load mode; A load detector that controls the sub-controller;
A semiconductor device comprising:
The semiconductor device, wherein the switch voltage is input to the load detection unit from a connection node between the first sub-transistor and the second sub-transistor inside the semiconductor device. A tuner unit that selects a broadcast signal of a desired channel from a received signal;
A decoder unit that generates a video signal and an audio signal from the broadcast signal selected by the tuner unit;
A display unit for outputting the video signal as a video;
A speaker unit for outputting the audio signal as audio;
An operation unit for accepting user operations;
An interface for receiving external input signals;
A control unit that comprehensively controls the operation of each of the above units;
A power supply unit for supplying power to each of the above-mentioned units;
Have
The power supply unit includes a switching power supply device according to any one of claims 1 to 5 or a semiconductor device according to claim 6 .

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