JP2011199972A - Control circuit for switching power supplies and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit for switching power supplies wherein dead time can be appropriately adjusted to the characteristics of a switch and an electronic apparatus.SOLUTION: The control circuit includes a first drive unit that drives a first switch; a second drive unit that drives a second switch; a regulator that supplies power to the first drive unit and the second drive unit; and a control unit that, when the output current of the regulator is increased, enlarges the period set between the on period of the first switch and the on period of the second switch.

Description

  The present application relates to a control circuit for a synchronous rectification switching power supply and an electronic apparatus.

  In an electronic device or the like, a switching power supply is used to supply power to a load, and for example, a DCDC converter that converts a DC voltage into another DC voltage is used. Conventionally, instead of a diode, there is a synchronous rectification type DCDC converter that uses a semiconductor switching element such as a MOSFET as a synchronous rectification element. With respect to the DC-DC converter of the synchronous rectification method, a technique for improving the conversion efficiency at the time of voltage conversion is known.

JP 2006-296186 A

  In a synchronous rectification type DCDC converter in which two switches connected in series are alternately turned on, a dead time is generally provided in order to prevent a through current. The dead time is a time set between the ON period of one switch and the ON period of the other switch, and is a period during which both switches are in the OFF state. However, an excessive dead time causes a through current, and an excessive dead time causes a reduction in power conversion efficiency.

  An object of the present application is to provide a switching power supply control circuit and an electronic device capable of appropriately adjusting a dead time in accordance with the characteristics of a switch.

  A control circuit for a switching power supply disclosed in the present application is a control circuit for a synchronous rectification switching power supply in which a first switch and a second switch are alternately turned on, and the first switch that drives the first switch. A drive unit; a second drive unit that drives the second switch; a regulator that supplies power to the first drive unit and the second drive unit; and when the output current of the regulator increases, the first switch A control unit that increases a period set between the ON period of the second switch and the ON period of the second switch.

  According to the control circuit and electronic device of the disclosed switching power supply, the dead time can be appropriately adjusted according to the characteristics of the switch.

It is a circuit block diagram of a 1st embodiment. It is a figure which shows the specific example 1 of a dead time adjustment circuit. It is a figure which shows the specific example of a bias regulator. It is a timing chart which shows operation | movement of 1st Embodiment. It is a circuit block diagram of a 2nd embodiment. It is a figure which shows the specific example 2 of a dead time adjustment circuit.

  FIG. 1 is a circuit block diagram of the first embodiment. In FIG. 1, in order to avoid the drawing from becoming complicated, the power supply lines of the power supply IC 1 are omitted except for the drive circuits 13 and 14, and only the signal lines are shown.

  The power supply voltage VCC is supplied as the input voltage Vin. A feedback voltage obtained by dividing the output voltage Vout by the resistors R1 and R2 is input to the comparator 2 in the power supply IC1 and compared with the reference voltage Vref. The output signal of the comparator 2 is input to the set terminal of the RS flip-flop 3. When the output voltage Vout decreases and the feedback voltage falls below the reference voltage Vref, the comparator 2 sets the RS flip-flop 3.

  The on-time generation circuit 4 receives the output voltage Vout, the input voltage Vin, and the control signal IN output from the RS flip-flop 3. The on-time generation circuit 4 is a circuit that determines the on-time of the high-side switch SW1 based on the output voltage Vout and the input voltage Vin. When the RS flip-flop 3 is set in accordance with the output signal of the comparator 2 and the control signal IN becomes H level, the on-time generating circuit 4 causes the RS flip-flop 3 to pass after the on-time based on the output voltage Vout and the input voltage Vin elapses. Is reset and the control signal IN is set to L level.

  The control signal IN is input to the AND gates 5 and 6. The AND gate 5 outputs a logical product of a signal obtained by inverting the drive signal DRVL output from the low-side drive circuit 14 by the inverter 7 and the control signal IN. The AND gate 6 outputs a logical product of the control signal IN and a signal obtained by level-converting the drive signal DRVH output from the high-side drive circuit 13 by the level shift circuit 12 and inverted by the inverter 8.

  The output of the AND gate 5 is input to the gate of the high side switch SW1 as the drive signal DRVH via the AND gate 9, the level shift circuit 12, and the high side drive circuit 13. The high side switch SW1 is, for example, an N channel MOSFET. The output of the AND gate 6 is input to the gate of the low side switch SW2 as the drive signal DRVL via the OR gate 10, the inverter 11, and the low side drive circuit 14. The low side switch SW2 is, for example, an N channel MOSFET.

  Thus, the drive signals DRVH and DRVL are generated based on signals obtained by ANDing the control signal IN and the inverted signal of the other drive signal by the AND gates 5 and 6, respectively. This prevents the switches SW1 and SW2 from being turned on simultaneously.

  The bias regulator 15 is an internal regulator that supplies power to the drive circuits 13 and 14. A voltage VB is supplied from the bias regulator 15 to the low side drive circuit 14. On the other hand, the voltage CB is supplied to the high side drive circuit 13 from the capacitor C1. The capacitor C1 is a bootstrap circuit. One end of the capacitor C1 is connected to the bias regulator 15 via the diode D1, and the other end is connected to a connection point LX between the switches SW1 and SW2 and the output coil L1.

  The function of the capacitor C1 will be described. As described above, in the DCDC converter according to this embodiment, an N-channel MOSFET is used for the high-side switch SW1 connected between the line of the input voltage Vin to which the power supply voltage VCC is applied and the connection point LX. In order to turn on the N-channel MOSFET, a gate voltage higher than that of the source is required. When the high side switch SW1 is in the on state, the source and drain are both at the power supply voltage VCC. Therefore, when the high-side switch SW1 is an N-channel MOSFET, it is necessary to create a gate voltage higher than the power supply voltage VCC.

  The capacitor C1 is connected from the bias regulator 15 via the diode D1 to the connection point LX. The forward voltage drop of the diode D1 is 0.7V. When the connection point LX becomes the ground potential by switching, the capacitor C1 is charged to a voltage of VB-0.7V via the diode D1. When the voltage at the connection point LX rises to the power supply voltage VCC by switching, the − side of the capacitor C1 becomes the power supply voltage VCC, and therefore the + side potential rises to VCC + VB−0.7V. Therefore, when the power source of the high side drive circuit 13 is supplied from the + side of the capacitor C1, the drive circuit 13 is always VB regardless of whether the low side switch SW2 is on or the high side switch SW1 is on. -0.7V voltage supply can be received. Thereby, the high-side drive circuit 13 can perform gate drive stably. The level shift circuit 12 performs level conversion between the VB level and the CB level.

  With the above configuration, in the DCDC converter of the present embodiment, the high side switch SW1 and the low side switch SW2 are alternately turned on, and a current flows through the output coil L1 via the switches SW1 and SW2. Further, the output capacitor C2 smoothes the output voltage Vout together with the output coil L1. As a result, the input voltage Vin is stepped down to generate the output voltage Vout.

  In the synchronous rectification type DCDC converter in which two switches connected in series are alternately turned on as in this embodiment, a dead time is provided to prevent a through current. Here, the time until the switch is completely turned on (or off) varies depending on the characteristics of the switch, such as the size of the FET. For example, when the total gate charge amount Qg, which is a charge amount necessary for the switch to be completely turned on, increases, the time until the switch is completely turned on becomes longer.

  When the switching frequency is fosc, the switch drive current I is approximately equal to Qg × fosc. Therefore, when the total gate charge amount Qg of the switch is large, the output of the regulator that supplies power to the drive circuit that drives the switch The current increases. Therefore, in the DCDC converter of this embodiment, the power supply IC1 includes the dead time adjustment circuit 16, and the dead time adjustment circuit 16 monitors the output current of the bias regulator 15, and increases the dead time when the output current increases. .

  FIG. 2 shows a specific example 1 of the dead time adjustment circuit 16. First, the configuration of the bias regulator 15 will be described with reference to FIG. FIG. 3 is a diagram showing a specific example of the bias regulator 15, and corresponding parts in FIGS. 2 and 3 are denoted by the same reference numerals. The operational amplifier 51 amplifies the difference between the voltage obtained by dividing the voltage VB with the resistors R10 and R11 and the reference voltage output from the band gap reference circuit 50. The gate voltage of the transistor P10 to which the power supply voltage VCC is applied to the source is controlled by the output of the operational amplifier 51. Thereby, the bias regulator 15 generates the voltage VB from the power supply voltage VCC.

  Next, returning to FIG. 2, the configuration of the dead time adjusting circuit 16 will be described. The gate voltage of the transistor P11 having the power supply voltage VCC applied to the source is controlled in the same manner as the transistor P10 in the output section of the bias regulator 15. Thereby, the transistor P11 passes a current corresponding to the output current of the bias regulator 15. The transistors N11 and N12 and the transistors P12 and P13 each constitute a current mirror circuit, and a current corresponding to the mirror ratio with respect to the current flowing through the transistor P11 is relayed to the transistor N13. When the mirror ratio is 1: 1, the current flowing through the transistor P11 is equal to the current flowing through the transistor N13. The gate voltage of the transistor N13 is controlled so that a constant current flows. Therefore, a current having a value obtained by subtracting a current corresponding to the output current of the bias regulator 15 from a constant current flowing through the transistor N13 flows through the transistor P14 connected to the transistor N13.

  Since the transistors P14 and P15 constitute a current mirror circuit, the transistor P15 charges the capacitor C11 by flowing a current having the same value as the current flowing through the transistor P14. Further, the capacitor C11 is discharged by the transistor N14 whose gate receives the inverted signal XIN of the control signal IN (see FIG. 1). A signal VBB generated based on the voltage of the capacitor C11 is input to the AND gate 9 (see FIG. 1).

  On the other hand, since the transistors P14 and P16 and the transistors N15 and N16 form a current mirror circuit, the transistor N16 discharges the capacitor C12 by flowing a current having the same value as the current flowing through the transistor P14. The capacitor C12 is charged by a transistor P17 whose gate receives an inverted signal XIN of the control signal IN (see FIG. 1). A signal VBA generated based on the voltage of the capacitor C12 is input to the OR gate 10 (see FIG. 1).

  The operation and effect of the above configuration will be described. FIG. 4 is a timing chart showing the operation of the first embodiment. When the inversion signal XIN becomes L level, the transistor N14 (see FIG. 2) is turned off, and the voltage level of the signal VBB increases as the capacitor C11 is charged. The rising slew rate of the signal VBB decreases as the output current of the bias regulator 15 increases. The drive signal DRVH is generated based on the output of the AND gate 9 (see FIG. 1) to which the signal VBB is input. Therefore, when the output current of the bias regulator 15 increases, the transition of the drive signal DRVH is delayed and the dead time tD1 increases.

  On the other hand, when the inverted signal XIN becomes H level, the transistor P17 (see FIG. 2) is turned off, and the voltage level of the signal VBA decreases as the capacitor C12 is discharged. The falling slew rate of the signal VBA decreases as the output current of the bias regulator 15 increases. The drive signal DRVL is generated based on the output of the OR gate 10 (see FIG. 1) to which the signal VBA is input. Therefore, when the output current of the bias regulator 15 increases, the transition of the drive signal DRVL is delayed, and the dead time tD2 increases.

  Thus, the dead time adjustment circuit 16 monitors the output current of the bias regulator 15, and increases the dead time when the output current increases. Accordingly, when the total gate charge amount Qg of the switches SW1 and SW2 is large (that is, the time until the switches SW1 and SW2 are completely turned on is long), the dead time can be set longer, so that the through current Can be prevented. Since the dead time is set according to the characteristics of the switches SW1 and SW2, it is possible to avoid setting an excessive dead time and to improve the power conversion efficiency of the DCDC converter. Further, by adjusting the dead time from the output current of the bias regulator 15 which is an internal regulator, there is an advantage that the output voltage Vout and the spike at the connection point LX are not affected by the spike.

  FIG. 5 is a circuit block diagram of the second embodiment. The second embodiment is different from the first embodiment in that the power supply for the drive circuits 13 and 14 is provided outside the power supply IC1. In the first embodiment, power is supplied to the drive circuits 13 and 14 from the bias regulator 15 which is an internal regulator, whereas in the second embodiment, power is supplied to the drive circuits 13 and 14 from the external power supply 17.

  In the second embodiment, the power supply IC 1 includes a sense resistor R 3 and a voltage / current conversion amplifier 18 at the input portion of the external power supply 17. The voltage-current conversion amplifier 18 converts the voltage difference between both ends of the sense resistor R3 inserted in the power supply line to the drive circuits 13 and 14 into a current. The output of the voltage / current conversion amplifier 18 is input to the dead time adjustment circuit 16.

  FIG. 6 shows a specific example 2 of the dead time adjustment circuit 16 in which the specific example 1 of the dead time adjustment circuit 16 described in FIG. 2 in the first embodiment corresponds to the second embodiment. A configuration including the transistors P30 and N30 and the resistors R30 and R31 corresponds to the voltage-current conversion amplifier 18 of FIG. The gate voltage of the transistor P30 whose source is connected to one end of the sense resistor R3 is controlled by a voltage obtained by dividing the voltage at the other end of the sense resistor R3 by the resistors R30 and R31. Thereby, the transistor P30 passes a sense current corresponding to the voltage difference between both ends of the sense resistor R3 (that is, corresponding to the output current of the external power supply 17 that supplies power to the drive circuits 13 and 14). The transistors N30 and N12 and the transistors P12 and P13 form a current mirror circuit, respectively, and a current having the same value as the sense current flowing through the transistor P30 is relayed to the transistor N13.

  Since the other points are the same as in the first embodiment, in FIG. 5 and FIG. 6, the same reference numerals are given to the parts corresponding to FIG. 1 and FIG. Even with the configuration of the second embodiment in which the power supply of the drive circuits 13 and 14 is provided outside the power supply IC 1, the dead time adjustment circuit 16 monitors the output current of the external power supply 17. The same effect as the first embodiment can be obtained.

  As described above in detail, according to the first and second embodiments, it is possible to appropriately adjust the dead time in accordance with the characteristics of the switches SW1 and SW2. In a synchronous rectification type DCDC converter, a through current can be prevented and power conversion efficiency can be improved.

  Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

  For example, the configuration of the DCDC converter is not limited to the above embodiment. A configuration in which a P-channel MOSFET is used for the high-side switch SW1 may be used. The switches SW1 and SW2 may be built in the power supply IC1. In the specific example of the dead time adjustment circuit 16 shown in FIGS. 2 and 6, the drive signal DRVL is input to the gate of the transistor N14 instead of the inverted signal XIN, and the signal VBB is reset according to the drive signal DRVL. Also good.

  Moreover, you may comprise an electronic device provided with the DCDC converter mentioned above, the battery which supplies the input voltage Vin, and the system which operates by supplying the output voltage Vout.

  The high side switch SW1 and the low side switch SW2 are examples of the first switch and the second switch, respectively. The high side drive circuit 13 and the low side drive circuit 14 are examples of a first drive unit and a second drive unit, respectively. The bias regulator 15 is an example of a regulator. The dead time adjustment circuit 16 is an example of a control unit. Capacitor C11 and capacitor C12 are examples of a first capacitor and a second capacitor, respectively. The signal VBB and the signal VBA are examples of the first signal and the second signal, respectively. The control signal IN is an example of a control signal. The RS flip-flop 3 and the on-time generation circuit 4 are examples of a switching control unit. The AND gate 5, the AND gate 6, the inverter 7, the inverter 8, the AND gate 9, the OR gate 10, and the inverter 11 are examples of a logic unit. The sense resistor R3 is an example of a sense resistor. The voltage / current conversion amplifier 18 is an example of a voltage / current conversion amplifier.

1 Power supply IC
2 Comparator 3 RS flip-flop 4 On-time generation circuit 5, 6, 9 AND gate 7, 8, 11 Inverter 10 OR gate 12 Level shift circuit 13, 14 Drive circuit 15 Bias regulator 16 Dead time adjustment circuit 17 External power supply 18 Voltage current Conversion amplifier C11, C12 Capacitor R3 Sense resistor SW1, SW2 Switch

Claims (6)

A control circuit for a synchronous rectification switching power supply that alternately turns on a first switch and a second switch,
A first drive unit for driving the first switch;
A second drive unit for driving the second switch;
A regulator for supplying power to the first drive unit and the second drive unit;
A controller that increases a period set between an ON period of the first switch and an ON period of the second switch when the output current of the regulator increases;
A control circuit comprising: The controller is
A first capacitor that is charged by a charging current that varies in size according to the output current of the regulator;
A second capacitor that is discharged by a discharge current whose magnitude changes according to the output current of the regulator;
With
The control circuit according to claim 1, wherein the period is adjusted by a first signal based on a voltage of the first capacitor and a second signal based on a voltage of the second capacitor. A comparator that compares a feedback voltage according to the output voltage of the switching power supply with a reference voltage;
A switching control unit for outputting a control signal for controlling on / off of the first switch and the second switch based on an output signal of the comparator;
A logic unit that performs a logical operation based on the control signal, the first signal, and the second signal, and generates a logic of each driving signal output from the first driving unit and the second driving unit;
The control circuit according to claim 2, further comprising: The control circuit according to claim 3, wherein the first signal and the second signal are each reset according to the logic of the control signal. A control circuit for a synchronous rectification switching power supply that alternately turns on a first switch and a second switch,
A first drive unit for driving the first switch;
A second drive unit for driving the second switch;
A sense resistor provided on a power supply line to the first drive unit and the second drive unit;
A voltage-current conversion amplifier that outputs a sense current according to a voltage difference between both ends of the sense resistor;
A controller that increases a period set between an on period of the first switch and an on period of the second switch when the sense current is increased;
A control circuit comprising: A first switch;
A second switch;
A first drive unit for driving the first switch;
A second drive unit for driving the second switch;
A regulator for supplying power to the first drive unit and the second drive unit;
A controller that increases a period set between an ON period of the first switch and an ON period of the second switch when the output current of the regulator increases;
A switching power supply including
A system to which the output voltage of the switching power supply is supplied;
An electronic device comprising:

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