JP2019213317A - Semiconductor device - Google Patents

Abstract

To prevent an increase in an output voltage even when an output feedback terminal is open.SOLUTION: A semiconductor device 100 includes: output feedback sections (120, 130, 140, 150) which drive a switch output stage 110 so that a feedback voltage Vfb corresponding to a terminal voltage of an output feedback terminal FB meets a predetermined reference voltage Vref to generate a desired output voltage Vout from an input voltage Vin; a switch voltage monitoring section 180 for forcibly stopping the switch output stage 110 through the output feedback section (especially, a control section 140) when an average value of a switch voltage Vsw generated by the switch output stage 110 is under an over-voltage state.SELECTED DRAWING: Figure 1

Description

  The invention disclosed in this specification relates to a semiconductor device.

  Conventionally, a switching power supply that generates a desired output voltage from an input voltage has been put to practical use as a power supply means for various applications.

  In addition, Patent Document 1 and Patent Document 2 can be cited as examples of related art related to the above.

JP 2007-209072 A US Patent Application Publication No. 2017/0079111

  However, in the above-described conventional switching power supply, there is a possibility that the output voltage may rise abnormally when the output feedback terminal of the semiconductor device that is the controlling body is opened.

  In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in this specification provides a semiconductor device capable of preventing an increase in output voltage even when an output feedback terminal is open. The purpose is to do.

  A semiconductor device disclosed in the present specification drives a switch output stage so that a terminal voltage of an output feedback terminal or a feedback voltage corresponding to the terminal voltage matches a predetermined reference voltage, and a desired output voltage from the input voltage. An output feedback unit that generates the switch output stage, and a switch voltage monitoring unit that forcibly stops the switch output stage via the output feedback unit when an average value of the switch voltage generated in the switch output stage is an overvoltage state, It is set as the structure (1st structure) to have.

  In the semiconductor device having the first configuration, the output feedback unit includes the switch when the terminal voltage or the feedback voltage is lower than a predetermined value and the average value of the switch voltages is in an overvoltage state. A configuration in which the output stage is forcibly stopped (second configuration) may be employed.

  The semiconductor device having the first or second configuration includes a function of shutting down the entire device when the terminal voltage or the feedback voltage is lower than the predetermined value for a predetermined period. (3rd configuration).

  In the semiconductor device having any one of the first to third configurations, the switch voltage monitoring unit averages the switch voltage to generate an average switch voltage, and the average switch voltage and overvoltage detection. It is preferable to have a configuration (fourth configuration) including a comparator that generates a comparison signal with a threshold value and outputs the comparison signal to the output feedback unit.

  In the semiconductor device having the fourth configuration, the averaging unit may be a low-pass filter including a resistor and a capacitor (fifth configuration).

  In the semiconductor device having the fifth configuration described above, the time constant of the low-pass filter is set such that the behavior of the average switch voltage matches the behavior of the output voltage (sixth configuration). It is good to.

  The semiconductor device having any one of the first to sixth configurations may further include a discharge unit (seventh configuration) that discharges the switch voltage when the switch output stage is forcibly stopped.

  In the semiconductor device having the seventh configuration, the discharge unit includes a resistor and a discharge switch connected in series between the output terminal of the switch voltage and a reference potential terminal (eighth configuration). Good.

  In the semiconductor device having any one of the first to eighth configurations, the output feedback unit generates an error voltage that generates an error voltage according to a difference between the terminal voltage or the feedback voltage and the reference voltage. And a controller (a ninth configuration) including a control unit that generates a control signal according to the error voltage, and a drive unit that drives the switch output stage according to the control signal.

  A switching power supply disclosed in the present specification includes a semiconductor device having any one of the first to ninth configurations and a part or all of the switch output stage that generates the output voltage from the input voltage. And (a tenth configuration).

  According to the invention disclosed in this specification, it is possible to provide a semiconductor device that can prevent an increase in output voltage even when an output feedback terminal is open.

Diagram showing overall configuration of switching power supply The figure which shows the example of 1 structure of a switch voltage monitoring part The figure which shows the example of 1 structure of an averaging part The figure which shows the example of 1 structure of a discharge part Flow chart showing an example of protection operation at the time of FB opening Timing chart showing an example of protection operation when the FB is open External view showing a configuration example of a vehicle

<Switching power supply (DC / DC converter)>
FIG. 1 is a diagram illustrating an overall configuration of a switching power supply. The switching power supply 1 of this configuration example is a power conversion device that converts an input voltage Vin into a desired output voltage Vout, and includes a semiconductor device 100 (so-called power supply control IC) as a control entity.

<Semiconductor device (power supply control IC)>
Next, the configuration and operation of the semiconductor device 100 will be described with reference to FIG. The semiconductor device 100 includes a switch output stage 110, a feedback voltage generation unit 120, an error voltage generation unit 130, a control unit 140, a drive unit 150, comparators 160 and 170, a switch voltage monitoring unit 180, and a discharge unit. 190 is integrated. In addition, the semiconductor device 100 includes a plurality of external terminals (only two of the output terminal SW and the output feedback terminal FB are explicitly shown in the figure) as means for establishing electrical connection with the outside of the device. .

  The switch output stage 110 is a step-down type that steps down the input voltage Vin to generate a desired output voltage Vout, and is synchronized with the output transistor 111 (PMOSFET [P channel type metal oxide semiconductor field effect transistor] in this figure). It includes a rectifying transistor 112 (NMOSFET [N channel type MOSFET] in this figure), an inductor 113, and a capacitor 114.

  The source of the output transistor 111 is connected to the application terminal for the input voltage Vin. The drain of the output transistor 111 is connected to the output terminal SW. A gate signal G <b> 1 is input to the gate of the output transistor 111. Accordingly, the output transistor 111 is turned off when the gate signal G1 is at a high level, and turned on when the gate signal G1 is at a low level.

  The source of the synchronous rectification transistor 112 is connected to the ground terminal (= the application terminal of the ground voltage GND, which corresponds to the reference potential terminal of the system). The drain of the synchronous rectification transistor 112 is connected to the output terminal SW. A gate signal G <b> 2 is input to the gate of the synchronous rectification transistor 112. Therefore, the synchronous rectification transistor 112 is turned on when the gate signal G2 is at a high level and turned off when the gate signal G2 is at a low level.

  The output transistor 111 and the synchronous rectification transistor 112 are complementarily turned on / off according to the gate signals G1 and G2. By such switching control, a rectangular wave switch voltage Vsw that is pulse-driven between the input voltage Vin and the ground voltage GND is generated at the output terminal SW. The term “complementary” is not limited to the case where the on / off states of the output transistor 111 and the synchronous rectification transistor 112 are completely reversed, but also includes a simultaneous off period (dead time) of both transistors. This includes cases where

  Note that the output transistor 111 and the synchronous rectification transistor 112 may be built in the semiconductor device 100 as shown in the figure, or may be externally attached to the semiconductor device 100. That is, a part of the switch output stage 100 may be externally attached to the semiconductor device 100, or the entire switch output stage 100 may be externally attached to the semiconductor device 100.

  Further, the output transistor 111 can be replaced with an NMOSFET. However, in that case, it is necessary to make the high level of the gate signal G1 higher than the input voltage Vin by using a bootstrap circuit, a charge pump circuit, or the like. Further, instead of the synchronous rectifying transistor 112, a rectifying diode may be used.

  Further, when a high voltage is applied to the switch output stage 110, a high voltage element such as a power MOSFET, IGBT (insulated gate bipolar transistor), or SiC transistor may be used as the output transistor 111 or the synchronous rectification transistor 112.

  The inductor 113 and the capacitor 114 are discrete components externally attached to the semiconductor device 100, and form an LC filter that rectifies and smoothes the switch voltage Vsw to generate the output voltage Vout. The first end of the inductor 113 is connected to the output terminal SW (= the application terminal of the switch voltage Vsw). The second end of the inductor 113 and the first end of the capacitor 114 are both connected to the output end of the output voltage Vout. The second end of the capacitor 114 is connected to the ground end. The output terminal of the output voltage Vout is also connected to the output feedback terminal FB.

  The feedback voltage generation unit 120 includes resistors 121 and 122 (resistance values: R121 and R122) connected in series between the output feedback terminal FB and the ground terminal, and corresponds to the output voltage Vout from a connection node between both resistors. The feedback voltage Vfb (= divided voltage of the output voltage Vout, Vfb = Vout × {R122 / (R121 + R122)}) is output. Note that the resistors 121 and 122 may be built in the semiconductor device 100 as shown in the figure, or may be externally attached to the semiconductor device 100. When the output voltage Vout is within the input dynamic range of the error voltage generator 130 and the comparators 160 and 170, the feedback voltage generator 120 may be omitted.

  The error voltage generation unit 130 includes an error amplifier 131, a resistor 132, and a capacitor 133, and generates an error voltage Verr corresponding to a difference between the feedback voltage Vfb and a predetermined reference voltage Vref.

  The error amplifier 131 is a current output type transconductance amplifier (so-called gm amplifier), and includes a feedback voltage Vfb input to the inverting input terminal (−) and a reference voltage Vref (input) input to the non-inverting input terminal (+). = Corresponding to the target set value of the output voltage Vout), an error current Ierr corresponding to the difference is generated. The error current Ierr flows in the positive direction (= direction from the error amplifier 131 toward the capacitor 133) when the feedback voltage Vfb is lower than the reference voltage Vref, and in the negative direction (=) when the feedback voltage Vfb is higher than the reference voltage Vref. In the direction from the capacitor 133 toward the error amplifier 131).

  The resistor 132 and the capacitor 133 are connected in series between the output terminal of the error amplifier 131 and the ground terminal, and receive an error current Ierr and generate an error voltage Verr. The error voltage Verr increases when the error current Ierr flows in the positive direction, and decreases when the error current Ierr flows in the negative direction. That is, the error voltage Verr is raised when Vfb <Vref, and the error voltage Verr is lowered when Vfb> Vref. Note that by appropriately setting the resistance value of the resistor 132 and the capacitance value of the capacitor 133, the phase of the error voltage signal Verr can be compensated to prevent oscillation of the output feedback loop.

  The control unit 140 generates control signals S1 and S2 according to the error voltage Verr. Specifically, the control unit 140 increases the on-duty Don of the control signals S1 and S2 (= the ratio of the on-period Ton of the output transistor 111 occupying the predetermined switching period T) as the error voltage Verr is higher. As the error voltage Verr is lower, the on-duty Don is lowered. By such PWM [pulse width modulation] control, the output voltage Vout can be adjusted to a desired target value. In addition, about the internal structure of the control part 140, since it is sufficient if a well-known technique is applied, detailed description is omitted.

  Although not explicitly shown in the figure, the control unit 140 receives the feedback input of the current detection signal corresponding to the inductor current and the load current flowing through the switch output stage 110, and performs the output feedback control of the current mode method. It is good.

  The drive unit 150 includes drivers 151 and 152, and drives the switch output stage 110) according to the control signals S1 and S2. More specifically, the driver 151 drives the output transistor 111 by generating the gate signal G1 according to the control signal S1. The driver 152 drives the synchronous rectification transistor 112 by generating the gate signal G2 according to the control signal S2.

  The feedback voltage generation unit 120, the error voltage generation unit 130, the control unit 140, and the drive unit 150 described above each have a terminal voltage of the output feedback terminal FB or a feedback voltage Vfb corresponding thereto corresponding to a predetermined reference voltage Vref. It corresponds to the component of the output feedback section that drives the switch output stage 110 so as to coincide with the input voltage Vin and generates the desired output voltage Vout from the input voltage Vin.

  The comparator 160 is a means for detecting whether or not the output feedback terminal FB is in an overvoltage state, and is input to the feedback voltage Vfb input to the non-inverting input terminal (+) and the inverting input terminal (−). The FB overvoltage detection signal Sa is generated by comparing the FB overvoltage detection threshold voltage Vovp. The FB overvoltage detection signal Sa is at a high level (= logic level when FB overvoltage is detected) when Vfb> Vovp, and is at a low level (= logic level when FB overvoltage is not detected) when Vfb <Vovp. . The control unit 140 performs an appropriate FB overvoltage protection operation according to the FB overvoltage detection signal Sa.

  The comparator 170 is a means for detecting whether or not the output feedback terminal FB is shorted to GND (ground fault). The comparator 170 receives the feedback voltage Vfb input to the inverting input terminal (−) and the non-inverting input terminal (+ The FB short detection signal Sb is generated by comparing the FB short detection threshold voltage Vscp input to the FB short circuit. The FB short detection signal Sb is at a high level (= logic level when FB short is detected) when Vfb <Vscp, and is at a low level (= logic level when FB short is not detected) when Vfb> Vscp. . The control unit 140 performs an appropriate FB short protection operation according to the FB short detection signal Sb.

  The switch voltage monitoring unit 180 is a means for detecting whether or not the output terminal SW is in an overvoltage state. The switch voltage monitoring unit 180 monitors the switch voltage Vsw generated in the switch output stage 110 and generates the SW overvoltage detection signal Sc. This is output to the control unit 140. The SW overvoltage detection signal Sc is at a high level when the average value of the switch voltage Vsw (= corresponding to a pseudo output voltage that changes with the same behavior as the output voltage Vout) is in an overvoltage state (= logic level when SW overvoltage is detected). Thus, when the average value of the switch voltage Vsw is not an overvoltage state, it becomes a low level (= a logic level when no SW overvoltage is detected). The control unit 140 performs an appropriate SW overvoltage protection operation according to the SW overvoltage detection signal Sc.

  The discharge unit 190 is connected between the output terminal SW and the ground terminal, and discharges the switch voltage Vsw according to the discharge control signal Sd input from the control unit 140.

<Switch voltage monitoring unit>
FIG. 2 is a diagram illustrating a configuration example of the switch voltage monitoring unit 180. The switch voltage monitoring unit 180 of this configuration example includes an averaging unit 181 and a comparator 182.

  The averaging unit 181 generates an average switch voltage Vave by averaging the switch voltage Vsw input from the output terminal SW.

  The comparator 182 compares the average switch voltage Vave input to the non-inverting input terminal (+) with the SW overvoltage detection threshold voltage Vth input to the inverting input terminal (−) to generate a comparison signal. It outputs as SW overvoltage detection signal Sc. The SW overvoltage detection signal Sc is at a high level (= logic level when SW overvoltage is detected) when Vave> Vth, and is at a low level (= logic level when SW overvoltage is not detected) when Vave <Vth. .

<Average section>
FIG. 3 is a diagram illustrating a configuration example of the averaging unit 181. The averaging unit 181 of this configuration example includes a resistor 181a (resistance value: R) and a capacitor 181b (capacitance value: C).

  The resistor 181a is connected between the input terminal of the switch voltage Vsw and the output terminal of the average switch voltage Vave. The capacitor 181b is connected between the output terminal of the average switch voltage Vave and the ground terminal. That is, the averaging unit 181 is configured as an RC low-pass filter including a resistor 181a and a capacitor 181b.

  Note that the time constant τ (= R × C) of the RC low-pass filter is desirably set so that the behavior of the average switch voltage Vave matches the behavior of the output voltage Vout. For example, when the capacitance value of the capacitor 114 forming the switch output stage 110 is on the order of μF, the resistance value R of the resistor 181a is set to several hundred kΩ to several MΩ, and the capacitance value C of the capacitor 181b is set to the pF order. It is good to set.

<Discharge part>
FIG. 4 is a diagram illustrating a configuration example of the discharge unit 190. The discharge unit 190 of this configuration example includes an NMOSFET 191 and a resistor 192.

  The first end of the resistor 192 is connected to the output terminal (= output terminal SW) of the switch voltage Vsw. A second end of the resistor 192 is connected to the drain of the NMOSFET 191. The source of the NMOSFET 191 is connected to the ground terminal.

  A discharge control signal Sd is input to the gate of the NMOSFET 192. Therefore, when the discharge control signal Sd is at a high level, the NMOSFET 192 is turned on, so that the discharge path of the switch voltage Vsw is conducted. On the other hand, when the discharge control signal Sd is at a low level, the NMOSFET 192 is turned off, so that the discharge path of the switch voltage Vsw is interrupted. Thus, the NMOSFET 192 functions as a discharge switch that is turned on / off in response to the discharge control signal Sd.

<Protection operation when FB is open>
FIG. 5 is a flowchart showing an example of the protection operation when the FB is open. When the flow starts, in step # 1, the semiconductor device 100 enters a normal operation state (= state in which the output voltage Vout is generated by PWM control according to the error voltage Verr).

  Next, in step # 2, if the FB open has not occurred (= NO in step # 2), the flow is returned from step # 2 to step # 1, and the normal operation state is continued. Is done.

  On the other hand, when FB open has occurred in step # 2 (= YES in step # 2), the feedback voltage Vfb decreases to the ground voltage GND (<Vscp), as in the case of the FB short. To do. Therefore, as shown in step # 3, the FB short detection signal Sb rises to a high level.

  In the subsequent step # 4, it is determined whether or not the high level period of the FB short detection signal Sb has continued for a predetermined mask period T1 (for example, 1 ms). If the determination is NO, the flow proceeds to step # 5. On the other hand, if a YES determination is made, the flow proceeds to step # 12.

  As long as the NO determination is made in step # 4, the FB short protection operation (# 12) is not performed. Therefore, the error voltage Verr increases regardless of the output voltage Vout due to the decrease of the feedback voltage Vfb accompanying the FB opening (step # 5).

  As a result, as shown in step # 6, the switch output stage 110 is in a full-on state (= a state in which the on-duty Don is swung out to the maximum value), so that the output voltage Vout increases from the target value. At this time, the average switch voltage Vave obtained by averaging the switch voltage Vsw also increases in the same manner as the output voltage Vout.

  However, when the average switch voltage Vave has not reached the threshold voltage Vth (when Step # 7 is NO), the flow is returned to Step # 2. Therefore, steps # 2 to # 7 are repeated until Vave> Vth.

  On the other hand, when the switch output stage 110 continues to be fully on and the average switch voltage Vave is higher than the threshold voltage Vth (when step # 7 is YES), as shown in step # 8, the SW overvoltage The detection signal Sc rises to a high level.

  At this time, the control unit 140 performs the SW overvoltage protection operation as shown in step # 9. Specifically, both the output transistor 111 and the synchronous rectification transistor 112 are turned off, and the switch voltage Vsw is discharged by the discharge unit 190.

  As described above, when Sc = H (that is, Vave> Vth), the control unit 140 forcibly stops the switch output stage 110 as the SW overvoltage protection operation. In particular, in this flowchart, when Sb = H (ie, Vfb <Vscp) and Sc = H (ie, Vave> Vth), the SW overvoltage protection operation of step # 9 is reached, and the switch output stage 110 is forcibly stopped. Is done.

  As a result, as shown in step # 10, the output voltage Vout starts to decrease, so that it is possible to protect the load connected to the subsequent stage of the switching power supply 1. Further, the average switch voltage Vave also decreases with the same behavior as the output voltage Vout.

  When the average switch voltage Vave becomes lower than the threshold voltage Vth (when step # 11 is YES), the flow is returned to step # 1, and the semiconductor device 100 is brought into the normal operation state described above. Will be restored. However, steps # 1 to # 11 are repeated unless the FB open is resolved.

  On the other hand, if YES is determined in step # 4, the flow proceeds to step # 12, and the FB short protection operation is performed. Note that, in the FB short protection operation in step # 12, unlike the SW overvoltage protection operation in step # 9, the entire semiconductor device 100 (except for the circuit portion necessary for self-recovery in step # 13) is shut down. That is, instead of forcibly stopping only the switch output stage 110, the entire semiconductor device 100 stops its operation.

  Thereafter, in step # 13, it is determined whether or not a predetermined cool-down period T2 (for example, 14 ms) has elapsed since the entire semiconductor device 100 was shut down. Here, when the NO determination is made, the flow is returned to step # 13, and the time measurement of the cool-down period T2 is continued. On the other hand, if the determination is YES, the flow is returned to step # 1, and the semiconductor device 100 is returned to the normal operation state. At that time, the semiconductor device 100 starts up in a startup sequence with a soft start operation, as in the first startup.

  As described above, the semiconductor device 100 shuts down the entire semiconductor device 100 when the feedback voltage Vfb is lower than the threshold voltage Vscp for detecting the FB short (Sb = H) for a predetermined mask period T1. (See steps # 3, # 4, and # 12). Therefore, even when a GND short circuit occurs in the output feedback terminal FB, it is possible to appropriately protect the semiconductor device 100 and the load connected thereto.

  FIG. 6 is a timing chart showing an example of the protection operation when the FB is open. From the top, the enable signal EN, the switch voltage Vsw, the output voltage Vout, the feedback voltage Vfb, the error voltage Verr, the average switch voltage Vsw, and the FB short are illustrated. The detection signal Sb and the SW overvoltage detection signal Sc are depicted.

  The enable signal EN is a logic signal for controlling whether or not the entire semiconductor device 100 can operate. Specifically, the semiconductor device 100 is in an operating state (= enabled state) when EN = H, and is in a non-operating state (= disabled state) when EN = L. Become.

  In the switch voltage Vsw and the output voltage Vout, the solid line indicates the behavior when the SW overvoltage protection operation is performed, and the broken line indicates the behavior when the SW overvoltage protection operation is not performed for comparison reference.

  Before the time t1, no FB open occurs, and the output voltage Vout is correctly fed back to the output feedback terminal FB. Therefore, in the semiconductor device 100, the error voltage Verr is generated so that the feedback voltage Vfb matches the reference voltage Vref, and the output voltage Vout is maintained at a desired target value. At this time, the feedback voltage Vfb is maintained at a voltage value higher than the threshold voltage Vscp for FB short detection. Accordingly, the FB short detection signal Sb is at a low level (= logic level when no FB short is detected). At this time, the average switch voltage Vave obtained by averaging the switch voltage Vsw is maintained at a voltage value lower than the SW overvoltage detection threshold voltage Vth. Therefore, the SW overvoltage detection signal Sc is also at a low level (= logic level when no SW overvoltage is detected). The operation state before time t1 corresponds to a state where steps # 1 to # 2 in FIG. 5 are repeated (# 2 = NO).

  When the FB open occurs at time t1, the feedback voltage Vfb remains below the reference voltage Vref. Therefore, the error voltage Verr rises from the equilibrium value, and the switch output stage 110 continues to be fully turned on, so that the output voltage Vout begins to rise beyond the target value. Note that when the FB is open, Vfb <Vscp, so the FB short detection signal Sb rises to a high level. As the on-duty Don in the switch output stage 110 increases (= high level period extension of the switch voltage Vsw), the average switch voltage Vave also starts to rise with the same behavior as the output voltage Vout. However, at this time, since Vave <Vth, the SW overvoltage detection signal Sc is maintained at a low level. The operation state at time t1 to t2 corresponds to a state where steps # 2 to # 7 in FIG. 5 are repeated (# 2 = YES, # 7 = NO).

  After time t1, the average switch voltage Vave continues to rise, and when Vave> Vth at time t2, the SW overvoltage detection signal Sc rises to a high level. As a result, the switch output stage 110 is forcibly stopped by the SW overvoltage protection operation, so that the output voltage Vout changes from increasing to decreasing. As the switch voltage Vsw is discharged, the average switch voltage Vave also decreases with the same behavior as the output voltage Vout. Note that the operation state from time t2 to t3 corresponds to a state where the forced stop of the switch output stage 110 is continued by steps # 7 to # 11 in FIG. 5 (# 7 = YES, # 11 = NO).

  After time t2, the average switch voltage Vave continues to decrease, and when Vave <Vth at time t3, the SW overvoltage detection signal Sc falls to a low level. As a result, the SW overvoltage protection operation is canceled, and the switching operation of the switch output stage 110 is restored. However, as long as the FB open is not canceled, the switch output stage 110 is fully turned on again, so that the average switch voltage Vave starts to rise again like the times t1 to t2, and the same SW overvoltage protection operation as before is repeated (time). (See t4).

  Although not explicitly shown in the figure, the FB short protection is performed when the high level period of the FB short detection signal Sb continues for a predetermined mask period T1 without the FB open being canceled after time t4. The entire semiconductor device 100 is shut down by the operation (step # 12 in FIG. 5).

<Application to vehicles>
FIG. 7 is an external view showing a configuration example of the vehicle X. The vehicle X of this configuration example includes various electronic devices X11 to X18 that operate by receiving supply of power supply voltage from a battery (not shown). In addition, about the mounting position of the electronic devices X11-X18 in FIG. 7, it may differ from the actual for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a braking unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is an electronic device that is incorporated into the vehicle X at the factory shipment stage as standard equipment and manufacturer's optional products such as wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, and electric seats. It is.

  The electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device that includes a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

  Note that the semiconductor device 100 (and the switching power supply 1 using the semiconductor device 100) described above can be incorporated in any of the electronic devices X11 to X18.

<Other variations>
In the above embodiment, various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above embodiment. . For example, mutual replacement of a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered restrictive, and the technical scope of the present invention is not limited to the above-described embodiment, but is claimed. It should be understood that all changes that fall within the meaning and range equivalent to the scope of the above are included.

  The invention disclosed in this specification can be applied to, for example, an in-vehicle power supply IC. However, the application object is not limited to this, and can be widely applied to semiconductor devices used for other purposes.

1 Switching power supply 100 Semiconductor device (power supply control IC)
110 Switch output stage 111 Output transistor (PMOSFET)
112 Synchronous Rectification Transistor (NMOSFET)
113 Inductor 114 Capacitor 120 Feedback Voltage Generating Unit 121, 122 Resistor 130 Error Voltage Generating Unit 131 Error Amplifier 132 Resistor 133 Capacitor 140 Control Unit 150 Drive Unit 151, 152 Driver 160 Comparator 170 Comparator 180 Switch Voltage Monitoring Unit 181 Averaging Unit 181a Resistance 181b Capacitor 182 Comparator 190 Discharge unit 191 NMOSFET
192 Resistance X Vehicle X11-X18 Electronic equipment

Claims (10)

An output feedback unit that generates a desired output voltage from the input voltage by driving the switch output stage so that the terminal voltage of the output feedback terminal or the feedback voltage corresponding thereto matches a predetermined reference voltage;
A switch voltage monitoring unit that forcibly stops the switch output stage via the output feedback unit when the average value of the switch voltage generated in the switch output stage is in an overvoltage state;
A semiconductor device comprising:   The output feedback unit forcibly stops the switch output stage when the terminal voltage or the feedback voltage is lower than a predetermined value and the average value of the switch voltages is in an overvoltage state. Item 14. The semiconductor device according to Item 1.   3. The apparatus according to claim 1, further comprising a function of shutting down the entire apparatus when the terminal voltage or the feedback voltage is lower than the predetermined value for a predetermined period. Semiconductor device. The switch voltage monitoring unit
An averaging unit that averages the switch voltages to generate an average switch voltage;
A comparator that generates a comparison signal between the average switch voltage and the overvoltage detection threshold and outputs the comparison signal to the output feedback unit;
The semiconductor device according to claim 1, wherein the semiconductor device includes:   The semiconductor device according to claim 4, wherein the averaging unit is a low-pass filter including a resistor and a capacitor.   6. The semiconductor device according to claim 5, wherein the time constant of the low-pass filter is set so that the behavior of the average switch voltage matches the behavior of the output voltage.   The semiconductor device according to claim 1, further comprising a discharge unit that discharges the switch voltage when the switch output stage is forcibly stopped.   8. The semiconductor device according to claim 7, wherein the discharge unit includes a resistor and a discharge switch connected in series between an output terminal of the switch voltage and a reference potential terminal. The output feedback unit is
An error voltage generator that generates an error voltage according to a difference between the terminal voltage or the feedback voltage and the reference voltage;
A control unit that generates a control signal according to the error voltage;
A drive unit for driving the switch output stage in response to the control signal;
The semiconductor device according to claim 1, comprising: A semiconductor device according to any one of claims 1 to 9,
A part or all of the switch output stage for generating the output voltage from the input voltage;
A switching power supply comprising:

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