JP2023115986A - Power supply circuit and vehicle - Google Patents

Abstract

To provide a power supply circuit that can suppress an increase of an output voltage when an input voltage rises steeply.SOLUTION: A power supply circuit configured so as to convert an input voltage to an output voltage comprises: a drive target element that is either a switching transistor or output transistors (1, 2) arranged between an input port (T1) configured so that the input voltage is applied to and an output port (T2) configured so that the output voltage is applied to; a driver (3) configured so as to drive the drive target element on the basis of a difference between a voltage based on the output voltage and a reference voltage; and a voltage generation unit (4) configured so as to raise a voltage to be supplied to a control terminal of the drive target element when the input voltage rises.SELECTED DRAWING: Figure 1

Description

The invention disclosed in this specification relates to a power supply circuit and a vehicle including the power supply circuit.

Linear power circuits such as LDO [low drop out] are used as power means for various devices. Patent Document 1 can be cited as an example of conventional technology related to a linear power supply circuit.

JP 2020-71681 A

When the output transistor of the linear power supply circuit is a P-channel MOSFET (metal-oxide-semiconductor field-effect transistor) or PNP transistor, when the input voltage supplied to the linear power supply circuit rises sharply, the output transistor is turned on. As a result, the output voltage of the linear power supply circuit may rise. For example, if the output voltage of the linear power supply circuit rises halfway, problems may occur in loads that utilize the output voltage of the linear power supply circuit. A switching power supply circuit may also have the same problem.

A power supply circuit disclosed in this specification is a power supply circuit configured to convert an input voltage into an output voltage, and includes a switching transistor or an input terminal configured to receive the input voltage. and an output terminal configured to be applied with the output voltage, and an element to be driven, which is either one of the output transistors provided between the A driver configured to drive an element to be driven; and a voltage generator configured to increase a voltage supplied to a control terminal of the element to be driven when the input voltage rises.

Further, the vehicle disclosed in this specification includes the power supply circuit configured as described above.

According to the invention disclosed in this specification, it is possible to suppress an increase in the output voltage of the power supply circuit when the input voltage supplied to the power supply circuit rises sharply.

FIG. 1 is a diagram showing a configuration example of a linear power supply circuit according to an embodiment. FIG. 2 is a diagram illustrating a configuration example of a voltage generator. FIG. 3 is a diagram showing voltage waveforms of respective parts when the voltage generation part is removed from the linear power supply circuit according to the embodiment. FIG. 4 is a diagram showing voltage waveforms of respective parts of the linear power supply circuit according to the embodiment. FIG. 5 is a diagram showing another configuration example of the voltage generator. FIG. 6 is an external view of the vehicle. FIG. 7 is a diagram showing a configuration example of a switching power supply circuit.

In this specification, a constant voltage means a voltage that is constant in an ideal state, and is actually a voltage that can slightly fluctuate due to changes in temperature or the like.

In this specification, the reference voltage means a voltage that is constant in an ideal state, and is actually a voltage that may slightly fluctuate due to temperature changes or the like.

In this specification, the term MOSFET means that the gate structure is a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. ” refers to a field effect transistor consisting of at least three layers. That is, the structure of the MOSFET gate is not limited to a three-layer structure of metal, oxide, and semiconductor.

FIG. 1 is a diagram showing a configuration example of a linear power supply circuit according to an embodiment. The linear power supply circuit shown in FIG. 1 includes a transistor 1, output transistors 2A and 2B, resistors R1A to R1C, a driver 3, a voltage generator 4, a regulator 5, a low voltage protection circuit 6, and a reference voltage source. It has VS1, a constant current source IS1, a terminal T1, and a terminal T2.

In the configuration example shown in FIG. 1, the transistor 1 and the output transistors 2A and 2B are P-channel MOSFETs.

The source of transistor 1 is connected to terminal T1 via resistor R1A. Each source of output transistors 2A and 2B is connected to terminal T1. The gate of transistor 1 and the gate of output transistor 2A are connected to terminal T1 via resistor R1C. Terminal T1 is configured to receive an input voltage VIN.

The drain of transistor 1 is connected to the first end of constant current source IS1. A second end of the constant current source IS1 is connected to ground potential. Also, the drain of the transistor 1 is connected to the gate of the transistor 1 and the gate of the output transistor 2A. The gate of output transistor 2B is connected to the gate of transistor 1 and the gate of output transistor 2A through resistor R1B. Each drain of output transistors 2A and 2B is connected to terminal T2. Terminal T2 is configured to receive an output voltage VOUT. An output capacitor and a load (not shown) are externally connected to the terminal T2.

Driver 3 is arranged to drive transistor 1 and output transistors 2A and 2B based on the difference between feedback voltage VFB and reference voltage VREF.

The feedback voltage VFB is a voltage based on the output voltage VOUT. The feedback voltage VFB may be a voltage having the same value as the output voltage VOUT, or may be a divided voltage of the output voltage VOUT. A feedback voltage VFB is supplied to the non-inverting input terminal of the driver 3 .

The reference voltage VREF is output from the reference voltage source VS1 and supplied to the inverting input terminal of the driver 3. FIG. The reference voltage source VS1 generates the reference voltage source VS1 from the input voltage VIN, for example.

Driver 3 outputs an error signal based on the difference between feedback voltage VFB and reference voltage VREF. The error signal is supplied to the gates of transistor 1 and output transistor 2A. Also, the error signal is supplied to the gate of the output transistor 2B through the resistor R1B.

The voltage generator 4 is configured to raise the voltage supplied to the gates of the output transistors 2A and 2B when the input voltage VIN rises. Details of the voltage generator 4 will be described later.

A regulator 5 generates a constant voltage VREG from an input voltage VIN. The constant voltage VREG is used as a drive voltage for the driver 3, for example.

The low voltage protection circuit 6 is a UVLO (under voltage lock-out) circuit. The low voltage protection circuit 6 is configured to monitor whether the input voltage VIN exceeds a predetermined value. The low voltage protection circuit 6 outputs a monitoring result signal SUVLO which is the monitoring result. In this embodiment, the monitoring result signal SUVLO becomes LOW level when the input voltage VIN does not exceed the predetermined value, and becomes HIGH level when the input voltage VIN exceeds the predetermined value.

FIG. 2 is a diagram showing a configuration example of the voltage generator 4. As shown in FIG. In the configuration example shown in FIG. 2, the voltage generator 4 includes transistors Q1 to Q3, a capacitor C1, resistors R2 to R4, and terminals T3 to T5. In the configuration example shown in FIG. 2, the transistors Q1 and Q2 are N-channel MOSFETs, and the transistor Q3 is a P-channel MOSFET.

A monitoring result signal SUVLO is supplied to the gate of the transistor Q1. The source of transistor Q1 is connected to ground potential. The drain of transistor Q1 is connected to the first end of capacitor C1, the first end of resistor R2, and the gate of transistor Q2.

A second end of capacitor C1 is connected to terminal T3. Terminal T3 is configured to receive an input voltage VIN.

The second end of resistor R2 and the source of transistor Q2 are connected to ground potential. The drain of transistor Q2 is connected to the first end of resistor R3 and the gate of transistor Q3.

A second end of resistor R3 is connected to terminal T4. Terminal T4 is configured to receive an input voltage VIN.

The source of transistor Q3 is connected to terminal T5 through resistor R4. Terminal T5 is configured to receive an input voltage VIN. Voltage VDQ3 is output from the drain of transistor Q3. Voltage VDQ3 is supplied to the gate of output transistor 2A. Also, the voltage VDQ3 is supplied to the gate of the output transistor 2B through the resistor R1B.

The function of the voltage generator 4 will be described below with reference to FIGS. 3 and 4. FIG. FIG. 3 is a diagram showing voltage waveforms of respective parts when the voltage generating part 4 is removed from the linear power supply circuit according to the embodiment. FIG. 4 is a diagram showing voltage waveforms of respective parts of the linear power supply circuit according to the embodiment. 3 and 4 are diagrams showing voltage waveforms when the linear power supply circuit according to the embodiment is in a no-load state.

Assuming that the voltage generator 4 is not provided, as shown in FIG. 3, the gate voltage VG1 of the output transistor 2A and the gate voltage VG2 of the output transistor 2B do not rise at the timing t1 when the input voltage VIN rises. The output transistors 2A and 2B are turned on. This increases the output voltage VOUT.

After the timing t1, the constant voltage VREG gradually increases, and the driver 3 gradually starts the control operation under the low voltage protection by the low voltage protection circuit 6 as the constant voltage VREG increases. The gate voltage VG1 and the gate voltage VG2 of the output transistor 2B gradually rise. The output voltage VOUT continues to rise until timing t2 at which the output transistors 2A and 2B are turned off.

After timing t2, timing t3 arrives at which the monitoring result signal SUVLO becomes HIGH level. After timing t3, the driver 3 starts the control operation in a state where the low voltage protection by the low voltage protection circuit 6 is canceled. Therefore, after timing t3, the output voltage VOUT rises to the target value VTG.

Next, the operation of the voltage generator 4 of the configuration example shown in FIG. 2 will be described with reference to FIG.

In the voltage generator 4 of the configuration example shown in FIG. 2, at the timing t1 when the input voltage VIN rises, the monitoring result signal SUVLO is at LOW level, so the transistor Q1 is turned off. Accordingly, the gate voltage VGD2 of the transistor Q2 also rises according to the rise of the input voltage VIN, turning on the transistor Q2. When the transistor Q2 is turned on, the transistor Q3 is also turned on, so the voltage VDQ3 becomes substantially the same value as the input voltage VIN. As a result, the gate voltage VG1 of the output transistor 2A and the gate voltage VG2 of the output transistor 2B rise at timing t1, and the output transistors 2A and 2B are turned off. Therefore, as shown in FIG. 4, the output voltage VOUT does not rise at timing t1.

The gate voltage VGD2 of the transistor Q2 maintains the HIGH level until the timing t3 at which the monitoring result signal SUVLO becomes HIGH level. When the monitoring result signal SUVLO becomes HIGH level, the transistor Q1 is turned on and the transistor Q2 is turned off. When transistor Q2 is turned off, the gate of transistor Q3 is pulled up by resistor R3 and transistor Q3 is also turned off.

The voltage generator 4 of the configuration example shown in FIG. 2 raises the voltage VDQ3 supplied to the gates of the output transistors 2A and 2B when the input voltage VIN rises by the operation described above. Therefore, the linear power supply circuit according to the embodiment can suppress the rise of the output voltage VOUT when the input voltage VIN sharply rises.

During the period from timing t1 to timing t3, current transiently flows through the voltage generator 4 of the configuration example shown in FIG. In other words, no current flows through the voltage generator 4 of the configuration example shown in FIG. Therefore, the linear power supply circuit according to the embodiment can achieve power saving.

Further, since the voltage generator 4 of the configuration example shown in FIG. 2 includes the transistor Q2 configured to be controlled by the input voltage VIN applied to the terminal T3, the input voltage VIN can be generated with a relatively simple circuit configuration. When it rises, voltage VDQ3 can rise.

In addition, in the voltage generator 4 of the configuration example shown in FIG. 2, the capacitor C1 is provided between the terminal T1 and the gate of the transistor Q2, so that the input voltage VIN is stable and the linear power supply circuit according to the embodiment It is possible to prevent wasteful current from flowing when the is performing a steady operation.

Further, since the voltage generator 4 of the configuration example shown in FIG. 2 operates according to the monitoring result signal SUVLO, the operation can be terminated at an appropriate timing.

FIG. 5 is a diagram showing another configuration example of the voltage generator 4. As shown in FIG. The voltage generator 4 of the structural example shown in FIG. 5 has a diode D1, a transistor Q4, a resistor R5, a Zener diode D2, and a terminal T6 added to the voltage generator 4 of the structural example shown in FIG. is applied with a constant voltage VREG instead of the input voltage VIN. In the configuration example shown in FIG. 5, the transistor Q4 is an N-channel MOSFET.

The cathode of diode D1 and the gate of transistor Q4 are connected to terminal T3, and the anode of diode D1 and the source of transistor Q4 are connected to the drain of transistor Q2. The drain of transistor Q4 is connected to the gate of transistor Q3 through resistor R5.

A clamp circuit formed by diode D1, transistor Q4 and resistor R5 clamps the voltage applied to terminal T3. That is, even when an abnormality occurs in the constant voltage VREG, it is possible to prevent the voltage applied to the terminal T3 from becoming excessive.

When the constant voltage VREG is in a steady state, that is, when the value of the constant voltage VREG is as designed, the constant voltage VREG is lower than the input voltage VIN. Therefore, even if the input voltage VIN is a high voltage, the transistor Q1 and the like can be made low voltage elements.

Terminal T6 is configured to receive an input voltage VIN. The cathode of Zener diode D2 is connected to terminal T6, and the anode of Zener diode D2 is connected to the gate of transistor Q3. Zener diode D2 is useful when the input voltage VIN is higher than the gate-to-source withstand voltage of transistor Q3. Zener diode D2 is a clamp element for preventing the voltage between the gate and source of transistor Q3 from exceeding the breakdown voltage between the gate and source of transistor Q3.

The voltage generator 4 of the configuration example shown in FIG. 5 raises the voltage VDQ3 when the input voltage VIN rises when the voltage VGQ2 becomes equal to or higher than the threshold voltage of the transistor Q2. That is, in the voltage generator 4 of the configuration example shown in FIG. 5, the constant voltage VREG rises substantially in synchronization with the input voltage VIN. Therefore, the voltage waveforms of the respective parts of the voltage generator 4 in the configuration example shown in FIG. 5 are substantially the same as the voltage waveforms shown in FIG. 4 except for the constant voltage VREG. The waveform of the constant voltage VREG of the voltage generator 4 in the configuration example shown in FIG. 5 is substantially the same as the waveform of the input voltage VIN. It has been confirmed by actual measurement that the rise of the output voltage VOUT can be suppressed if the slew rate of the constant voltage VREG is approximately 29 V/μsec or less.

6 is an external view of the vehicle X. FIG. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving voltage supplied from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

Note that the linear power supply circuit described above can be incorporated in any of the electronic devices X11 to X18.

The above embodiments are illustrative in all respects and should be considered non-limiting, and the technical scope of the invention disclosed herein is not a description of the above embodiments, It should be understood that all modifications within the meaning and scope of equivalents of the claims are included.

A bipolar transistor may be used instead of the MOSFET used in the above embodiments. Further, although the linear power supply circuit has two output transistors in the above embodiment, the number of output transistors may be one or three or more.

The invention disclosed in this specification can also be applied to a switching power supply circuit. A switching power supply circuit shown in FIG. 7 is an example in which the invention disclosed in this specification is applied to a switching power supply circuit. The switching power supply circuit shown in FIG. 7 replaces the transistor 1, output transistors 2A and 2B, resistors R1A to R1C, and constant current source IS1 of the linear power supply circuit shown in FIG. C2 is replaced, and the driver 3 is replaced with a driver 3'. The driver 3' is arranged to turn on/off the switching transistor 7 based on the difference between the feedback voltage VFB and the reference voltage VREF. The cathode of diode D3 is connected to the drain of switching transistor 7 and the first end of inductor L1. The second end of inductor L1 is connected to the first end of output capacitor C2 and terminal T2. The anode of diode D3 and the second end of output capacitor C2 are connected to ground potential. The switching power supply circuit shown in FIG. 7 converts an input voltage VIN into a pulse voltage (also called switch voltage) generated by switching of the switching transistor 7, and converts the pulse voltage into an output voltage VOUT. That is, the switching transistor 7 is configured to generate the pulse voltage by switching in a power supply circuit configured to convert the input voltage VIN into a pulse voltage and convert the pulse voltage into the output voltage VOUT. In the switching power supply circuit shown in FIG. 7, the pulse voltage is the voltage generated at the connection node between the switching transistor 7 and the diode D3.

The power supply circuit described above is a power supply circuit configured to convert an input voltage into an output voltage, and includes a switching transistor or an input terminal (T1) configured to receive the input voltage and the an element to be driven, which is either one of output transistors (1, 2) provided between an output terminal (T2) configured to be applied with an output voltage, a voltage based on the output voltage, and a reference voltage; a driver (3) configured to drive the element to be driven based on the difference between the two, and configured to raise the voltage supplied to the control terminal of the element to be driven when the input voltage rises and a voltage generator (4) (first configuration).

The power supply circuit having the first configuration can suppress an increase in the output voltage when the input voltage rises steeply.

In the power supply circuit having the first configuration, even in a configuration (second configuration) in which a current transiently flows in the voltage generator during a period from when the input voltage rises to when a predetermined time elapses. good.

The power supply circuit having the second configuration can achieve power saving.

In the power supply circuit having the first or second configuration, the voltage generation unit includes a voltage application terminal (T3) configured to receive the input voltage or a constant voltage generated from the input voltage; and a transistor (Q2) configured to be controlled by the voltage applied to the voltage application terminal (third configuration).

In the power supply circuit having the third configuration, the voltage supplied to the control terminal of the output transistor can be raised when the input voltage rises with a relatively simple circuit configuration.

In the power supply circuit having the third configuration, the constant voltage is applied to the voltage application end, and the constant voltage is lower than the input voltage when the constant voltage is in a steady state. It may be a configuration (fourth configuration).

In the power supply circuit having the fourth configuration, even when the input voltage is high, some elements of the voltage generator can be low withstand voltage elements.

In the power supply circuit having the fourth configuration, the voltage generator includes a clamp circuit (D1, Q4, R5) configured to clamp the voltage applied to the voltage application terminal (fifth configuration). configuration).

The power supply circuit having the fifth configuration can prevent the voltage applied to the voltage application terminal from becoming excessive even when an abnormality occurs in the constant voltage.

In the power supply circuit having any one of the third to fifth configurations, the voltage generator includes a capacitor (C1) provided between the voltage application terminal and the control terminal of the transistor (sixth configuration ).

The power supply circuit having the sixth configuration can prevent unnecessary current from flowing when the input voltage is stable and the power supply circuit is performing a steady operation.

In the power supply circuit having any one of the first to sixth configurations, according to the monitoring result of a low voltage protection circuit (6) configured to monitor whether the input voltage exceeds a predetermined value, the A configuration (seventh configuration) in which the voltage generator operates may be employed.

The power supply circuit having the seventh configuration can terminate its operation at an appropriate timing.

The vehicle described above has a configuration (eighth configuration) including the power supply circuit having any one of the first to seventh configurations.

In the vehicle having the eighth configuration, it is possible to suppress an increase in the output voltage of the power supply circuit when the input voltage supplied to the power supply circuit rises steeply.

1, Q1 to Q4 transistors 2A, 2B output transistor 1' switching transistor 3, 3' driver 4 voltage generator 5 regulator 6 low voltage protection circuit 7 switching transistor C1 capacitor C2 output capacitor D1, D3 diode D2 zener diode IS1 constant current source L1 Inductor R1A~R1C, R2~R4 Resistor T1~T6 Terminal VS1 Reference voltage source X Vehicle X11~X18 Electronic equipment

Claims (8)

A power supply circuit configured to convert an input voltage to an output voltage,
A driving target that is either a switching transistor or an output transistor provided between an input terminal configured to receive the input voltage and an output terminal configured to receive the output voltage an element;
a driver configured to drive the driven element based on a difference between a voltage based on the output voltage and a reference voltage;
a voltage generator configured to raise the voltage supplied to the control terminal of the driven element when the input voltage rises;
A power circuit. 2. The power supply circuit according to claim 1, wherein a current transiently flows through said voltage generator during a period from when said input voltage rises to when a predetermined time elapses. The voltage generator is
a voltage application end configured to receive the input voltage or a constant voltage generated from the input voltage;
a transistor configured to be controlled by a voltage applied to the voltage application terminal;
3. The power supply circuit according to claim 1, comprising: 4. The power supply circuit according to claim 3, wherein said voltage applying end is configured to apply said constant voltage, and said constant voltage is lower than said input voltage when said constant voltage is in a steady state. The voltage generator is
5. The power supply circuit according to claim 4, comprising a clamp circuit configured to clamp the voltage applied to said voltage application end. The voltage generator is
6. The power supply circuit according to claim 3, further comprising a capacitor provided between said voltage application terminal and a control terminal of said transistor. 7. The voltage generation unit according to any one of claims 1 to 6, wherein the voltage generator operates according to a monitoring result of a low voltage protection circuit configured to monitor whether the input voltage exceeds a predetermined value. power supply circuit. A vehicle comprising the power supply circuit according to any one of claims 1 to 7.

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