JP2017121164A - Switching regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching regulator capable of executing a malfunction protection operation without directly using a detection result of a detection element for detecting a physical quantity which is an object of malfunction protection.SOLUTION: A switching regulator control circuit includes: a malfunction detection part such as a continuous pulse detection circuit 15; a malfunction protection part (a shutdown circuit 16). The malfunction detection part detects a malfunction state under which a duty ratio of a switching signal is out of a normal modulation range on the basis of the duty ratio. The malfunction protection part, when the malfunction state is detected by the malfunction detection part, stops a switching operation of a switching element.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a switching regulator.

  Switching power supply (switching regulator) control methods that stabilize the output voltage by changing the duty ratio of the switching signal according to disturbances such as input voltage fluctuation and output current fluctuation are roughly divided into voltage mode control and current mode control. it can. In general, the current mode control is an extremely effective control method in terms of simplifying phase compensation, high-speed response, and reducing the number of external parts. A conventional example of a current mode control type switching power supply is shown in FIG.

JP 2014-003850 A

A switching power supply apparatus 100 shown in FIG. 11 performs current mode control by detecting a current flowing through a lower metal oxide semiconductor (MOS) transistor Q2. According to the current mode control, the upper MOS transistor Q1 and the lower MOS transistor Q2 are turned on / off in a complementary manner, and the input voltage _VIN is converted to a pulsed switch voltage _VSW by this switching operation. Then, the switch voltage V _SW is smoothed by the inductor L1 and the output capacitor C1, and converted to an output voltage _VOUT that is lower than the input voltage _VIN .

For example, an in-vehicle switching power supply device is required to perform a high-speed switching operation of 2 MHz or more in order to avoid noise in the AM radio frequency band. In the switching power supply apparatus 100 shown in FIG. 11, for example, when the input voltage _{VIN is set} to 48 [V], the output voltage _{VOUT is set} to 3.3 [V], and the switching frequency f is set to 2 [MHz], The pulse width W of the voltage _VSW is 34 [ns] as follows.

  In the switching power supply device 100 shown in FIG. 11, the overcurrent protection operation is performed based on the overcurrent detection signal OC generated when the overcurrent flowing through the upper MOS transistor Q1 is detected. However, in the case of the above setting, since there is only 34 [ns] in which the upper MOS transistor Q1 is in the on state, it is impossible to detect the overcurrent flowing through the upper MOS transistor Q1.

  Note that the current mode control type switching power supply device disclosed in Patent Document 1 also detects an overcurrent flowing through the upper switching element and executes an overcurrent protection operation, similarly to the switching power supply device 100 shown in FIG. Have similar problems.

In order to solve the above problem, the configuration may be changed so that the overcurrent protection operation is performed based on the overcurrent flowing through the lower MOS transistor Q2. In the state where the overcurrent is detected, the output voltage _VOUT of the switching power supply device 100 is lowered. _Therefore , if there is no restriction on the pulse width W of the switch voltage _VSW , the upper side is returned at the recovery timing from the overcurrent. When the MOS transistor Q1 is turned on, the on time of the upper MOS transistor Q1 extends without limit. For this reason, when the output voltage V _OUT is decreasing, a configuration for limiting the pulse width W of the switch voltage V _SW is also added. Here, in the overcurrent state, the load is short-circuited and an overcurrent is generated, and the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 of the switching power supply device 100 is short-circuited to generate an overcurrent. There is a state that is. In the state where the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 of the switching power supply device 100 is short-circuited and an overcurrent is generated, no overcurrent flows through the lower MOS transistor Q2. For this reason, only with the configuration in which the overcurrent protection operation is performed based on the overcurrent flowing through the lower MOS transistor Q2, the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 of the switching power supply device 100 is short-circuited. It is not possible to detect the state where the error occurs. That is, in a state where the load is short-circuited and an overcurrent is generated, the pulse width W of the switch voltage _VSW is limited and an overcurrent flowing through the lower MOS transistor Q2 is detected. In the state where the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 is short-circuited and an overcurrent is generated, the pulse current W of the switch voltage _VSW is limited and the overcurrent flows through the lower MOS transistor Q2. Is not detected. In order to perform the overcurrent protection operation in a state where the pulse width W of the switch voltage V _SW is limited and the overcurrent flowing through the lower MOS transistor Q2 is not detected, the overcurrent protection is performed without directly using the detection result of the current detection element. There is a need for a technique that can perform the operation. Not only the above-described overcurrent, but also a technique that can perform an abnormality protection operation without directly using a detection result of a detection element that detects a physical quantity that is an object of abnormality protection is very useful.

  In view of the above situation, an object of the present invention is to provide a switching regulator that can perform an abnormality protection operation without directly using a detection result of a detection element that detects a physical quantity that is a target of abnormality protection.

  A switching regulator control circuit disclosed in the present specification is used in a switching regulator that converts an input voltage into an output voltage by switching of a switching element, and a switching signal for controlling the on / off operation of the switching element. A switching regulator control circuit to generate, wherein the duty ratio is normal based on a duty ratio of the switching signal or a variable correlated with the duty ratio of the control signal used to generate the switching signal An abnormal state detection unit that detects an abnormal state that is outside the modulation range; and an abnormality protection unit that stops switching of the switching element when the abnormal state is detected by the abnormal state detection unit (first 1 configuration).

  In the switching regulator control circuit of the first configuration, the modulation range in which the duty ratio is normal is the modulation of the duty ratio that appears as a response to a disturbance that can be assumed during the operation of the switching regulator having the switching regulator control circuit. A configuration indicating the range (second configuration) may be used. Note that disturbances that can be assumed during operation of the switching regulator having the switching regulator control circuit include, for example, input voltage fluctuation, load current fluctuation, and the like.

  In the switching regulator control circuit having the first or second configuration, the abnormality protection unit detects a pulse width of the switching signal, a voltage correlated with the pulse width, or a current correlated with the pulse width. Further, a configuration (third configuration) for detecting the abnormal state based on the detection result may be employed.

  Further, in the switching regulator control circuit having any one of the first to third configurations, the upper limit of the pulse width is limited to a fixed width, and the abnormality detection unit operates the pulse of the fixed width normally in the switching signal. The configuration may be such that the abnormal state is detected (fourth configuration) when the switching period of the time occurs n times (where n is a natural number equal to or less than m) within m cycles.

  In the switching regulator control circuit of the fourth configuration, a plurality of fixed width values may be set, and a configuration (fifth configuration) that can be arbitrarily selected from a plurality of settings may be used.

  In the switching regulator control circuit of the fourth or fifth configuration, the fixed width value is a function of at least one of an input voltage and an output voltage of the switching regulator having the switching regulator control circuit (sixth Configuration).

  A current mode control type switching power supply device disclosed in the present specification includes a first switch having a first end connected to a first application end to which an input voltage is applied, and a first end of the first switch. A second switch connected to the second end and connected to a second application end to which a voltage lower than the input voltage is applied to the second end; a current detection unit for detecting a current flowing through the second switch; An overcurrent detection unit that detects an overcurrent flowing through the second switch; and a control unit that controls the first switch and the second switch in accordance with a current detected by the current detection unit. The unit accumulates information on the current detected by the current detection unit during a predetermined period while the first switch is in an off state, and generates a slope voltage based on the accumulated current information Have a part The first switch and the second switch are controlled according to the slope voltage, and the first switch and the second switch are turned on while the first switch and the second switch are controlled according to the slope voltage. / When the pulse width of the pulse generated in the switching signal for controlling the off-operation exceeds a fixed width, the pulse width of the pulse generated in the switching signal is limited to the fixed width, and the overcurrent detection unit During the period in which the overcurrent is detected, the switching signal is not generated with a pulse, and the first pulse is generated when the fixed-width pulse is continuously generated in the switching signal at the switching frequency during normal operation. A configuration (seventh configuration) may be employed in which the on / off operation of the switch is stopped and the first switch is turned off.

  In the current mode control type switching power supply device having the seventh configuration, the control unit generates an error signal according to a difference between a voltage corresponding to the output voltage of the current mode control type switching power supply device and a reference voltage. An error amplifier, a comparator that compares the slope voltage with the error signal and generates a reset signal that is a comparison signal, an oscillator that generates a set signal that is a clock signal of a predetermined frequency, and the set signal and the reset signal Accordingly, a configuration (eighth configuration) may be included that includes a timing control circuit that controls on / off of the first switch and on / off of the second switch.

  In the current mode control type switching power supply of the seventh or eighth configuration, the fixed width value is a function of the input voltage and the output voltage of the current mode control type switching power supply (the ninth (Configuration).

  Further, in the current mode control type switching power supply device having any one of the seventh to ninth configurations, the second switch is a MOS transistor, and the current detection unit uses the voltage across the on-resistance of the MOS transistor. The current flowing through the second switch may be detected, and the overcurrent detection unit may detect the overcurrent flowing through the second switch using the voltage across the ON resistance of the MOS transistor (tenth configuration). .

  In addition, the in-vehicle device disclosed in the present specification includes a switching regulator control circuit having any one of the first to sixth configurations, and switching that is on / off controlled by a switching signal output from the switching regulator control circuit. A switching regulator including an element or a current mode control type switching power supply having any one of the seventh to tenth configurations (eleventh configuration).

  The vehicle disclosed in the present specification has a configuration (a twelfth configuration) including an on-vehicle device having an eleventh configuration and a battery for supplying power to the on-vehicle device.

  According to the switching regulator disclosed in the present specification, the abnormality protection operation can be performed without directly using the detection result of the detection element that detects the physical quantity that is the target of abnormality protection.

The figure which shows the example of whole structure of a switching power supply device The figure which shows one structural example of a current detection circuit and a slope circuit The figure which shows the example of 1 structure of the voltage-current conversion circuit 4A The figure which shows one structural example of 5 A of voltage-current conversion circuits The figure which shows the other structural example of a current detection circuit and a slope circuit The figure which shows the example of a principal part structure of a timing control circuit FIG. 5 is a timing chart showing an operation example of the timing control circuit shown in FIG. 5 is a timing chart showing another operation example of the timing control circuit shown in FIG. The figure which shows the other principal part structural example of a timing control circuit Timing chart showing an operation example of the timing control circuit shown in FIG. External view showing an example of the configuration of a vehicle equipped with in-vehicle equipment The figure which shows the prior art example of a current mode control type switching power supply device Diagram showing maximum pulse width of switching signal 3D plot of the maximum pulse width of the switching signal shown in FIG. Three-dimensional plot of the maximum pulse width of the switching signal considering circuit variations The figure which shows the other whole structural example of a switching power supply device The figure which shows the modification of the switching power supply device shown in FIG. The figure which shows the other modification of the switching power supply device shown in FIG.

<Overall configuration>
FIG. 1 is a diagram illustrating an overall configuration example of a current mode control type switching power supply device (current mode control type switching regulator). The switching power supply device 101 of this configuration example is a current mode control type switching power supply device that performs a step-down operation for stepping down an input voltage, and includes a timing control circuit 1, an upper MOS transistor Q1, a lower MOS transistor Q2, and an inductor. L1, output capacitor C1, voltage dividing resistors R1 and R2, error amplifier 2, reference voltage source 3, current detection circuit 4, slope circuit 5, comparator 6, oscillator 7, and overcurrent detection circuit 8.

  The timing control circuit 1 controls on / off of the upper MOS transistor Q1 and on / off of the lower MOS transistor Q2, and the gate signal G1 and lower MOS of the upper MOS transistor Q1 according to the set signal SET and the reset signal RESET. A gate signal G2 of the transistor Q2 is generated.

The upper MOS transistor Q1 is an N-channel MOS transistor, and is an example of an upper switch that conducts / cuts off a current path from the input voltage application terminal to which the input voltage _VIN is applied to the inductor L1. The drain of the upper MOS transistor Q1 is connected to the input voltage application terminal to which the input voltage _VIN is applied. The source of the upper MOS transistor Q1 is connected to one end of the inductor and the drain of the lower MOS transistor Q2. A gate signal G1 is supplied from the timing control circuit 1 to the gate of the upper MOS transistor Q1. The upper MOS transistor Q1 is turned on when the gate signal G1 is at a high level, and is turned off when the gate signal G1 is at a low level.

  The lower MOS transistor Q2 is an N-channel MOS transistor, and is an example of a lower switch that conducts / cuts off a current path from the ground terminal to the inductor L1. As described above, the drain of the lower MOS transistor Q2 is connected to one end of the inductor and the source of the upper MOS transistor Q1. The source of the lower MOS transistor Q2 is connected to the ground terminal. A gate signal G2 is supplied from the timing control circuit 1 to the gate of the lower MOS transistor Q2. The lower MOS transistor Q2 is turned on when the gate signal G2 is at a high level, and turned off when the gate signal G2 is at a low level. A diode can be used as the lower switch instead of the lower MOS transistor Q2. In this case, a sense resistor connected in series with the diode is provided, and the current detection circuit 4 detects the voltage across the sense resistor. There is a need to.

The upper MOS transistor Q1 and the lower MOS transistor Q2 are complementarily turned on / off under the control of the timing control circuit 1. As a result, a pulsed switch voltage _VSW is generated at the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2. It is preferable to provide a dead time when both the upper MOS transistor Q1 and the lower MOS transistor Q2 are turned off when the upper MOS transistor Q1 and the lower MOS transistor Q2 are switched on / off.

The inductor L1 and the output capacitor C1, a pulsed switch voltage _{V SW} smoothes and generates the output voltage _{V OUT,} supplies its output voltage _{V OUT} to an application terminal of the output voltage _{V OUT.}

The voltage dividing resistors R1 and R2 divide the output voltage _VOUT to generate a feedback voltage _VFB .

The error amplifier 2 generates an error signal V _ERR corresponding to the difference between the feedback voltage V _FB and the reference voltage output from the reference voltage source 3.

  The current detection circuit 4 detects the current flowing through the lower MOS transistor Q2 based on the drain-source voltage when the lower MOS transistor Q2 is on, that is, the voltage across the ON resistance of the lower MOS transistor Q2.

  The slope circuit 5 generates and outputs a slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the current detection circuit 4.

  When generating a slope voltage in which current information is reflected in the slope of the slope, the current detection circuit 4 and the slope circuit 5 may be configured as shown in FIG. On the other hand, when generating a slope voltage in which current information is reflected in the offset voltage of the slope, the current detection circuit 4 and the slope circuit 5 may be configured as shown in FIG. 4, for example.

  In the example shown in FIG. 2, the current detection circuit 4 is constituted by a voltage-current conversion circuit 4A. In the example shown in FIG. 2, the slope circuit 5 includes switches S1 to S3, capacitors C2 and C3, and a voltage-current conversion circuit 5A.

Each of the voltage / current conversion circuits 4A and 5A includes a timing control circuit 1, an error amplifier 2, a reference voltage source 3, a current detection circuit 4, a slope circuit 5, a comparator 6, an oscillator 7, and an overcurrent detection circuit. 8 is a circuit driven by an internal power supply voltage _VCC generated inside an IC [integrated circuit].

  The voltage-current conversion circuit 4A converts the drain-source voltage of the lower MOS transistor Q2 into a current and outputs the current. When the switch S1 is on, the capacitor C2 is charged by the output current of the voltage / current conversion circuit 4A. On the other hand, when the switch S2 is on, the capacitor C2 is discharged.

The voltage-current conversion circuit 5A converts the charging voltage _VCRG of the capacitor C2 into a current and outputs it. The capacitor C3 is charged by the output current of the voltage-current conversion circuit 5A. On the other hand, when the switch S3 is on, the capacitor C3 is discharged. The charging voltage of the capacitor C3 becomes the slope voltage V _SLP .

FIG. 3A and FIG. 3B are diagrams showing examples of the configuration of each of the voltage / current conversion circuits 4A and 5A. In the voltage-current conversion circuit shown in FIG. 3A, the current source CS1 supplies a current to a current mirror circuit composed of N-channel MOS transistors Q3 and Q4. Mirror ratio of the current mirror circuit composed of N-channel type MOS transistors Q3 and Q4 is 1: 1, the difference between the resistance value r4 of the current flowing through the resistor R4 to switch voltage _{V SW} and the resistance value r3 of the resistor R3 resistor R4 A value obtained by dividing by (r3-r4). Then, a current corresponding to the current flowing through the resistor R4 (current corresponding to the switch voltage _VSW that is the input voltage of the voltage-current conversion circuit 4A) is converted into voltage-current by the current mirror circuit including the P-channel MOS transistors Q5 and Q6. It is swept out as the output current of the circuit 4A. In the voltage-current converter circuit shown in FIG. 3B, a current corresponding to the input voltage of the voltage-current converter circuit flows through the resistor R5 by the series circuit of the resistor R5 and the PNP transistor Q7, and the voltage-current converter is connected to the connection node of the resistor R5 and the PNP transistor Q7 A voltage corresponding to the input voltage of the circuit is generated. Furthermore, a current corresponding to the connection node voltage of the resistor R5 and the PNP transistor Q7 (voltage corresponding to the input voltage of the voltage-current conversion circuit) flows through the resistor R6 by the series circuit of the NPN transistor Q8 and the resistor R6. Then, a current corresponding to the current flowing through the resistor R6 (current corresponding to the input voltage V of the voltage-current conversion circuit 5A) is output as the output current of the voltage-current conversion circuit by the current mirror circuit composed of the P-channel MOS transistors Q9 and Q10. Swept out.

  In the example shown in FIG. 4, the current detection circuit 4 is configured by a voltage-current conversion circuit 4A. In the example shown in FIG. 4, the slope circuit 5 includes switches S1, S2, and S4, a capacitor C2, and a constant current source CS2. Note that the value of the constant current output from the constant current source CS2 is desirably adjustable.

Each of the voltage / current conversion circuit 4A and the constant current source CS2 includes a timing control circuit 1, an error amplifier 2, a reference voltage source 3, a current detection circuit 4, a slope circuit 5, a comparator 6, an oscillator 7, The circuit is driven by an internal power supply voltage _VCC generated in an IC [integrated circuit] including a current detection circuit 8.

The voltage-current conversion circuit 4A converts the drain-source voltage of the lower MOS transistor Q2 into a current and outputs the current. The capacitor C2 is charged by the output current of the voltage / current conversion circuit 4A when the switch S1 is on, and is charged by the output current of the constant current source CS2 when the switch S4 is on. On the other hand, when the switch S2 is on, the capacitor C2 is discharged. The charging voltage of the capacitor C2 becomes the slope voltage V _SLP .

  Next, returning to FIG. 1, the description of the switching power supply apparatus 101 will be continued.

Comparator 6 generates a reset signal RESET is a comparison signal by comparing the output voltage of the slope circuit 5 and the error signal V _ERR. Since the slope voltage V _SLP generated by the slope circuit 5 has a fixed period, the reset signal RESET is a PWM [pulse width modulation] signal.

  The oscillator 7 generates a set signal SET that is a clock signal having a predetermined frequency.

  The overcurrent detection circuit 8 detects an overcurrent when the current flowing through the lower MOS transistor Q2 exceeds the threshold based on the voltage generated when the lower MOS transistor Q2 is in the on state. Using the detection result of the overcurrent detection circuit 8, the timing control circuit 1 performs an overcurrent protection operation. Details of the overcurrent protection operation will be described later.

<First Example of Overcurrent Protection>
FIG. 5 is a diagram showing a main configuration of the timing control circuit 1 according to the first embodiment of overcurrent protection. The timing control circuit 1 having the configuration shown in FIG. 5 includes an OR gate 11, a NOR gate 12, a D flip-flop 13, and an amplifier 14.

The OR gate 11 performs a logical OR operation between the reset signal RESET output from the comparator 6 and the fixed width signal FW, and outputs the operation result. The fixed width signal FW is a signal generated inside the timing control circuit 1, and is a predetermined time (a timing at which the set signal SET switches from the high level to the low level) from the falling edge of the set signal SET output from the oscillator 7. The pulse signal rises when a time corresponding to the fixed width W1 shown in FIG. 6 has elapsed. Fixed width W1 shown in FIG. 6 to be greater than the maximum pulse width of the gate signal G1 and the switch voltage V _SW at the normal operation, a predetermined time of the.

Here, a method for setting the fixed width W1 will be described. The switching power supply device 101 is also subject to disturbances such as input voltage fluctuation and output current fluctuation during normal operation. However, the pulse width of the gate signal G1 and the switch voltage V _SW must be avoided to be fixed to a fixed width W1 by disturbance despite the normal operation. Therefore, the fixed width W1 is determined from the zero cross frequency Fzero of the total gain of the control system of the switching power supply apparatus 101.

  If the zero cross frequency Fzero is high, the response in the control system becomes fast, and the modulation amount of the switching signal (gate signal G1) becomes large. On the other hand, if the zero cross frequency Fzero is low, the response in the control system is delayed, and the modulation amount of the switching signal (gate signal G1) becomes small. Therefore, a zero-cross frequency Fzero suitable for each field in which the switching power supply device 101 is used (in-vehicle field, industrial machine field, consumer device field, etc.) is determined, and a switching signal (gate signal G1) at a stable time is determined using simulation software. ) To obtain the maximum pulse width.

As one setting example of the switching power supply device 101 used in the in-vehicle field, the zero cross frequency Fzero is 100 kHz, the input voltage _VIN is 20 to 60 V, the output voltage _VOUT is 5 V, the switching frequency is 2.1 MHz, and the output current I _{When OUT} is set to 0 to 1A, the maximum pulse width of the switching signal (gate signal G1) is obtained with the zero cross frequency Fzero in increments of 20 kHz and the input voltage _VIN in increments of 10V, as shown in FIG. FIG. 13 is a three-dimensional plot of the maximum pulse width of the switching signal shown in FIG. If the fixed width W1 is set in the area of the arrow shown in FIG. 13, that is, the area above the boundary surface F1, the pulse width of the gate signal G1 and the switch voltage _VSW is fixed by the disturbance despite the normal operation. It is possible to avoid being fixed to W1.

However, in FIG. 12 and FIG. 13, circuit variations and the like are not taken into consideration. Therefore, for example, as shown in FIG. 14, the fixed width W1 is set in a region above the boundary surface F2 obtained by multiplying the boundary surface F1 by 2.2. It is desirable. This makes it possible to avoid even with variations in the circuit, the pulse width of the gate signal G1 and the switch voltage V _SW is fixed to the fixed width W1 by disturbance despite the normal operation.

Fixed width W1 may be a single value, but at least if one is Kaware, the maximum on-duty of acceptable gate signal G1 and the switch voltage V _SW is different (normal operation of the input voltage V _IN and the output voltage V _OUT Since the allowable maximum pulse width of the gate signal G1 and the switch voltage _VSW is different), the value of the fixed width W1 may be a function of the input voltage _VIN and the output voltage _VOUT . In this case, the timing control circuit 1 may have a storage unit that stores the functional equation, and may calculate the value of the fixed width W1 by calculation using the functional equation. The value of the fixed width W1 and the value of the input voltage _VIN the value of the output voltage V _OUT of the reference and fixed-width data table has a storage section storing a data table indicating a relationship between the value W1 may be obtained.

It is not practical to monitor the input voltage V _IN and the output voltage V _OUT in real time and change the value of the fixed width W1 according to the input voltage V _IN and the output voltage V _OUT. It is preferable to obtain the value of the fixed width W1 within the range of V _IN and the output voltage V _OUT .

For example, when the output voltage _VOUT is set to one value as in the setting example described above, the value of the fixed width W1 is made a function of only the input voltage _VIN . In this case, for example, a value suitable for the type of battery voltage used as the input voltage _VIN may be selected from a plurality of fixed width W1 values.

Further, for example, when a set value of the output voltage _VOUT can be selected from a plurality of values by a resistance value of a resistor externally attached to the timing control circuit 1, for example, a plurality of fixed widths W1 set. A value suitable for the set value of the output voltage _VOUT may be selected from the values.

  The NOR gate 12 performs a negative OR operation between the output signal of the OR gate 11 and the output signal OC of the overcurrent detection circuit 8, and outputs the calculation result. The overcurrent detection circuit 8 sets the output signal OC to a high level when determining that the current flowing through the lower MOS transistor Q2 exceeds the threshold, and determines that the current flowing through the lower MOS transistor Q2 does not exceed the threshold. In this case, the output signal OC is set to low level. A period in which the output signal OC is at a high level is a period in which an overcurrent is detected by the overcurrent detection circuit 8.

  A high-level constant signal REG is supplied to the data input terminal (D) of the D flip-flop 13, and a set signal SET output from the oscillator 7 is supplied to the clock pulse terminal (CP) of the D flip-flop 13. The output signal of the NOR gate 12 is supplied to the reset terminal (R) of the flip-flop 13. The D flip-flop 13 holds the value of the data (constant signal REG) input to the data input terminal (D) at the timing when the set signal SET switches from the high level to the low level. The signal output from the output terminal (Q) of the D flip-flop 13 is amplified by the amplifier 14 and becomes the gate signal G1.

  FIG. 6 is a timing chart showing an operation example of the timing control circuit 1 shown in FIG. FIG. 6 shows an operation in the case where the switching power supply device 101 enters a normal overcurrent state at time t0 and then continues in a normal overcurrent state. Here, the normal overcurrent state is a state in which an overcurrent flows through the switching power supply device 101 when the load of the switching power supply device 101 becomes an overload.

Since the normal overcurrent state continues and the output voltage _VOUT decreases after time t0, no pulse is generated in the reset signal RESET after the D flip-flop 13 is reset once by the pulse of the reset signal RESET.

In the overcurrent protection operation period, when the output signal OC of the overcurrent detection circuit 8 is at a high level, a low level signal continues to be supplied to the reset terminal (R) of the D flip-flop 13, so that the gate signal G1 and the switch The voltage _VSW becomes low level.

Also, during the overcurrent protection operation period, when the output signal OC of the overcurrent detection circuit 8 is at a low level, the D flip-flop 13 is set by the falling edge of the set signal SET, and the D flip-flop is driven by the pulse of the fixed width signal FW. since 13 is reset, the pulse width of the gate signal G1 and the switch voltage V _SW is fixed to a fixed width W1.

Thus, the overcurrent protection operation period, the switching frequency is lower than during normal operation with a pulse width of the gate signal G1 and the switch voltage V _SW is fixed to a fixed width W1. Thereby, the on-duty of the switch voltage _VSW can be reduced. That is, the overcurrent protection operation is performed while controlling the on / off operation of the upper MOS transistor Q1 by the switching signal (gate signal G1).

In FIG. 6, in one continuous period, which is the output signal OC of the overcurrent detection circuit 8 is at a high level, the pulse of the gate signal G1 and the switch voltage V _SW is thinned one, which is only It is an example. Only the pulse of the gate signal G1 and the switch voltage V _SW is thinned one, when the current flowing through the upper MOS transistor Q1 is not lower than the threshold value, for example, as in the timing chart shown in FIG. 7, over in one continuous period output signal OC is at a high level of the current detection circuit 8, a pulse of the gate signal G1 and the switch voltage V _SW is more thinned.

<Second Example of Overcurrent Protection>
As described above, the overcurrent detection circuit 8 is a circuit that determines whether or not the current flowing through the lower MOS transistor Q2 exceeds a threshold value. Therefore, in the first embodiment of the overcurrent protection described above, the overcurrent protection operation can be performed against the overcurrent state that occurs when the load is short-circuited, but the connection between the upper MOS transistor Q1 and the lower MOS transistor Q2 is possible. An overcurrent protection operation cannot be performed against an overcurrent state that occurs when the node is short-circuited to the ground potential.

  Here, only in order to perform an overcurrent protection operation against an overcurrent state that occurs when the connection node of the upper MOS transistor Q1 and the lower MOS transistor Q2 is short-circuited to the ground potential, FIG. It is conceivable to add the conventional overcurrent protection circuit shown. However, such a solution is not preferable because the circuit scale is significantly increased.

  Therefore, in the second embodiment of overcurrent protection, an overcurrent state that occurs when the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 is short-circuited to the ground potential without significantly increasing the circuit scale. Enable overcurrent protection operation.

  FIG. 8 is a diagram showing a main configuration of the timing control circuit 1 according to the second embodiment of overcurrent protection. The timing control circuit 1 configured as shown in FIG. 8 has a configuration in which a continuous pulse detection circuit 15 and a shutdown circuit 16 are added to the timing control circuit 1 configured as shown in FIG.

  The continuous pulse detection circuit 15 monitors the output signal of the D flip-flop 13 and determines whether or not a pulse having a fixed width W1 is continuously generated at the switching frequency during normal operation.

The shutdown circuit 16 operates according to the detection result of the continuous pulse detection circuit 15. When the continuous pulse detection circuit 15 detects that pulses having a fixed width W1 are continuously generated at the switching frequency during normal operation, the shutdown circuit 16 switches the upper MOS transistor Q1 and the lower MOS transistor Q2. The control operation of the timing control circuit 1 is stopped so that the operation stops and the upper MOS transistor Q1 is turned off. Note that overcurrent protection other than stopping the control operation of the timing control circuit 1 may be performed. For example, when the continuous pulse detection circuit 15 detects that pulses having a fixed width W1 are continuously generated at the switching frequency during normal operation, the switching power supply device 101 and the supply source of the input voltage _VIN (for example, a battery) ) May be cut off. Also in this case, the switching operation of the upper MOS transistor Q1 and the lower MOS transistor Q2 is stopped, and the upper MOS transistor Q1 is turned off.

  Since the overcurrent protection operation for the normal overcurrent state is the same as that of the first embodiment of the overcurrent protection described above, the description thereof is omitted. Hereinafter, an overcurrent protection operation against an overcurrent state that occurs when the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 is short-circuited to the ground potential will be described.

  FIG. 9 is a timing chart showing an operation example of the timing control circuit 1 shown in FIG. FIG. 9 shows the operation when the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 is short-circuited to the ground potential at time t2, and the overcurrent state due to the short-circuit continues thereafter.

  The overcurrent detection circuit 8 determines whether or not the current flowing through the lower MOS transistor Q2 exceeds a threshold value. Therefore, in FIG. 9, the output signal OC is held at a low level.

  Further, after time t1, since the overcurrent state that occurs when the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2 is short-circuited to the ground potential, no pulse is generated in the reset signal RESET.

  As a result, a pulse having a fixed width W1 is continuously generated twice at the switching frequency in the normal operation in the output signal V13 of the D flip-flop 13 after time t1, and the control operation of the timing control circuit 1 is stopped at time t2. . That is, an overcurrent protection operation for stopping the on / off operation of the upper MOS transistor Q1 is performed at time t2.

  In the above-described embodiment, when it is detected that pulses having a fixed width W1 are continuously generated at the switching frequency during normal operation, the duty ratio of the switching signal (gate signal G1) is outside the normal modulation range. Although it is determined that it is in an overcurrent state, it is more generalized that a pulse with a fixed width W1 has a switching cycle (reciprocal of switching frequency) in normal operation n times within m cycles (where n is less than or equal to m) When it is detected that a natural number) or more has occurred, it may be determined that the overcurrent state in which the duty ratio of the switching signal (gate signal G1) is outside the normal modulation range. Each value of m and n is set appropriately, an overcurrent state where the duty ratio of the switching signal (gate signal G1) is within the normal modulation range, and a modulation range where the duty ratio of the switching signal (gate signal G1) is normal What is necessary is just to avoid misdetecting that it is the overcurrent state which is outside. It is possible to detect that a pulse having a fixed width W1 is generated n times (where n is a natural number less than or equal to m) within m cycles during normal operation. This is nothing but detecting an abnormal value of the duty ratio of the signal G1).

<Other overall configuration>
FIG. 15 is a diagram illustrating an overall configuration example of a voltage mode control type switching power supply device (voltage mode control type switching regulator). In FIG. 15, the same parts as those in FIGS. 1 and 8 are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate. The switching power supply 102 of this configuration example is a voltage mode control type switching power supply that performs a step-down operation for stepping down an input voltage, and includes a timing control circuit 1, an upper MOS transistor Q1, a lower MOS transistor Q2, and an inductor. L1, an output capacitor C1, voltage dividing resistors R1 and R2, an error amplifier 2, a reference voltage source 3, a comparator 6, an oscillator 7, a ramp circuit 9, an abnormality detection circuit 10, an amplifier 14, And a shutdown circuit 16.

  An amplifier 14 that functions as a driver is provided between the timing control circuit 1 and the gate of the upper MOS transistor Q1. The timing control signal output from the timing control circuit 1 is amplified by the amplifier 14 and is supplied to the gate of the upper MOS transistor Q1 as a switching signal (gate signal G1). Although not shown, a driver is similarly provided between the timing control circuit 1 and the gate of the lower MOS transistor Q2. A similar driver may be provided for the switching power supply apparatus 101 shown in FIG.

The ramp circuit 9 generates and outputs a ramp voltage having a slope corresponding to the input voltage _VIN . The comparator 6 compares the lamp voltage and the error signal V _ERR output from the ramp circuit 9 generates a reset signal RESET is compared signals. The ramp circuit 9 suppresses fluctuations in the error signal V _ERR by feedforward control of the slope of the ramp voltage when the input voltage _VIN fluctuates.

  The abnormality detection circuit 10 monitors the duty ratio of the timing control signal output from the timing control circuit 1 to the amplifier 14, and when the duty ratio (on duty) of the timing control signal exceeds a predetermined value, the switching signal ( It is determined that the abnormal state where the duty ratio of the gate signal G1) is outside the normal modulation range.

The shutdown circuit 16 operates according to the determination result of the abnormality detection circuit 10. When the abnormality detection circuit 10 determines that the duty ratio of the switching signal (gate signal G1) is outside the normal modulation range, the shutdown circuit 16 switches the upper MOS transistor Q1 and the lower MOS transistor Q2. The control operation of the timing control circuit 1 is stopped so that the operation stops. Note that abnormality protection other than the stop of the control operation of the timing control circuit 1 may be performed. For example, when the abnormality detection circuit 10 determines that the duty ratio of the switching signal (gate signal G1) is outside the normal modulation range, the switching power supply device 102 and the supply source of the input voltage _VIN (for example, The electrical connection with the battery may be cut off. Also in this case, the switching operation of the upper MOS transistor Q1 and the lower MOS transistor Q2 is stopped.

In the switching power supply 102, the abnormality detection circuit 10 monitors the duty ratio of the timing control signal output from the timing control circuit 1 to the amplifier 14. However, the abnormality detection circuit 10 does not operate as in the switching power supply 103 shown in FIG. The duty ratio of the switching signal (gate signal G1) may be monitored, and the abnormality detection circuit 10 may monitor the value of the error signal V _ERR as in the switching power supply device 104 shown in FIG. The error signal V _ERR is a control signal used to generate the switching signal (gate signal G1), and since the value of the error signal V _ERR and the duty ratio of the switching signal (gate signal G1) are correlated, Similar abnormality protection can be realized by monitoring the value of the error signal V _ERR instead of the duty ratio of the timing control signal or the switching signal (gate signal G1).

<Application>
Next, application examples of the switching power supply devices 101 to 104 described above will be described. FIG. 10 is an external view showing a configuration example of a vehicle equipped with an in-vehicle device. The vehicle X of this configuration example includes onboard devices X11 to X17 and a battery (not shown) that supplies power to these onboard devices X11 to X17.

  The in-vehicle device X11 is an engine control unit that performs control related to the engine (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto cruise control).

  The in-vehicle device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The in-vehicle device X13 is a transmission control unit that performs control related to the transmission.

  The in-vehicle device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power Steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The in-vehicle device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The in-vehicle device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment item or a manufacturer option product such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, and an air conditioner.

  The in-vehicle device X17 is an electronic device that is arbitrarily attached to the vehicle X by the user, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [Electronic Toll Collection System].

  In addition, the switching power supply devices 101 to 104 described above can be incorporated in any of the in-vehicle devices X11 to X17.

<Other variations>
The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  For example, in the above embodiment, the step-down switching regulator has been described as an example. However, the application target of the present invention is not limited to this, and can be applied to all switching regulators.

  As described above, the above embodiments are examples in all respects and should not be considered to be restrictive, and the technical scope of the present invention is not the description of the above embodiments, but the claims. It is to be understood that all changes that come within the scope of the claims, are equivalent in meaning to the claims, and fall within the scope of the claims.

  The present invention can be used for a switching regulator used in all fields (such as home appliance field, automobile field, and industrial machine field).

DESCRIPTION OF SYMBOLS 1 Timing control circuit 2 Error amplifier 3 Reference voltage source 4 Current detection circuit 5 Slope circuit 6 Comparator 7 Oscillator 8 Overcurrent detection circuit 9 Ramp circuit 10 Abnormality detection circuit 11 OR gate 12 NOR gate 13 D flip-flop 14 Amplifier 15 Continuous pulse detection Circuit 16 Shutdown circuit 101-104 Switching power supply C1 Output capacitor C2, C3 Capacitor CS1 Current source CS2 Constant current source L1 Inductor Q1 Upper MOS transistor Q2 Lower MOS transistor Q3-Q10 Transistors R1, R2 Voltage dividing resistor R3-R6 Resistor S1 -S4 switch X vehicle X11-X17 in-vehicle equipment

Claims (12)

A switching regulator control circuit for generating a switching signal for controlling an on / off operation of the switching element, which is used in a switching regulator that converts an input voltage into an output voltage by switching of the switching element;
Based on the duty ratio of the switching signal or a variable correlated with the duty ratio of the control signal used to generate the switching signal, an abnormal state in which the duty ratio is outside the normal modulation range is detected. An abnormal state detector to perform,
When the abnormal state is detected by the abnormal state detection unit, an abnormality protection unit that stops switching of the switching element;
A switching regulator control circuit comprising:   2. The switching regulator according to claim 1, wherein the modulation range in which the duty ratio is normal indicates a modulation range of the duty ratio that appears as a response to a disturbance that can be assumed during operation of the switching regulator having the switching regulator control circuit. Control circuit.   2. The abnormality protection unit detects a pulse width of the switching signal, a voltage correlated with the pulse width, or a current correlated with the pulse width, and detects the abnormal state based on the detection result. Or the switching regulator control circuit of Claim 2. The upper limit of the pulse width is limited to a fixed width,
The abnormality detection unit detects the abnormal state when the switching period of the fixed-width pulse in the switching signal is generated n times (where n is a natural number of m or less) within m cycles during normal operation. The switching regulator control circuit as described in any one of Claims 1-3 detected.   The switching regulator control circuit according to claim 4, wherein a plurality of values of the fixed width are set, and can be arbitrarily selected from the plurality of settings.   6. The switching regulator control circuit according to claim 4, wherein the value of the fixed width is at least one function of an input voltage and an output voltage of a switching regulator having the switching regulator control circuit. A first switch having a first end connected to a first application end to which an input voltage is applied;
A second switch having a first end connected to a second end of the first switch and a second end connected to a second application end to which a voltage lower than the input voltage is applied;
A current detector for detecting a current flowing through the second switch;
An overcurrent detector for detecting an overcurrent flowing through the second switch;
A control unit for controlling the first switch and the second switch according to the current detected by the current detection unit;
With
The control unit accumulates current information detected by the current detection unit during a predetermined period while the first switch is in an off state, and generates a slope voltage based on the accumulated current information. A voltage generation unit, controlling the first switch and the second switch according to the slope voltage;
If the first switch and the second switch are controlled according to the slope voltage, the pulse width of the pulse generated in the switching signal for controlling the on / off operation of the first switch and the second switch is fixed. When exceeding the width, the pulse width of the pulse generated in the switching signal is limited to the fixed width,
During the period when the overcurrent is detected by the overcurrent detection unit, a pulse is not generated in the switching signal, and the fixed-width pulse is continuously generated in the switching signal at a switching frequency during normal operation. A current mode control type switching power supply, wherein the first switch is turned off by stopping the on / off operation of the first switch. The controller is
An error amplifier that generates an error signal according to a difference between a voltage according to an output voltage of the current mode control type switching power supply device and a reference voltage;
A comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal;
An oscillator that generates a set signal that is a clock signal of a predetermined frequency;
A timing control circuit for controlling on / off of the first switch and on / off of the second switch according to the set signal and the reset signal;
The current mode control type switching power supply device according to claim 7.   The current mode control type switching power supply device according to claim 7 or 8, wherein the value of the fixed width is a function of the input voltage and an output voltage of the current mode control type switching power supply device. The second switch is a MOS transistor;
The current detection unit detects a current flowing through the second switch using a voltage across the on-resistance of the MOS transistor;
10. The current mode control type switching power supply according to claim 7, wherein the overcurrent detection unit detects an overcurrent flowing through the second switch using a voltage across the ON resistance of the MOS transistor. 11. apparatus. A switching regulator comprising: the switching regulator control circuit according to any one of claims 1 to 6; and a switching element that is on / off controlled by a switching signal output from the switching regulator control circuit, or
An in-vehicle device comprising the current mode control type switching power supply device according to any one of claims 7 to 10. In-vehicle device according to claim 11,
A battery for supplying power to the in-vehicle device;
A vehicle comprising: