JP2014003770A - Power supply device, and on-vehicle apparatus and vehicle using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply device that can implement appropriate mode switching.SOLUTION: A comparator 602 compares a voltage V603 appearing across both ends of a resistance 603 with a predetermined threshold voltage Vth62, and decides a logic level of a selector control signal S62 on the basis of the result of comparison. The output signal S62 is at a high level when the voltage V603 is lower than the threshold voltage Vth62, and is at a low level when the voltage V603 is higher than the threshold voltage Vth62. A selector 114 selects either one of a PWM pulse S1a and a fixed on-time pulse S1b as an output signal S2 on the basis of the logic level of the selector control signal S62 input from the comparator 602.

Description

  The present invention relates to a power supply device, and an in-vehicle device and a vehicle using the same.

  Recently, a switching regulator (chopper type DC / DC converter) has been put into practical use as a low power consumption type power supply device in the in-vehicle field. The switching regulator performs operation mode switching control according to the load in order to improve efficiency at light load.

  For example, in a load state (heavy load state) in which the output current Iout is sufficiently larger than the internal consumption current Icc, the operation is performed in a heavy load mode (for example, PWM mode) giving priority to the stability of the output current Iout. On the other hand, in a load state (light load state) in which the output current Iout is reduced to the same level as the internal consumption current Icc, the operation is performed in a light load mode (for example, a fixed on-time mode) that prioritizes reduction of the consumption current.

  In addition, Patent Document 1 and Patent Document 2 can be cited as examples of related art related to the above.

JP 2010-81749 A JP 2011-61971 A

  It is very important to appropriately determine a switching load point for switching the plurality of operation modes. For example, depending on the application of the power supply device, the hysteresis of the switching load point is eliminated by eliminating the deviation between the switching load point from the heavy load mode to the light load mode and the switching load point from the light load mode to the heavy load mode. Is required.

  In view of the above-described problems, an object of the present invention is to provide a power supply device capable of appropriately switching operation modes.

  To achieve the above object, a power supply device according to the present invention includes a switching element that is turned on / off to generate an output voltage from an input voltage, and a control that performs on / off control of the switching element at a predetermined period. Operation control for comparing a resistance voltage generated between both ends of a circuit and a resistor provided in an output path of the output voltage with a predetermined threshold voltage and determining an operation method of the control circuit according to a result of the comparison And a comparator that generates a signal (first configuration).

  The power supply device having the first configuration includes a heavy load mode in which the control circuit prioritizes output stability and a light load mode in which reduction of internal current consumption is prioritized according to the operation control signal. It is preferable to adopt a configuration (second configuration) characterized by determining which operation method to use.

  In the power supply device having the second configuration, the control circuit operates in the light load mode when the resistance voltage is lower than a predetermined threshold voltage, and when the resistance voltage is higher than the predetermined threshold voltage. A configuration (third configuration) that operates in the heavy load mode is preferable.

  In the power supply device having the third configuration, the resistor is an overcurrent detection resistor that detects an overcurrent according to a potential difference generated at both ends of the resistor, and the overcurrent detection circuit included in the power supply device includes: Are preferably connected to each other (fourth configuration).

  Further, in the power supply device having the fourth configuration, the control circuit includes a first pulse signal generation unit that generates a first pulse signal, a second pulse signal generation unit that generates a second pulse signal, and the control A selector (fifth configuration) may be provided that includes a selector that supplies either the first pulse signal or the second pulse signal to the switching element according to a signal.

  Further, in the power supply device having the fifth configuration, the first pulse signal is a PWM [pulse width modulation] signal whose on-time is changed by output feedback control, and the second pulse signal is on-time and on-time. A configuration (sixth configuration) is characterized in that the number of times is a fixed on-time pulse.

  Further, the power supply device having the sixth configuration is characterized in that the power supply device is connected between the switching element and the output voltage application end, and between the first end of the coil and the ground end. And a capacitor connected between the second end of the coil and the ground end (seventh configuration).

  In the power supply device having the seventh configuration, the resistor is connected between the second end of the coil and the application end of the output voltage (eighth configuration). It is good to.

  In addition, the in-vehicle device according to the present invention may have a configuration (9th configuration) including a power supply device having any one of the first to eighth configurations.

  In addition, the vehicle according to the present invention may have a configuration (tenth configuration) including the in-vehicle device having the ninth configuration and a battery for supplying power to the in-vehicle device.

  According to the present invention, since the switching load point between the heavy load mode and the light load mode has no hysteresis, the operation mode can be appropriately switched. According to the present invention, the switching load point can be changed by the user by changing the resistance value of the resistor provided in the output path of the output voltage.

Block diagram showing the overall configuration of the power supply Timing chart showing an example of operation in PWM mode Timing chart showing an example of operation in fixed on-time mode The figure which shows a mode that the behavior of switch voltage changes according to load Waveform diagram showing switching waveforms in PWM mode Waveform diagram showing switching waveforms in fixed on-time mode Schematic diagram showing an example of a conventional switching load point Circuit block diagram showing a part of the configuration of the power supply The schematic diagram which showed an example of the switching load point of this invention External view showing a configuration example of a vehicle equipped with a power supply device

<Overall configuration>
FIG. 1 is a block diagram showing the overall configuration of the power supply apparatus. The power supply device 1 of this configuration example is a step-down type having a semiconductor device 10 and various discrete components (coil L1, diode D1, resistors R1 and R2, and capacitors C1 to C6) externally connected thereto. It is a switching regulator.

  The semiconductor device 10 is a monolithic semiconductor integrated circuit device (for example, an in-vehicle power supply IC) in which a switching control circuit 100, an internal power supply voltage generation circuit 200, and a power supply switching circuit 300 are integrated. The semiconductor device 10 has external terminals T1 to T10.

  Outside the semiconductor device 10, the external terminal T1 is connected to the ground terminal via the capacitor C4. The external terminal T2 is connected to the application end of the output voltage Vo. A capacitor C2 is connected between the application terminal of the output voltage Vo and the ground terminal. The external terminal T3 is connected to the application terminal of the input voltage Vi (for example, the positive electrode of the vehicle battery). A capacitor C1 is connected between the application terminal of the input voltage Vi and the ground terminal. The external terminal T4 is connected to the first end of the coil L1 and the cathode of the diode D1. The second end of the coil L1 is connected to the application end of the output voltage Vo. The anode of the diode D1 is connected to the ground terminal. The diode D1 can be replaced with a synchronous rectification transistor. The external terminal T5 is connected to the application terminal of the input voltage Vi through the capacitor C3. The external terminal T6 is an output terminal for a power good signal S8 described later. The external terminal T7 is an input terminal for an external power supply voltage Vcc (a constant voltage generated from the input voltage Vi). In the case where the input voltage Vi is directly supplied as the external power supply voltage Vcc, the external terminal T7 can be omitted. The external terminal T8 is connected to the ground terminal via the capacitor C5. The external terminal T9 is connected to the ground terminal via a resistor R1 and a capacitor C6 connected in series. The external terminal T10 is connected to the ground terminal via the resistor R2.

  The switching control circuit 100 is a circuit block that generates an output voltage Vo from an input voltage Vi by turning on / off the output transistor 101. The output transistor 101, a driver 102, a low-level voltage generator 103, and a feedback voltage generator Unit 104, soft start voltage generation unit 105, error amplifier 106, oscillator 107, slope voltage generation unit 108, comparator 109, PWM [pulse width modulation] pulse generation unit 110, and on-time fixed pulse generation unit 111, a one-shot pulse generation unit 112, a selector control unit 113, a selector 114, comparators 115 and 116, an OR gate 117, and an N-channel MOS field effect transistor 118.

  The output transistor 101 is connected between the external terminal T3 and the external terminal T4, and is turned on / off to generate the output voltage Vo from the input voltage Vi. In this configuration example, a P-channel MOS [metal oxide semiconductor] field effect transistor is used as the output transistor 101. However, an N-channel MOS field effect transistor may be used, or a pnp type or an npn type. The bipolar transistor may be replaced.

  The driver 102 generates the gate signal G1 of the output transistor 101 according to the pulse signal S2 output from the selector 114, and turns on / off the output transistor 101. The upper power supply terminal of the driver 102 is connected to the external terminal T3 (application terminal for the input voltage Vi). The lower power supply terminal of the driver 102 is connected to the output terminal (application terminal of the low level voltage VL) of the low level voltage generation unit 103. Therefore, the gate signal G1 is pulse-driven between the input voltage Vi and the low level voltage VL. In this configuration example, an inverter is used as the driver 102. Therefore, the gate signal G1 is at a low level when the pulse signal S2 is at a high level, and is at a high level when the pulse signal S2 is at a low level. That is, the output transistor 101 is turned on when the pulse signal S2 is at a high level and turned off when the pulse signal S2 is at a low level.

  The low level voltage generation unit 103 is connected between the lower power supply terminal of the driver 102 and the external terminal T5, and generates a low level voltage VL obtained by reducing the input voltage Vi by a predetermined value. By providing the low level voltage generation unit 103, the drive voltage (= Vi−VL) applied between the upper power supply terminal and the lower power supply terminal of the driver 102 is within an appropriate range even if the input voltage Vi varies. Therefore, it is not necessary to increase the breakdown voltage of the driver 102 unnecessarily.

  The feedback voltage generation unit 104 includes resistors Ra and Rb connected in series between the unit terminal T2 and the ground terminal, and a feedback voltage Vfb (= output voltage Vo) corresponding to the output voltage Vo from a connection node of the resistors Ra and Rb. Of the divided voltage).

  The soft start voltage generation unit 105 generates a soft start voltage Vss that gradually increases when the power supply device 1 is started up by charging the capacitor C5 connected to the external terminal T8. The soft start voltage generation unit 105 also has a function of generating a soft start completion signal S3.

  The error amplifier 106 has a lower one of a predetermined reference voltage Vref and a soft start voltage Vss applied to the first and second non-inverting input terminals (+) and a feedback applied to the inverting input terminal (−). An error voltage ERR corresponding to the difference from the voltage Vfb is generated. The output terminal of the error amplifier 106 is connected to the phase compensation resistors R1 and C6 via the external terminal T9.

  The oscillator 107 generates a clock signal CLK having a predetermined frequency. The frequency of the clock signal CLK can be adjusted using a resistor R2 connected to the external terminal T10.

  The slope voltage generator 108 generates a slope voltage SLP having a sawtooth waveform, a triangular waveform, or a waveform conforming thereto in synchronization with the clock signal CLK.

  The comparator 109 compares the error voltage ERR applied to the inverting input terminal (−) and the slope voltage SLP applied to the non-inverting input terminal (+) to generate a comparison signal S0. The comparison signal S0 is a binary signal that is at a low level when the error voltage ERR is higher than the slope voltage SLP and that is at a high level when the error voltage ERR is lower than the slope voltage SLP.

  The PWM pulse generator 110 generates a PWM pulse S1a based on the clock signal CLK and the comparison signal S0. More specifically, the PWM pulse generation unit 110 sets the PWM pulse S1a to a high level using the rising edge of the clock signal CLK as a trigger, while setting the PWM pulse S1a to a low level using the rising edge of the comparison signal S0 as a trigger. Reset.

  The on-time fixed pulse generation unit 111 generates an on-time fixed pulse S1b having a constant on-time ton and the number of on-times N, triggered by the falling edge of the comparison signal S0. The generation operation of the on-time fixed pulse S1b is performed in synchronization with the clock signal CLK.

  The one-shot pulse generator 112 monitors the soft start completion signal S3, and when the soft start voltage Vss exceeds a predetermined threshold voltage Vth4, the one-shot pulse S1c having a constant on-time tfix and on-time M is fixed once. Is generated. The operation of generating the one-shot pulse S1c is performed in synchronization with the clock signal CLK. In FIG. 1, the on-time fixed pulse generation unit 111 and the one-shot pulse generation unit 112 are depicted as independent blocks, but the one-shot pulse generation unit 112 and the on-time fixed pulse generation unit 111 are part of the circuit. Alternatively, the circuit scale can be reduced by sharing all of them.

  The selector control unit 113 generates the selector control signal S4 so as to select one of the PWM pulse S1a and the on-time fixed pulse S1b according to the load weight (the magnitude of the output current Io). More specifically, the selector control unit 113 includes a counter that counts the low level period of the comparison signal S0, and whether or not the comparison signal S0 is maintained at the low level over a predetermined mask period Tmask. Accordingly, the selector control signal S4 is generated so as to select one of the PWM pulse S1a and the on-time fixed pulse S1b. That is, it can be said that the selector control unit 113 has a configuration in which the weight of the load (the magnitude of the output current Io) is determined by monitoring the period in which the comparison signal S0 is maintained at the low level.

  The selector 114 selects any one of the PWM pulse S1a, the on-time fixed pulse S1b, and the one-shot pulse S1c as the output signal S2 based on the soft start completion signal S3 and the selector control signal S4.

  The comparator 115 compares the feedback voltage Vfb applied to the inverting input terminal (−) and the threshold voltage Vth1 (<Vref) applied to the non-inverting input terminal (+) to generate the short protection signal S5. The short protection signal S5 is at a low level (normal logic level) when the feedback voltage Vfb is higher than the threshold voltage Vth1, and is at a high level (abnormal (eg, ground fault) when the feedback voltage Vfb is lower than the threshold voltage Vth1. Logic level) at the time of occurrence.

  The comparator 116 compares the feedback voltage Vfb applied to the non-inverting input terminal (+) and the threshold voltage Vth2 (> Vref) applied to the inverting input terminal (−) to generate the overvoltage protection signal S6. The overvoltage protection signal S6 is low level (normal logic level) when the feedback voltage Vfb is lower than the threshold voltage Vth2, and is high level (abnormal (when overvoltage occurs) when the feedback voltage Vfb is higher than the threshold voltage Vth2. ) Logic level).

  The OR gate 117 performs an OR operation on the short protection signal S5 applied to the first input terminal and the overvoltage protection signal S6 applied to the second input terminal, thereby generating the abnormality detection signal S7. The abnormality detection signal S7 becomes low level when both the short protection signal S5 and the overvoltage protection signal S6 are low level (normal logic level), and at least one of the short protection signal S5 and the overvoltage protection signal S6 is high level. High level when (logical level at the time of abnormality).

  N-channel MOS field effect transistor 118 forms an open drain output stage for outputting power good signal S8 from external terminal T6 to a microcomputer or the like. The drain of the transistor 118 is connected to the external terminal T6. The external terminal T6 is pulled up by an external resistor (not shown). The source of the transistor 118 is connected to the ground terminal. The gate of the transistor 118 is connected to the output terminal of the OR gate 117. The transistor 118 is turned off when the abnormality detection signal S7 is at a low level, and turned on when the abnormality detection signal S7 is at a high level. Therefore, the power good signal S8 is at a high level (normal logic level) when the abnormality detection signal S7 is at a low level, and is at a low level (logical level at abnormality) when the abnormality detection signal S7 is at a high level. Become.

  The internal power supply voltage generation circuit 200 is a circuit block that generates an internal power supply voltage Vreg from an external power supply voltage Vcc (for example, input voltage Vi) applied to the external terminal T7. And a pre-regulator unit 203, a reference voltage generation unit 204, and resistors 205 and 206 (resistance values: R205 and R206).

  The drain of the transistor 201 is connected to the external terminal T7. The source of the transistor 201 is connected to the external terminal T7, and is also connected to the ground terminal via resistors 205 and 206 connected in series. The gate of the transistor 201 is connected to the output terminal of the operational amplifier 202. The non-inverting input terminal (+) of the operational amplifier 202 is connected to the output terminal of the reference voltage generation unit 204. An inverting input terminal (−) of the operational amplifier 202 is connected to a connection node (application terminal of the divided voltage Vreg ′) between the resistor 205 and the resistor 206. The pre-regulator unit 203 generates a drive voltage for the reference voltage generation unit 204 from the external power supply voltage Vcc. The reference voltage generation unit 204 operates in response to the drive voltage supplied from the preregulator unit 203, and generates a constant reference voltage VREF (for example, a band gap voltage having a flat temperature characteristic).

  In the internal power supply voltage generation circuit 200 configured as described above, the operational amplifier 202 has the same reference voltage VREF applied to the non-inverting input terminal (+) and the divided voltage Vreg ′ applied to the inverting input terminal (−). Thus, the conductivity of the transistor 201 is controlled. Therefore, the internal power supply voltage Vreg generated by the internal power supply voltage generation circuit 200 is expressed by the following equation (1).

  The power supply switching circuit 300 is a circuit block that switches which of the internal power supply voltage Vreg and the output voltage Vo is supplied as the drive voltage Vsup of the switching control circuit 100, and includes switches 301 and 302.

  The switch 301 is a switch element that conducts / cuts off between the application terminal of the internal power supply voltage Vreg and the application terminal of the drive voltage Vsup. As the switch 301, for example, a P-channel MOS field effect transistor can be used.

  The switch 302 is a switch element that conducts / cuts off between the application terminal of the output voltage Vo and the application terminal of the drive voltage Vsup. As the switch 302, for example, a P-channel MOS field effect transistor can be used.

  In the power supply device 1 configured as described above, the output transistor 101 is repeatedly turned on and off, whereby the magnetic energy is repeatedly accumulated and released in the coil L1, and the output voltage Vo obtained by stepping down the input voltage Vi is generated. Note that the switch voltage Vsw appearing at the external terminal T4 is a pulse voltage that is at a high level (approximately the input voltage Vi) when the output transistor 101 is on and is at a low level (approximately the ground voltage GND) when the output transistor 101 is off. The voltage Vo corresponds to a voltage obtained by smoothing the switch voltage Vsw.

  Although not clearly shown in FIG. 1, the semiconductor device 10 is integrated with various protection circuits (thermal shutdown circuit, overcurrent protection circuit, voltage drop protection circuit, etc.) in addition to the circuit block described above.

<PWM mode (heavy load mode)>
FIG. 2 is a timing chart showing an example of operation in the PWM mode. In order from the top, the clock signal CLK, the slope voltage SLP, the error voltage ERR, the comparison signal S0, the PWM pulse S1a (output signal S2), and the switch voltage Vsw And the coil current IL is depicted.

  When the load is heavy (the output current Io is large), the power supply device 1 is in the PWM mode. In the PWM mode, the PWM pulse S1a is selected as the output signal S2 of the selector 114, and the driver 102 turns on / off the output transistor 101 in accordance with the pulse signal S2. During the ON period of the output transistor 101, the switch voltage Vsw becomes a high level (almost the input voltage Vi), and the coil current IL increases. On the other hand, during the off period of the output transistor 101, the switch voltage Vsw is at a low level (almost the ground voltage GND), and the coil current IL decreases.

  As described above, the PWM pulse S1a becomes a high level triggered by the rising edge of the clock signal CLK, and becomes a low level triggered by the rising edge of the comparison signal S0. The clock signal CLK becomes high level at a constant switching cycle TPWM, and the comparison signal S0 becomes high level when the error voltage ERR becomes lower than the slope voltage SLP. Accordingly, the on-duty of the output transistor 101 (the ratio of the high level period of the PWM pulse S1a to the switching cycle TPWM) becomes shorter as the error voltage ERR is lower, and becomes longer as the error voltage ERR is higher.

  In the PWM mode in which the on / off control of the output transistor 101 is performed according to the PWM pulse S1a as described above, the output feedback control is performed so that the feedback voltage Vfb matches the reference voltage Vref, and the output voltage Vo is set to a desired target value. Maintained.

<On-time fixed mode (light load mode)>
FIG. 3 is a timing chart showing an operation example of the fixed on-time mode. From the top, the clock signal CLK, the slope voltage SLP, the error voltage ERR, the comparison signal S0, the on-time fixed pulse S1b (output signal S2), and the switch The voltage Vsw and the coil current IL are depicted.

  When the load is light (the output current Io is small), the power supply device 1 switches from the PWM mode to the on-time fixed mode in order to suppress the internal current consumption Icc at the time of light load. In the fixed on-time mode, the fixed on-time pulse S1b is selected as the output signal S2 of the selector 114, and the driver 102 turns on / off the output transistor 101 in accordance with the pulse signal S2.

  When a pulse edge (for example, a falling edge) of the comparison signal S0 is detected, the on-time fixed pulse generation unit 111 generates an on-time fixed pulse S1b having a constant on-time ton and the number of on-times N, and then compares them. The generation of the on-time fixed pulse S1b is stopped until the pulse edge of the signal S0 is detected. That is, the on-time fixed pulse generator 111 generates the on-time fixed pulse S1b every time the charge Q supplied to the coil L1 is all consumed as the output current Io to the load.

  As described above, in the fixed on-time mode, the switching control circuit 100 generates the on-time fixed pulse S1b and turns on / off the output transistor 101 to turn on and off the output transistor 101, and the on-time fixed mode. The output voltage Vo is generated from the input voltage Vi by alternately repeating the stationary period Toff in which the generation of the pulse S1b is stopped.

  When the current value of the internal consumption current Icc in the operation period Ton is Ion and the current value of the internal consumption current Icc in the quiescent period Toff is Ioff (<Ion), the period T (= Ton + Toff) of the on-time fixed pulse S1b. The average value of the internal current consumption Icc can be calculated by the following equation (2).

  In the above formula (2), when Ion, Ioff, and Ton are fixed, the smaller the ratio of the operation period Ton in the period T, the smaller the internal consumption current Icc, and conversely, the operation period Ton in the period T The larger the ratio, the larger the internal consumption current Icc.

  In this fixed on-time mode, the charge Q is supplied to the load every time the transistor 101 is turned on. Therefore, when the transistor 101 is turned on N times, the total amount of charge supplied to the load is (N × Q). It becomes.

  Further, when the inductance of the coil L1 is L, the on-time of the on-time fixed pulse S1b is ton, and the off-time is toff, the peak value ILp of the coil current IL can be expressed by the following equation (3a). . Therefore, the charge Q supplied to the load every time the transistor 101 is turned on can be calculated by the following equation (3b).

  As can be seen from the above equation (3b), since the charge Q is proportional to the square of the on-time ton, if the on-time ton is fixed, the charge Q supplied to the load is determined and the period T is determined. In summary, the following equation (4) is established between the period T and the charge Q.

  From the above equation (4), the period T of the on-time fixed pulse S1b becomes longer as the on-time ton or the on-times N is set larger. Therefore, by appropriately setting the ON time ton or the ON count N, it is possible to reduce the ratio of the operation period Ton to the period T and reduce the internal current consumption Icc.

<Mode switching operation>
FIG. 4 is a diagram showing how the behavior of the switch voltage Vsw changes according to the load, and it is assumed that the load decreases from the left to the right.

  In a state where the power supply device 1 is driven in the PWM mode (when the power supply device 1 is activated or in a heavy load state), the behavior of the switch voltage Vsw generally starts with the continuous mode (A) when the load is reduced. To the discontinuous mode (B). However, the switching period Ta in the continuous mode (A) and the period Tb in the discontinuous mode (B) are both maintained at the switching period TPWM (= period of the clock signal CLK) determined inside the semiconductor device 10. Yes.

  When the load is further reduced, the PWM pulse S1a is lost and the switching cycle TPWM cannot be maintained, and the behavior of the switch voltage Vsw shifts to the intermittent oscillation mode (C) (Tc> TPWM). . At this time, the operation mode of the power supply device 1 is switched from the PWM mode to the on-time fixed mode (D) according to a load determination operation described later.

  As described above, the switching period Td (corresponding to the period T in FIG. 3) in the fixed on-time mode is designed to be sufficiently larger than the switching period TPWM in the PWM mode at light load. The generation operation of the fixed on-time pulse S1b is turned off for at least one switching cycle TPWM after N pulses are generated. As described above, the main feature of the fixed on-time mode is that the operation period Ton for generating the fixed on-time pulse S1b and the stationary period Toff for stopping the generation of the fixed on-time pulse S1b are alternately repeated, so Is to improve the power efficiency ξ at light load by reducing the internal current consumption Icc (average value).

  As shown in FIG. 5, when the transistor 101 is turned on once in the PWM mode, the charge supplied to the load is Q1, and the minimum on time (minimum pulse width) of the PWM pulse S1a is tmin. The threshold current Ith1 at the time of switching to the fixed on-time mode can be generally obtained from the following equation (5).

  The switching from the fixed on-time mode to the PWM mode can be understood in the same manner as described above. As shown in FIG. 6, when the transistor 101 is turned on N times in the fixed on-time mode, the charge supplied to the load is Q2, and when the on-period for each on-time fixed pulse S1b is ton, The threshold current Ith2 when switching from the fixed time mode to the PWM mode can be generally obtained from the following equation (6).

  The switching load point (threshold currents Ith1, Ith2) is extremely important. Usually, since tmin <ton, Ith1 <Ith2. This is schematically shown in FIG. The upper part of FIG. 7 shows the threshold current Ith1 when shifting from the PWM mode to the fixed on-time mode. The lower part of FIG. 7 shows the threshold current Ith2 when shifting from the fixed on-time mode to the PWM mode.

  In the fixed on-time mode, since the on-time ton and the number of on-times N are fixed, it is easy to design the threshold current Ith2, and it is easy to adjust the power efficiency ξ at an ultralight load. However, if the on-time ton and the number of on-times N are set large in order to increase the power efficiency ξ in a light load state, a deviation occurs between the threshold current Ith1 and the threshold current Ith2, as shown in FIG. Depending on the application of the power supply device 1, this hysteresis may be a problem.

  Therefore, the power supply device 1 of the present configuration example has a configuration in which the operation mode can be switched without being affected by hysteresis and the switching load point can be changed by the user.

  More specifically, in order to realize the above-described mode switching operation, the power supply device 1 of this configuration example has the configuration shown in FIG. In FIG. 8, the switching element 101, the driver 102, the PWM pulse generator 110, the on-time fixed pulse generator 111, the selector 114, the external terminal T3, the external terminal T4, and the input / output stage (coil L1, diode) from the configuration of FIG. FIG. 6 is a circuit block diagram showing a configuration in which D1, a capacitor C1, and a capacitor C2) are extracted and a comparator 601, a comparator 602, a resistor 603, an external terminal TP, and an external terminal TN of this configuration example are further added.

  The non-inverting input terminal (+) of the comparator 601 is connected to the positive terminal of the constant voltage source, and a predetermined threshold voltage Vth61 is applied (however, based on the output voltage Vo). The inverting input terminal (−) of the comparator 601 is connected to the external terminal TP. The output terminal of the comparator 601 is connected to the driver 102.

  The non-inverting input terminal (+) of the comparator 602 is connected to the positive terminal of the constant voltage source, and a predetermined threshold voltage Vth62 is applied (however, based on the output voltage Vo). The inverting input terminal (−) of the comparator 602 is connected to the external terminal TP. The output terminal of the comparator 602 is connected to the selector 114.

  A first end of the resistor 603 is connected to a second end of the coil L1. A second end of the resistor 603 is connected to an application end of the output voltage Vo. The external terminal TP is connected to a connection node between the second end of the coil L1 and the first end of the resistor 603. The external terminal TN is connected to a connection node between the second end of the resistor 603 and the application end of the output voltage Vo. The external terminal TN is connected to the negative terminal of the constant voltage source of the comparator 601 and the comparator 602.

  Next, the operation of the power supply device 1 having the above configuration will be described. The comparator 601 monitors the current IL flowing through the coil L1 by comparing a potential difference (hereinafter referred to as “voltage V603” (referred to as output voltage Vo reference)) between both ends of the resistor 603 with a predetermined threshold voltage Vth61. Functions as an overcurrent detection circuit.

  The comparator 601 compares the voltage V603 with a predetermined threshold voltage Vth61, and determines the logic level of the output signal S61 (= overcurrent detection signal) based on the comparison result. The output signal S61 is at a high level (normal logic level) when the voltage V603 is lower than the threshold voltage Vth61, and is at a low level (logic level when abnormal) when the voltage V603 is higher than the threshold voltage Vth61. The When the output signal S61 becomes low level, the driver 102 is stopped because the output current Io is in an overcurrent state.

  The comparator 602 compares the voltage V603 with a predetermined threshold voltage Vth62 (<< threshold voltage Vth61), and determines the logic level of the selector control signal S62 (= operation control signal) based on the comparison result. The output signal S62 is at a high level when the voltage V603 is lower than the threshold voltage Vth62, and is at a low level when the voltage V603 is higher than the threshold voltage Vth62.

  Based on the logic level of the selector control signal S62 input from the comparator 602, the selector 114 of this configuration example selects either the PWM pulse S1a or the on-time fixed pulse S1b as the output signal S2.

  When the selector control signal S62 is at a high level, it can be seen that the output current Io is small (light load), so the output signal S1b from the on-time fixed pulse generator 111 is output as the output signal S2. That is, the operation is performed in the low load mode. On the other hand, when the selector control signal S62 is at a low level, it can be seen that the output current Io is large (heavy load), so the output signal S1a from the PWM pulse generator 110 is output as the output signal S2. That is, the operation is performed in the PWM mode.

  When such a configuration is adopted, a switching load point (threshold current Ith3) between the fixed on-time mode and the PWM mode is obtained by the following equation (7).

  The switching of the operation mode performed by the configuration described above will be described with reference to the schematic diagram of FIG. As shown in FIG. 9, according to this configuration example, the operation mode is switched based on the comparison result of the comparator 602. For this reason, the switching load point from the fixed on-time mode to the PWM mode coincides with the switching load point from the fixed on-time mode to the PWM mode, and has no hysteresis (range indicated by γ in FIG. 9). Therefore, it can be used for applications that dislike hysteresis.

  Further, according to the present configuration example, the threshold voltage Ith3 changes according to the resistance value of the resistor 603 because the threshold voltage Vth62 is a fixed value as shown in the equation (7). Therefore, the user can change the switching load point described above by exchanging the resistor 603 connected to the outside of the semiconductor device 10. Thus, for example, the switching load point can be adjusted according to whether the user gives priority to the fixed on-time mode or the heavy load mode.

  In this configuration example, in the configuration in which the operation mode is switched by comparing the voltage V603 generated in the resistor 603 with the predetermined threshold voltage Vth62, a minute voltage generated in the overcurrent detection resistor 603 is appropriately set. A device for detection is important.

<Vehicle>
FIG. 10 is an external view showing a configuration example of a vehicle on which the power supply device 1 is mounted. The vehicle X of this configuration example includes onboard devices X11 to X17 and a battery (not shown in FIG. 10) that supplies power to these onboard devices X11 to X17.

  The in-vehicle device X11 is an engine control unit that performs control related to the engine (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto cruise control).

  The in-vehicle device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The in-vehicle device X13 is a transmission control unit that performs control related to the transmission.

  The in-vehicle device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power Steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The in-vehicle device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The in-vehicle device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment item or a manufacturer option product such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, and an air conditioner.

  The in-vehicle device X17 is an electronic device that is arbitrarily attached to the vehicle X by the user, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [Electronic Toll Collection System].

  The power supply device 1 described above can be incorporated in any of the in-vehicle devices X11 to X17.

<Other variations>
The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be applied to, for example, an in-vehicle system power supply IC. However, the application target of the present invention is not limited to this, and can be widely applied to semiconductor devices used for other purposes.

DESCRIPTION OF SYMBOLS 1 Power supply device 10 Semiconductor device 100 Switching control circuit 101 Output transistor (P channel type MOS field effect transistor)
102 Driver (Inverter)
103 Low level voltage generator 104 Feedback voltage generator Ra, Rb Resistor 105 Soft start voltage generator 105a Current source 105b N-channel MOS field effect transistor 105c Comparator 106 Error amplifier 107 Oscillator 108 Slope voltage generator 109 Comparator 110 PWM pulse generation Unit 111 On-time fixed pulse generator 112 One-shot pulse generator 113 Selector controller (counter)
114 Selector 115 Comparator 116 Comparator 117 OR Gate 118 N-channel MOS Field Effect Transistor 119 On-Time Fixed Pulse Adjustment Unit 120 On-Time Fixed Pulse Invalid Unit (Comparator)
121 NOR gate 122 Counter adjustment unit 200 Internal power supply voltage generation circuit 201 N channel type MOS field effect transistor 202 Operational amplifier 203 Preregulator unit 204 Reference voltage generation unit 205, 206 Resistor 300 Power supply switching circuit 301, 302 Switch (P channel type MOS electric field) Effect transistor)
303 Inverters 601, 602 Comparator 603 Resistor L1 Coil D1 Diode R1-R4 Resistor C1-C6 Capacitor T1-T14 External terminal TP, TN External terminal X Vehicle X11-X17 In-vehicle device

Claims (10)

A switching element that is turned on / off to generate an output voltage from the input voltage;
A control circuit that performs on / off control of the switching element at a predetermined period;
A resistance voltage generated between both ends of the resistor provided in the output path of the output voltage is compared with a predetermined threshold voltage, and an operation control signal for determining an operation method of the control circuit is generated according to the comparison result A comparator to
A power supply device comprising: The control circuit determines in accordance with the operation control signal whether to operate in a heavy load mode that prioritizes output stability or a light load mode that prioritizes reduction of internal current consumption. The power supply device according to claim 1. The control circuit operates in the light load mode when the resistance voltage falls below a predetermined threshold voltage, and operates in the heavy load mode when the resistance voltage exceeds a predetermined threshold voltage. Item 3. The power supply device according to Item 2. The resistor is an overcurrent detection resistor that detects an overcurrent according to a potential difference generated at both ends of the resistor, and is also connected to an overcurrent detection circuit included in the power supply device. The power supply device described in 1. The control circuit includes:
A first pulse signal generator for generating a first pulse signal;
A second pulse signal generator for generating a second pulse signal;
The power supply device according to claim 4, further comprising: a selector that supplies either the first pulse signal or the second pulse signal to the switching element in accordance with the control signal. The first pulse signal is a PWM (pulse width modulation) signal whose on-time is changed by output feedback control,
The power supply device according to claim 5, wherein the second pulse signal is an on-time fixed pulse in which an on-time and the number of on-times are constant. The power supply device includes a coil connected between the switching element and an output voltage application end, a rectifier element connected between a first end of the coil and a ground end, and a second of the coil. The power supply device according to claim 6, further comprising: a capacitor connected between the end and the ground end.   The power supply device according to claim 7, wherein the resistor is connected between a second end of the coil and an application end of the output voltage. An in-vehicle device comprising the power supply device according to claim 1. In-vehicle device according to claim 9,
A battery for supplying power to the in-vehicle device;
The vehicle characterized by having.

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