JP6329047B2 - Current mode controlled switching power supply - Google Patents

Description

  The present invention relates to a current mode control type switching power supply capable of performing a step-down operation for stepping down an input voltage.

  Switching power supply control methods can be broadly divided into voltage mode control and current mode control. In general, the current mode control is an extremely effective control method in terms of simplifying phase compensation, high-speed response, and reducing the number of external parts. A conventional example of a current mode control type switching power supply is shown in FIG.

JP 2010-220355 A

The switching power supply device 100 shown in FIG. 14 performs current mode control by detecting a current flowing through an upper MOS [metal oxide semiconductor] transistor Q1. According to the current mode control, the upper MOS transistor Q1 and the lower MOS transistor Q2 are turned on / off in a complementary manner, and the input voltage V _IN is converted into a pulsed switch voltage V _SW by this switching operation. Then, the switch voltage V _SW is smoothed by the inductor L1 and the output capacitor C1, and converted to an output voltage V _OUT lower than the input voltage V _IN .

When the current mode control is executed by detecting the current flowing through the upper MOS transistor Q1, the current feedback portion corresponds to the difference (V _IN −V _SW ) between the input voltage and the switch voltage, so that the current detection circuit has the input voltage V _{If the} detected current information is generated as the _IN reference and is transmitted to the slope circuit that generates the slope voltage V _{SLP based} on the internal power supply voltage, the current information is supplied to the slope voltage V _SLP after the upper MOS transistor Q1 is turned on. As shown in FIG. 15, there is a delay time D until the signal is transmitted.

In addition, since the current feedback portion corresponds to the difference between the input voltage and the switch voltage (V _IN −V _SW ), if noise occurs at the rise of the switch voltage V _SW , the noise is transmitted as it is and the slope voltage V _SLP It will be reflected in.

When the pulse width of the switch voltage V _SW becomes narrow, the above delay time and noise become dominant, causing a problem that current feedback cannot be performed.

  Note that the current mode control type switching power supply device disclosed in Patent Document 1 also detects the current flowing through the upper switching element and executes the current mode control similarly to the switching power supply device 100 shown in FIG. Have similar problems.

  In view of the above situation, the present invention provides a current mode control type switching power supply device capable of current feedback even when the ratio of the output voltage to the input voltage is small and the current feedback does not depend on the input voltage and the output current. The purpose is to do.

<First technical features>
Among the current mode control type switching power supply devices disclosed in this specification, the current mode control type switching power supply device having the first technical feature has a first end connected to an input voltage application end. A first switch, a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a voltage lower than the input voltage, and flowing through the second switch A current detection unit that detects a current; and a control unit that controls the first switch and the second switch according to the current detected by the current detection unit, wherein the control unit includes the first switch A slope voltage generator for accumulating information on the current detected by the current detector during a predetermined period during the off state, and generating a slope voltage based on the accumulated current information; A structure (1-1 configuration) for controlling said first switch and said second switch in response to.

  Further, in the current mode control type switching power supply device having the above-described configuration 1-1, the current detection unit is a voltage-current conversion circuit that converts a voltage corresponding to a current flowing through the second switch into a current, and the slope The voltage generator may be configured to have a capacitor (1-2 configuration) for charging the output current of the voltage-current converter.

  Further, in the current mode control type switching power supply having the above-described configuration 1-2, the slope voltage generator further includes a charging switch for conducting / cutting off a current path from the output terminal of the voltage-current conversion circuit to the capacitor. It is good to make it the structure which has (1-3 structure).

  Further, in the current mode control type switching power supply device having the above configuration 1-2 or 1-3, the slope voltage generator includes a reset unit that discharges the capacitor and resets a charging voltage of the capacitor ( (1-4 configuration).

  Moreover, in the current mode control type switching power supply device having any one of the first to first to fourth configurations, the control unit is configured to output a voltage corresponding to an output voltage of the current mode control type switching power supply device and a reference voltage. An error amplifier that generates an error signal according to the difference, a comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal, and an oscillator that generates a set signal that is a clock signal of a predetermined frequency; And a timing control circuit that controls on / off of the first switch and on / off of the second switch in accordance with the set signal and the reset signal (configuration 1-5). .

  Further, in the current mode control type switching power supply device having any one of the first to first to fifth configurations, the second switch is a MOS transistor, and the current detection unit is a voltage across the on-resistance of the MOS transistor. It is preferable to use a configuration for detecting the current flowing through the second switch (1-6 configuration).

  Of the in-vehicle devices disclosed in the present specification, the in-vehicle device having the first technical feature is a current mode control type switching power supply device having any one of the first to first to sixth configurations. (1-7 configuration).

  Of the vehicles disclosed in the present specification, a vehicle having the first technical feature includes an in-vehicle device having the first to seventh configuration and a battery for supplying electric power to the in-vehicle device. (Structure 1-8).

<Second technical feature>
Among the current mode control type switching power supply devices disclosed in this specification, the current mode control type switching power supply device having the second technical feature has a first end connected to an input voltage application end. A first switch, a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a voltage lower than the input voltage, and flowing through the second switch A current detection unit that detects a current; and a control unit that controls the first switch and the second switch according to the current detected by the current detection unit, wherein the control unit includes the first switch An accumulation unit that accumulates information on the current detected by the current detection unit during a predetermined period during the off state, and transmission of current information accumulated by the accumulation unit before the first switch is switched from OFF to ON. And a reflecting unit that reflects the information of the current accumulated by the accumulating unit on the slope voltage, and controls the first switch and the second switch according to the slope voltage (second -1 configuration).

  In the current mode control type switching power supply having the above-described configuration 2-1, the storage unit and the reflection unit may be configured to be circuits driven by the same power supply voltage (configuration 2-1).

  Further, in the current mode control type switching power supply having the above-described configuration 2-1 or 2-2, the current detection unit is a voltage-current conversion circuit that converts a voltage corresponding to a current flowing through the second switch into a current. The storage unit includes a capacitor that charges the output current of the voltage-current conversion circuit, and the reflection unit reflects the charging voltage of the capacitor in the slope voltage (configuration 2-3). It is good to.

  Further, in the current mode control type switching power supply device having the above configuration 2-3, the storage section further includes a charging switch for conducting / cutting off a current path from the output terminal of the voltage-current conversion circuit to the capacitor. (Configuration 2-4) may be used.

  Further, in the current mode control type switching power supply having the above-described configuration 2-4, the storage unit turns off the charging switch at the end of the dead time provided immediately after the first switch is switched from on to off. The charging switch may be switched from on to off at the start of a dead time provided immediately after the second switch is switched from on to off (second to fifth configuration).

  Further, in the current mode control type switching power supply device having any one of the above configurations 2-3 to 2-5, the storage unit includes a reset unit that discharges the capacitor and resets a charging voltage of the capacitor ( It is preferable to use the 2-6th configuration.

  Further, in the current mode control type switching power supply device having any one of the above configurations 2-1 to 2-6, the control unit is configured to obtain a voltage according to an output voltage of the current mode control type switching power supply device and a reference voltage. An error amplifier that generates an error signal according to the difference, a comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal, and an oscillator that generates a set signal that is a clock signal of a predetermined frequency; And a timing control circuit that controls on / off of the first switch and on / off of the second switch in accordance with the set signal and the reset signal (configuration 2-7). .

  Further, in the current mode control type switching power supply device having any one of the above-mentioned configurations 2-1 to 2-7, the second switch is a MOS transistor, and the current detector is a voltage across the on-resistance of the MOS transistor. It is preferable to use a configuration for detecting the current flowing through the second switch (configuration 2-8).

  Of the in-vehicle devices disclosed in this specification, the in-vehicle device having the second technical feature is a current mode control type switching power supply device having any one of the configurations of 2-1 to 2-8. (Configuration 2-9).

  Of the vehicles disclosed in the present specification, a vehicle having the second technical feature includes an in-vehicle device having a configuration 2-9 and a battery for supplying electric power to the in-vehicle device. (Structure 2-10).

<Third technical features>
Among the current mode control type switching power supply devices disclosed in this specification, the current mode control type switching power supply device having the third technical feature has a first end connected to an input voltage application end. A first switch, a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a voltage lower than the input voltage, and flowing through the second switch A current detection unit that detects a current; and a control unit that controls the first switch and the second switch according to the current detected by the current detection unit, wherein the control unit includes the first switch An accumulation unit that accumulates information on the current detected by the current detection unit in a certain period of time during the off state; and a reflection unit that reflects the information on the current accumulated by the accumulation unit in a slope voltage. ,Previous A structure (3-1 arrangement) for controlling said first switch and said second switch in accordance with the slope voltage.

  Further, in the current mode control type switching power supply device having the above configuration 3-1, the control unit outputs an error signal corresponding to a difference between a voltage corresponding to the output voltage of the current mode control type switching power supply device and a reference voltage. An error amplifier to be generated; a comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal; an oscillator that generates a set signal that is a clock signal of a predetermined frequency; and the set signal and the reset A timing control circuit that controls on / off of the first switch and on / off of the second switch according to a signal, and the predetermined time is provided within a high level period of the set signal ( It is preferable to use the configuration 3-2.

  In the current mode control type switching power supply having the above configuration 3-2, the timing control circuit turns on the first switch when the set signal is switched from a high level to a low level, and the reset signal The first switch is turned off when switching from a low level to a high level, and when the set signal is switched from a low level to a high level, the first signal is forcibly set regardless of the level transition state of the reset signal. It may be configured to turn off one switch and turn on the second switch (configuration 3-3).

  Further, in the current mode control type switching power supply device having any one of the above configurations 3-1 to 3-3, the storage unit and the reflection unit are circuits driven by the same power supply voltage (3-4). (Configuration).

  Further, in the current mode control type switching power supply device having any one of the above-described configurations 3-1 to 3-4, the current detection unit converts a voltage corresponding to a current flowing through the second switch into a current. The storage unit includes a capacitor that charges the output current of the voltage-current conversion circuit, and the reflection unit reflects the charging voltage of the capacitor in the slope voltage (third to fifth) Configuration).

  Further, in the current mode control type switching power supply device having the above configuration 3-5, the storage section further includes a charging switch for conducting / cutting off a current path from the output terminal of the voltage-current conversion circuit to the capacitor. (Configuration 3-6) may be used.

  Further, in the current mode control type switching power supply device of the above configuration 3-5 or 3-6, the storage unit includes a reset unit that discharges the capacitor and resets the charging voltage of the capacitor (third) -7)).

  Further, in the current mode control type switching power supply device having any one of the above-described configurations 3-1 to 3-7, the reflection unit may be configured to store the current accumulated by the accumulation unit before the first switch is switched from OFF to ON. It is preferable to adopt a configuration (third to eighth configuration) in which transmission of information is started and current information accumulated by the accumulation unit is reflected in the slope voltage.

  Further, in the current mode control type switching power supply device having any one of the above configurations 3-1 to 3-8, the second switch is a MOS transistor, and the current detection unit is a voltage across the on-resistance of the MOS transistor. It is preferable to use a configuration for detecting the current flowing through the second switch (configuration 3-9).

  In addition, among the in-vehicle devices disclosed in this specification, the in-vehicle device having the third technical feature is a current mode control type switching power supply device having any one of the configurations of 3-1 to 3-9. (Configuration 3-10).

  Of the vehicles disclosed in this specification, a vehicle having a third technical feature includes an in-vehicle device having a configuration of 3-10 and a battery for supplying electric power to the in-vehicle device. (Configuration 3-11).

<Fourth technical feature>
Among the current mode control type switching power supply devices disclosed in this specification, the current mode control type switching power supply device having the fourth technical feature has a first end connected to an input voltage application end. A first switch, a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a voltage lower than the input voltage, and flowing through the second switch A current detection unit that detects current; and a control unit that controls the first switch and the second switch, and the control unit has a ratio of the output voltage to the input voltage equal to or lower than a predetermined value. The first switch and the second switch are controlled according to the current detected by the current detection unit, and when the ratio of the output voltage to the input voltage is not less than the predetermined value, the current detection unit A structure (4-1 arrangement) for controlling said first switch and said second switch independently of the out current.

  Further, in the current mode control type switching power supply having the above-described configuration of 4-1, the current mode control type switching power supply device further includes a first switch current detection unit that detects a current flowing through the first switch, and the control unit outputs an output voltage corresponding to the input voltage When the ratio is not less than or equal to a predetermined value, the first switch and the second switch may be controlled according to the current detected by the first switch current detector (4-2 configuration). .

  Further, in the current mode control type switching power supply having the above-described configuration of (4-1) or (4-2), the control unit is configured to switch the first switch when a ratio of the output voltage to the input voltage is a predetermined value or less. A slope voltage generation unit that accumulates information on the current detected by the current detection unit during a predetermined period while the signal is in an off state, and generates a slope voltage based on the accumulated current information; When the ratio of the output voltage to the voltage is equal to or lower than a predetermined value, the first switch and the second switch are controlled according to the slope voltage (configuration 4-3).

  Further, in the current mode control type switching power supply having the above-mentioned configuration 4-3, the current detection unit is a voltage-current conversion circuit for converting a voltage corresponding to a current flowing through the second switch into a current, and the slope The voltage generation unit may have a configuration (fourth to fourth configuration) having a capacitor that charges the output current of the voltage-current conversion circuit.

  In the current mode control type switching power supply having the above-mentioned configuration 4-4, the slope voltage generator further includes a charging switch for conducting / cutting off a current path from the output terminal of the voltage-current conversion circuit to the capacitor. It is good to have the structure (4-5th structure) to have.

  Further, in the current mode control type switching power supply device having the above configuration 4-4 or 4-5, the slope voltage generation unit has a reset unit that discharges the capacitor and resets the charging voltage of the capacitor ( (4-6th configuration).

  Further, in the current mode control type switching power supply device having any one of the above fourth to fourth to sixth configurations, the control unit generates an error signal corresponding to a difference between a voltage corresponding to the output voltage and a reference voltage. An error amplifier, a comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal, an oscillator that generates a set signal that is a clock signal of a predetermined frequency, the set signal and the reset signal It is preferable to adopt a configuration (fourth to seventh configuration) having a timing control circuit that controls on / off of the first switch and on / off of the second switch according to the above.

  Further, in the current mode control type switching power supply device having any one of the above-described configurations of 4-1 to 4-7, the second switch is a MOS transistor, and the current detection unit is a voltage across the on-resistance of the MOS transistor. It is preferable to use a configuration for detecting the current flowing through the second switch (configuration 4-8).

  Of the in-vehicle devices disclosed in the present specification, the in-vehicle device having the fourth technical feature is a current mode control type switching power supply device having any one of the configurations of 4-1 to 4-8. (4-9th configuration).

  Of the vehicles disclosed in this specification, a vehicle having a fourth technical feature includes a vehicle-mounted device having a configuration of 4-9 and a battery for supplying power to the vehicle-mounted device. (Structure 4-10).

<Fifth technical feature>
Among the current mode control type switching power supply devices disclosed in this specification, the current mode control type switching power supply device having the fifth technical feature has a first end connected to an input voltage application end. A first switch, a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a voltage lower than the input voltage, and flowing through the second switch A current detection unit that detects a current; and a control unit that controls the first switch and the second switch according to the current detected by the current detection unit, wherein the control unit includes the first switch An accumulation unit for accumulating information on the current detected by the current detection unit during a predetermined period during the off state, and a reflection for reflecting the information on the current accumulated by the accumulation unit in the offset voltage of the slope voltage And a slope setting unit for setting the slope of the slope of the slope voltage to a constant value, and controlling the first switch and the second switch in accordance with the slope voltage (first to 5-1 Configuration).

  In the current mode control type switching power supply having the above-mentioned configuration of (5-1), it is preferable that the predetermined period is a fixed time (configuration of (5-2)).

  Further, in the current mode control type switching power supply having the above-described configuration of (5-1) or (5-2), the reflecting unit is configured to store the current information accumulated by the accumulation unit before the first switch is switched from OFF to ON. It is preferable to adopt a configuration (5-3 configuration) in which the information on the current accumulated by the accumulation unit is reflected and reflected on the offset voltage of the slope voltage.

  Further, in the current mode control type switching power supply device having any one of the configurations of the first to fifth-3, the current detection unit converts a voltage corresponding to a current flowing through the second switch into a current. In the circuit, the storage unit and the reflection unit may share a capacitor that charges the output current of the voltage-current conversion circuit (configuration 5-4).

  Further, in the current mode control type switching power supply of the fifth to fourth configuration, the slope setting unit includes a constant current source, and a slope switch for conducting / cutting off a current path from the constant current source to the capacitor, It is good to make it the structure which has (5-5th structure).

  Further, in the current mode control type switching power supply device having the above configuration 5-4 or 5-5, the storage unit is for charging / disconnecting a current path from the output terminal of the voltage-current conversion circuit to the capacitor. A configuration further having a switch (5-6 configuration) is preferable.

  Further, in the current mode control type switching power supply device of any one of the fifth to fourth to sixth configurations, the storage unit includes a reset unit that discharges the capacitor and resets a charging voltage of the capacitor ( (5-7) configuration).

  Further, in the current mode control type switching power supply having any one of the first to fifth to seventh configurations, the control unit generates an error signal corresponding to a difference between a voltage corresponding to the output voltage and a reference voltage. An error amplifier, a comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal, an oscillator that generates a set signal that is a clock signal of a predetermined frequency, the set signal and the reset signal It is preferable to adopt a configuration (5-8 configuration) having a timing control circuit for controlling on / off of the first switch and on / off of the second switch according to the above.

  Further, in the current mode control type switching power supply device having any one of the above-mentioned configurations of 5-1 to 5-8, the second switch is a MOS transistor, and the current detector is a voltage across the on-resistance of the MOS transistor. It is preferable to use a configuration (5-9 configuration) for detecting the current flowing through the second switch.

  In addition, among the in-vehicle devices disclosed in this specification, the in-vehicle device having the fifth technical feature is a current mode control type switching power supply device having any one of the configurations of 5-1 to 5-9. (5-10 configuration).

  Of the vehicles disclosed in this specification, a vehicle having a fifth technical feature includes an in-vehicle device having a configuration of 5-10 and a battery for supplying electric power to the in-vehicle device. (Structure 5-11).

  According to the current mode control type switching power supply device disclosed in this specification, current feedback is possible even when the ratio of the output voltage to the input voltage is small. Further, among the current mode control type switching power supply devices disclosed in this specification, the current mode control type switching power supply device having the fifth technical feature is such that the current feedback depends on the input voltage and the output current. do not do.

The figure which shows the example of whole structure of 1st Embodiment of a switching power supply device. The figure which shows one structural example of a current detection circuit and a slope circuit The figure which shows the example of 1 structure of the voltage-current conversion circuit 4A The figure which shows one structural example of 5 A of voltage-current conversion circuits Timing chart showing an example of operation of a switching power supply Timing chart showing a modification of the operation example shown in FIG. 4A Timing chart showing another operation example of the switching power supply Timing chart showing a modification of the operation example shown in FIG. 5A Timing chart showing still another operation example of the switching power supply device Timing chart showing a modification of the operation example shown in FIG. 6A The figure which shows the rough waveform of the slope voltage which reflected current information on the slope of the slope The figure which shows the rough waveform of the slope voltage which reflected current information in the offset voltage of the slope The figure which shows the other structural example of a current detection circuit and a slope circuit Timing chart showing still another operation example of the switching power supply device The figure which shows the example of whole structure of 2nd Embodiment of a switching power supply device. Timing chart showing an example of judgment on the ratio of output voltage to input voltage Timing chart showing another example of judgment regarding ratio of output voltage to input voltage External view showing an example of the configuration of a vehicle equipped with in-vehicle equipment The figure which shows the prior art example of a current mode control type switching power supply device Timing chart showing an operation example of a conventional switching power supply device

<Overall configuration (first embodiment)>
FIG. 1 is a diagram illustrating an overall configuration example of a first embodiment of a current mode control type switching power supply device. The switching power supply device 101 of this configuration example is a current mode control type switching power supply device that performs a step-down operation for stepping down an input voltage, and includes a timing control circuit 1, an upper MOS transistor Q1, a lower MOS transistor Q2, and an inductor. L1, an output capacitor C1, voltage dividing resistors R1 and R2, an error amplifier 2, a reference voltage source 3, a current detection circuit 4, a slope circuit 5, a comparator 6, and an oscillator 7 are provided.

  The timing control circuit 1 controls on / off of the upper MOS transistor Q1 and on / off of the lower MOS transistor Q2, and the gate signal G1 and lower MOS of the upper MOS transistor Q1 according to the set signal SET and the reset signal RESET. A gate signal G2 of the transistor Q2 is generated.

The upper MOS transistor Q1 is an N-channel MOS transistor, and is an example of an upper switch that conducts / cuts off a current path from the input voltage application terminal to which the input voltage V _IN is applied to the inductor L1. The drain of the upper MOS transistor Q1 is connected to the input voltage application terminal to which the input voltage V _IN is applied. The source of the upper MOS transistor Q1 is connected to one end of the inductor and the drain of the lower MOS transistor Q2. A gate signal G1 is supplied from the timing control circuit 1 to the gate of the upper MOS transistor Q1. The upper MOS transistor Q1 is turned on when the gate signal G1 is at a high level, and is turned off when the gate signal G1 is at a low level.

  The lower MOS transistor Q2 is an N-channel MOS transistor, and is an example of a lower switch that conducts / cuts off a current path from the ground terminal to the inductor L1. As described above, the drain of the lower MOS transistor Q2 is connected to one end of the inductor and the source of the upper MOS transistor Q1. The source of the lower MOS transistor Q2 is connected to the ground terminal. A gate signal G2 is supplied from the timing control circuit 1 to the gate of the lower MOS transistor Q2. The lower MOS transistor Q2 is turned on when the gate signal G2 is at a high level, and turned off when the gate signal G2 is at a low level. A diode can be used as the lower switch instead of the lower MOS transistor Q2. In this case, a sense resistor connected in series with the diode is provided, and the current detection circuit 4 detects the voltage across the sense resistor. There is a need to.

The upper MOS transistor Q1 and the lower MOS transistor Q2 are complementarily turned on / off under the control of the timing control circuit 1. As a result, a pulsed switch voltage V _SW is generated at the connection node between the upper MOS transistor Q1 and the lower MOS transistor Q2. It is preferable to provide a dead time when both the upper MOS transistor Q1 and the lower MOS transistor Q2 are turned off when the upper MOS transistor Q1 and the lower MOS transistor Q2 are switched on / off.

The inductor L1 and the output capacitor C1, a pulsed switch voltage V _SW smoothes and generates the output voltage V _OUT, supplies its output voltage V _OUT to an application terminal of the output voltage V _OUT.

The voltage dividing resistors R1 and R2 divide the output voltage V _OUT to generate a feedback voltage V _FB .

The error amplifier 2 generates an error signal V _ERR corresponding to the difference between the feedback voltage V _FB and the reference voltage output from the reference voltage source 3.

  The current detection circuit 4 detects the current flowing through the lower MOS transistor Q2 based on the drain-source voltage when the lower MOS transistor Q2 is on, that is, the voltage across the ON resistance of the lower MOS transistor Q2.

  The slope circuit 5 generates and outputs a slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the current detection circuit 4.

Comparator 6 generates a reset signal RESET is a comparison signal by comparing the output voltage of the slope circuit 5 and the error signal V _ERR. Since the slope voltage V _SLP generated by the slope circuit 5 has a fixed period, the reset signal RESET is a PWM [pulse width modulation] signal.

  The oscillator 7 generates a set signal SET that is a clock signal having a predetermined frequency.

<First generation example of slope voltage>
FIG. 2 is a diagram illustrating a configuration example of the current detection circuit 4 and the slope circuit 5. In the example shown in FIG. 2, the current detection circuit 4 is constituted by a voltage-current conversion circuit 4A. In the example shown in FIG. 2, the slope circuit 5 includes switches S1 to S3, capacitors C2 and C3, and a voltage-current conversion circuit 5A.

Each of the voltage-current conversion circuits 4A and 5A is an IC [1] including a timing control circuit 1, an error amplifier 2, a reference voltage source 3, a current detection circuit 4, a slope circuit 5, a comparator 6, and an oscillator 7. integrated circuit] is a circuit driven by an internal power supply voltage V _CC generated inside.

  The voltage-current conversion circuit 4A converts the drain-source voltage of the lower MOS transistor Q2 into a current and outputs the current. When the switch S1 is on, the capacitor C2 is charged by the output current of the voltage / current conversion circuit 4A. On the other hand, when the switch S2 is on, the capacitor C2 is discharged.

The voltage-current conversion circuit 5A converts the charging voltage V _CRG of the capacitor C2 into a current and outputs it. The capacitor C3 is charged by the output current of the voltage-current conversion circuit 5A. On the other hand, when the switch S3 is on, the capacitor C3 is discharged. The charging voltage of the capacitor C3 becomes the slope voltage V _SLP .

  FIG. 3A and FIG. 3B are diagrams showing an example of the configuration of each of the voltage / current conversion circuits 4A and 5A. In the voltage-current conversion circuit shown in FIG. 3A, the current source 8 supplies current to a current mirror circuit composed of N-channel MOS transistors Q3 and Q4. If the mirror ratio of the current mirror circuit composed of the N-channel MOS transistors Q3 and Q4 is 1: 1, the current flowing through the resistor R4 is the difference between the resistance value r3 of the resistor R3 and the resistance value r4 of the resistor R4 ( It is a value divided by r3-r4). A current corresponding to the current flowing through the resistor R4 (current corresponding to the switch voltage Vsw, which is the input voltage of the voltage-current conversion circuit 4A) is converted into a voltage-current conversion circuit by a current mirror circuit composed of the P-channel MOS transistors Q5 and Q6. Swept out as 4A output current. In the voltage-current converter circuit shown in FIG. 3B, a current corresponding to the input voltage of the voltage-current converter circuit flows through the resistor R5 by the series circuit of the resistor R5 and the PNP transistor Q7, and the voltage-current converter is connected to the connection node of the resistor R5 and the PNP transistor Q7. A voltage corresponding to the input voltage of the circuit is generated. Furthermore, a current corresponding to the connection node voltage of the resistor R5 and the PNP transistor Q7 (voltage corresponding to the input voltage of the voltage-current conversion circuit) flows through the resistor R6 by the series circuit of the NPN transistor Q8 and the resistor R6. Then, a current corresponding to the current flowing through the resistor R6 (current corresponding to the input voltage V of the voltage-current conversion circuit 5A) is output as the output current of the voltage-current conversion circuit by the current mirror circuit composed of the P-channel MOS transistors Q9 and Q10. Swept out.

  FIG. 4A is a timing chart showing an operation example of the switching power supply apparatus 101.

  In the example shown in FIG. 4A, the timing control circuit 1 switches the gate signal G1 from the low level to the high level when the set signal SET switches from the low level to the high level, and switches the reset signal RESET from the low level to the high level. Sometimes the gate signal G1 is switched from high level to low level. The slope circuit 5 switches on / off of the switches S <b> 1 to S <b> 3 in accordance with an instruction from the timing control circuit 1.

When the reset signal RESET is switched from the low level to the high level (at timing t11), the slope circuit 5 maintains the switch S1 in the off state, switches the switch S2 from the off state to the on state, and switches the switch S3 in the off state. Switch from on to off. As a result, the capacitors C2 and C3 are discharged, and the charging voltage V _CRG and the slope voltage V _SLP of the capacitor C2 become 0, respectively.

  Then, after the slope circuit 5 switches the switch S2 from the on state to the off state and finishes discharging the capacitor C2, the slope circuit 5 switches the switch S1 from the off state to the on state at the timing t12. The timing of t12 can be, for example, at the end of the dead time provided immediately after the upper MOS transistor Q1 is switched from on to off.

  Next, at the timing t13, the slope circuit 5 switches the switch S1 from the on state to the off state. The timing of t13 can be, for example, at the start of a dead time provided immediately after the lower MOS transistor Q2 is switched from on to off.

Since the switch S1 conducts the current path from the voltage-current conversion circuit 4A to the capacitor C2 during the period from the timing t12 to the timing t13, information on the current flowing through the lower MOS transistor Q2 is accumulated in the form of the charging voltage V _CRG. Is done.

Thereafter, when the set signal SET is switched from the low level to the high level (at timing t14), the slope circuit 5 switches the switch S3 from the on state to the off state. Since the capacitor C3 is charged by the output current of the voltage-current conversion circuit 5A in the period from the timing of t14 to the timing of the next t11 (period in which the upper MOS transistor Q1 is turned on), the timing from t12 to t13 Information on the current flowing through the lower MOS transistor Q2 during the period up to the timing is transmitted and reflected in the slope voltage V _SLP .

According to the switching power supply device 101, the current feedback portion corresponds to the difference (V _SW −GND) between the switch voltage V _SW and the ground voltage. Therefore, as in the present generation example of the slope voltage, since both the current detection circuit 4 and the slope circuit 5 can be operated at an internal power supply voltage V _CC reference, the current information from the current detection circuit 4 to the slope circuit 5 transmits It is possible to shorten the delay time that can occur in the process.

In the present generation example of the slope voltage, since the information of the current flowing through the lower MOS transistor Q2 in the period leading up to the timing of t13 from timing t12 is accumulated in the form of a charging voltage V _CRG, etc. rise of the switch voltage V _SW Even if noise is applied, the noise is averaged over the period from the timing t12 to the timing t13. That is, it is possible to reduce the amount of noise per unit time that is transmitted and reflected on the slope voltage V _SLP .

Therefore, according to this generation example of the slope voltage, current feedback is possible even when the ratio of the output voltage V _OUT to the input voltage V _IN is small (when the pulse width of the switch voltage V _SW is narrow).

In addition, from the viewpoint of stabilizing the control system of the current mode control, a superposition unit is provided in the slope circuit 5, and the superposition unit rises for a period from the timing t14 to the timing t11 with a constant slope. the pseudo slope voltage V _S 'generates, the new slope voltage V _SLP superimposed voltage (new slope voltage V _SLP)' the slope voltage V _SLP it is desirable to output as the output voltage of the slope circuit 5. In this case, as shown in FIG. 4B, when the slope voltage V _SLP ′ exceeds the error signal V _ERR , the reset signal RESET is switched from the low level to the high level.

<Second generation example of slope voltage>
The configurations of the current detection circuit 4 and the slope circuit 5 are the same as those in the above-described first generation example of the slope voltage.

  FIG. 5A is a timing chart showing another operation example of the switching power supply apparatus 101.

  In the example shown in FIG. 5A, the timing control circuit 1 switches the gate signal G1 from the low level to the high level when the set signal SET switches from the high level to the low level, and switches the reset signal RESET from the low level to the high level. Sometimes the gate signal G1 is switched from high level to low level. The slope circuit 5 switches on / off of the switches S <b> 1 to S <b> 3 in accordance with an instruction from the timing control circuit 1.

When the reset signal RESET switches from low level to high level (at timing t21), the slope circuit 5 maintains the switch S1 in the off state, switches the switch S2 from the off state to the on state, and switches the switch S3 in the off state. Switch from on to off. As a result, the capacitors C2 and C3 are discharged, and the charging voltage V _CRG and the slope voltage V _SLP of the capacitor C2 become 0, respectively.

  Then, after the slope circuit 5 switches the switch S2 from the on state to the off state and finishes discharging the capacitor C2, the slope circuit 5 switches the switch S1 from the off state to the on state at the timing t22. The timing of t22 can be set at the end of the dead time provided immediately after the upper MOS transistor Q1 is switched from on to off, for example.

  Next, the slope circuit 5 switches the switch S1 from the on state to the off state at the timing of t23. The timing of t23 can be, for example, at the start of the dead time provided immediately after the lower MOS transistor Q2 is switched from on to off.

Since the switch S1 conducts the current path from the voltage-current conversion circuit 4A to the capacitor C2 during the period from the timing t22 to the timing t23, information on the current flowing through the lower MOS transistor Q2 is accumulated in the form of the charging voltage V _CRG. Is done.

Thereafter, when the set signal SET is switched from the low level to the high level (at the timing t24), the slope circuit 5 switches the switch S3 from the on state to the off state. Since the capacitor C3 is charged by the output current of the voltage-current conversion circuit 5A in the period from the timing t24 to the next timing t21, the lower MOS transistor Q2 flows in the period from the timing t22 to the timing t23. Current information is transmitted and reflected on the slope voltage V _SLP .

In the above-described first generation example of the slope voltage, the upper MOS transistor Q1 is switched from OFF to ON, and at the same time, transmission of information on the current flowing through the lower MOS transistor Q2 is started and reflected in the slope voltage V _SLP . On the other hand, in this generation example of the slope voltage, before the upper MOS transistor Q1 is switched from OFF to ON, transmission of information on the current flowing through the lower MOS transistor Q2 is started and reflected in the slope voltage V _SLP. Yes. Therefore, in this generation example of the slope voltage, the minimum pulse width of the switch voltage V _SW that enables current feedback can be made narrower than that in the first generation example of the slope voltage described above.

In addition, from the viewpoint of stabilizing the control system of the current mode control, a superposition unit is provided in the slope circuit 5, and the superposition unit rises for a period from the timing t24 to the timing t21 with a constant slope. the pseudo slope voltage V _S 'generates, the new slope voltage V _SLP superimposed voltage (new slope voltage V _SLP)' the slope voltage V _SLP it is desirable to output as the output voltage of the slope circuit 5. In this case, as shown in FIG. 5B, when the slope voltage V _SLP ′ exceeds the error signal V _ERR , the reset signal RESET is switched from the low level to the high level.

<Third generation example of slope voltage>
The configurations of the current detection circuit 4 and the slope circuit 5 are the same as those in the first generation example and the second generation example of the slope voltage described above.

  FIG. 6A is a timing chart showing still another operation example of the switching power supply apparatus 101.

  In the example shown in FIG. 6A, the timing control circuit 1 switches the gate signal G1 from the low level to the high level when the set signal SET switches from the high level to the low level, and switches the reset signal RESET from the low level to the high level. Sometimes the gate signal G1 is switched from high level to low level.

  Further, the timing control circuit 1 switches from the low level to the high level when the set signal SET switches from the low level to the high level based on the set signal SET, and has a high level period shorter than the high level period of the set signal SET. An internal clock signal CLK is generated internally. Each high level period of the internal clock signal CLK is a fixed time, and is a period of current feedback in the third generation example of the slope voltage. Each high level period of the internal clock signal CLK is set such that the internal clock signal CLK is switched from the high level to the low level before the start of the dead time provided immediately after the lower MOS transistor Q2 is switched from on to off. Adjust it.

  Further, the timing control circuit 1 forces the gate signal G1 to the low level and the gate signal G2 to the high level regardless of the level transition state of the reset signal RESET when the internal clock signal CLK is switched from the low level to the high level. To do. Thus, current feedback can be reliably started when the internal clock signal CLK is switched from the low level to the high level.

  The slope circuit 5 switches on / off of the switches S <b> 1 to S <b> 3 in accordance with an instruction from the timing control circuit 1.

When the reset signal RESET switches from the low level to the high level (at timing t31), the slope circuit 5 maintains the switch S1 in the off state, switches the switch S2 from the off state to the on state, and switches the switch S3 in the off state. Switch from on to off. As a result, the capacitors C2 and C3 are discharged, and the charging voltage V _CRG and the slope voltage V _SLP of the capacitor C2 become 0, respectively.

  Then, after the slope circuit 5 switches the switch S2 from the on state to the off state and finishes discharging the capacitor C2, when the internal clock signal CLK switches from the low level to the high level (at the timing of t32), the slope circuit 5 The switch S1 is switched from the off state to the on state.

  Next, when the internal clock signal CLK is switched from the high level to the low level (at timing t33), the slope circuit 5 switches the switch S1 from the on state to the off state.

Since the switch S1 conducts the current path from the voltage-current conversion circuit 4A to the capacitor C2 for a certain period of time provided in the period from the timing t32 to the timing t33, that is, in the high level period of the set signal SET, the voltage-current conversion The circuit 4A detects the current flowing through the lower MOS transistor Q2, and information on the current flowing through the lower MOS transistor Q2 is accumulated in the form of the charging voltage V _CRG .

Thereafter, the slope circuit 5 switches the switch S3 from the on state to the off state at the timing of t34. The timing of t34 can be, for example, at the start of the dead time provided immediately after the lower MOS transistor Q2 is switched from on to off. Since the capacitor C3 is charged by the output current of the voltage-current conversion circuit 5A in the period from the timing t34 to the next t31 timing, it flows through the lower MOS transistor Q2 in the period from the timing t32 to the timing t33. Current information is transmitted and reflected on the slope voltage V _SLP .

In the first generation example and the second generation example of the slope voltage described above, the on period of the switch S1 is a period depending on the on period of the upper MOS transistor Q1, and therefore the on period of the switch S1 is The voltage varies depending on the ratio of the output voltage V _OUT to the input voltage V _IN , and the control system for current mode control tends to become unstable. On the other hand, in this example of generating the slope voltage, the on-period of the switch S1 is set to a certain period, so that the control system for current mode control is stabilized.

Further, in this example of generating the slope voltage, as in the above-described second example of generating the slope voltage, the transmission of information on the current flowing through the lower MOS transistor Q2 before the upper MOS transistor Q1 is switched from OFF to ON. _Is reflected in the slope voltage V _SLP . Therefore, in this generation example of the slope voltage, the minimum width of the switch voltage V _SW that enables current feedback can be made narrower than the first generation example of the slope voltage described above.

Note that the minimum pulse width of the switch voltage V _SW that enables current feedback is equivalent to the above-described first generation example of the slope voltage, but in this generation example of the slope voltage, the upper MOS transistor Q1 is turned on from off. From the point of time when switching to, the information on the current flowing through the lower MOS transistor Q2 can be modified to start transmission of the slope voltage V _SLP .

From the viewpoint of further stabilizing the control system for current mode control, a superposition unit is provided in the slope circuit 5, and the superposition unit rises for a period from the timing t34 to the timing t31 with a constant slope or that 'generates, the new slope voltage V _SLP pseudo slope voltage V _S voltage superimposed on the slope voltage V _SLP of a triangular waveform (the new slope voltage V _SLP)' outputs as the output voltage of the slope circuit 5 desirable. In this case, as shown in FIG. 6B, when the slope voltage V _SLP ′ exceeds the error signal V _ERR , the reset signal RESET is switched from the low level to the high level.

<Fourth generation example of slope voltage>
In the first to third generation examples of the slope voltage described above, a slope voltage in which current information is reflected in the slope of the slope is generated as shown in FIG. 7, whereas in this generation example, as shown in FIG. A slope voltage is generated by reflecting the current information in the offset voltage of the slope.

When the first to third generation examples of the slope voltage described above are employed, the transfer characteristic (closed loop transfer function) of the control system is applied to the input voltage V _IN and the output load (the load connected to the application terminal of the output voltage V _OUT ). The use condition is limited because it depends, but when this generation example is adopted, the use condition is not restricted because the transfer characteristic (closed loop transfer function) of the control system does not depend on the input voltage V _IN and the output load. There are advantages.

Hereinafter, the relationship between the transfer characteristic of the control system described above, the input voltage V _IN and the output load will be described in detail.

(When first to third examples of slope voltage are used)
The relationship of the following equation (1) is established between the on-duty D of the upper MOS transistor Q1 and the value V _C of the error signal V _ERR output from the error amplifier 2. S _E is the slope slope (fixed value) of the pseudo slope voltage V _S , S _N is the slope slope reflecting the information of the current flowing through the lower MOS transistor Q2, and T is the maximum value of D Is a coefficient for 1 to be 1.

Here, when the value V _C of the error signal V _ERR output from the error amplifier 2 fluctuates by ΔV _C , the on-duty D of the upper MOS transistor Q1 fluctuates by ΔD. Therefore, the following equation (2) is established. Note that S _N ′ is the slope of the slope reflecting the information on the current flowing through the lower MOS transistor Q2.

From the above formulas (1) and (2), ΔD is expressed by the following formula (3).

Here, since S _N is expressed by the following equation (4), the following equation (5) is established. Note that t _P is the information accumulation time of the current flowing through the lower MOS transistor Q2, I _OUT is the output current supplied to the output load, and the value of the error signal V _ERR output from the error amplifier 2 when V _C is varied [Delta] V _C, the output current I _OUT is varied [Delta] I _OUT.

Here, ΔI is expressed by the following equation (6), and ΔV _OUT is expressed by the following equation (7). G _{DV (S)} is a parameter for shaping the switch voltage V _SW to the output voltage V _OUT .

By substituting the above formulas (6) and (7) into the above formulas (3) and (5), the following formula (8) is obtained.

The ratio of ΔV _{OUT to} ΔV _C is expressed by the following equation (9) using the above (8).

From the above equation (9), when the input voltage V _IN increases, the voltage gain increases, and when the output current I _OUT increases, it becomes difficult to cancel the current because G _{DV (S)} is difficult to cancel with the denominator and the numerator. That is, the transfer characteristic (closed loop transfer function) of the control system depends on the input voltage V _IN and the output load.

(When this generation example of slope voltage is adopted)
Similarly to the case where the first to third generation examples of the slope voltage are adopted, considering the transfer characteristics of the control system, the following equation (12) is obtained from the following equation (10). R _S is a parameter indicating how strongly the current information is applied to the slope voltage as an offset voltage, and is represented by the following equation (11).

At this time, when the condition of the following expression (13) is set, the following expression (14) is established.

From the above equation (14), it can be seen that the transfer characteristic (closed loop transfer function) of the control system does not depend on the input voltage V _IN and the output load.

(Details of this generation example)
Next, details of this generation example will be described. The current detection circuit 4 and the slope circuit 5 have the configuration shown in FIG. 9, and the switching power supply device 101 operates as shown in FIG.

  In the example shown in FIG. 9, the current detection circuit 4 is configured by a voltage-current conversion circuit 4A. In the example shown in FIG. 9, the slope circuit 5 includes switches S1, S2, and S4, a capacitor C2, and a constant current source 9. Note that the value of the constant current output from the constant current source 9 is desirably adjustable.

Each of the voltage-current conversion circuit 4A and the constant current source 9 includes a timing control circuit 1, an error amplifier 2, a reference voltage source 3, a current detection circuit 4, a slope circuit 5, a comparator 6, and an oscillator 7. This is a circuit driven by an internal power supply voltage V _CC generated inside an IC [integrated circuit].

The voltage-current conversion circuit 4A converts the drain-source voltage of the lower MOS transistor Q2 into a current and outputs the current. The capacitor C2 is charged by the output current of the voltage / current conversion circuit 4A when the switch S1 is on, and is charged by the output current of the constant current source 9 when the switch S4 is on. On the other hand, when the switch S2 is on, the capacitor C2 is discharged. The charging voltage of the capacitor C2 becomes the slope voltage V _SLP .

  In the example shown in FIG. 10, the timing control circuit 1 switches the gate signal G1 from the low level to the high level when the set signal SET is switched from the high level to the low level, and switches the reset signal RESET from the low level to the high level. Sometimes the gate signal G1 is switched from high level to low level.

  Further, the timing control circuit 1 switches from the low level to the high level when the set signal SET switches from the low level to the high level based on the set signal SET, and has a high level period shorter than the high level period of the set signal SET. An internal clock signal CLK is generated internally. Each high level period of the internal clock signal CLK is a fixed time, and is a period of current feedback in the fourth generation example of the slope voltage. Each high level period of the internal clock signal CLK is set such that the internal clock signal CLK is switched from the high level to the low level before the start of the dead time provided immediately after the lower MOS transistor Q2 is switched from on to off. Adjust it.

  Further, the timing control circuit 1 forces the gate signal G1 to the low level and the gate signal G2 to the high level regardless of the level transition state of the reset signal RESET when the internal clock signal CLK is switched from the low level to the high level. To do. Thus, current feedback can be reliably started when the internal clock signal CLK is switched from the low level to the high level.

  The slope circuit 5 switches on / off of the switches S1, S2, and S4 in accordance with an instruction from the timing control circuit 1.

When the reset signal RESET is switched from the low level to the high level (at timing t41), the slope circuit 5 maintains the switch S1 in the off state, switches the switch S2 from the off state to the on state, and switches on the switch S4. Switch from off to off. As a result, the capacitor C2 is discharged, and the slope voltage V _SLP that is the charging voltage of the capacitor C2 becomes zero.

  Then, after the slope circuit 5 switches the switch S2 from the on state to the off state and completes the discharge of the capacitor C2, when the internal clock signal CLK switches from the low level to the high level (at timing t42), the slope circuit 5 The switch S1 is switched from the off state to the on state.

  Next, when the internal clock signal CLK is switched from the high level to the low level (at timing t43), the slope circuit 5 switches the switch S1 from the on state to the off state.

  Since the switch S1 conducts the current path from the voltage-current conversion circuit 4A to the capacitor C2 during the period from the timing t42 to the timing t43, information on the current flowing through the lower MOS transistor Q2 is in the form of the charging voltage of the capacitor C2. Accumulated.

Next, when the set signal SET is switched from the high level to the low level (at timing t44), the slope circuit 5 switches the switch S4 from the off state to the on state. During the period from the timing t44 to the next timing t41, the capacitor C2 is charged by the output current of the constant current source 9. As a result, the slope voltage V _SLP that is the charging voltage of the capacitor C2 is a voltage that increases at a constant increase rate according to the output current of the constant current source 9 (a constant slope according to the output current of the constant current source 9). The voltage is superimposed on the offset voltage reflecting the information on the current flowing through the lower MOS transistor Q2. The slope voltage _VSLP, which is the charging voltage of the capacitor C2, becomes the output signal of the slope circuit 5.

In this generation example, the slope voltage V _SLP is generated by reflecting the information on the current flowing through the lower MOS transistor Q2 in the slope offset voltage, so that the transfer characteristic (closed loop transfer function) of the control system is the input voltage V _IN and the output. Independent of load. For this reason, the use conditions of the switching power supply device 101 are not limited.

Further, in this generation example, similar to the above-described second generation example of the slope voltage, before the upper MOS transistor Q1 is switched from OFF to ON, transmission of information on the current flowing through the lower MOS transistor Q2 is started and the slope voltage V _This is reflected in _SLP . Therefore, in this generation example of the slope voltage, the minimum pulse width of the switch voltage V _SW that enables current feedback can be made narrower than that in the first generation example of the slope voltage described above.

  In this generation example, as in the third generation example of the slope voltage described above, the ON period of the switch S1 is set to a constant period, so that the control system for current mode control is stable.

<Overall configuration (second embodiment)>
FIG. 11 is a diagram illustrating an overall configuration example of the second embodiment of the current mode control type switching power supply device. The switching power supply 102 of this configuration example has a configuration in which a current detection circuit 10 is added to the switching power supply 101.

  The current detection circuit 10 detects the current flowing through the upper MOS transistor Q1 based on the drain-source voltage in the ON state of the upper MOS transistor Q1, that is, the voltage across the ON resistance of the upper MOS transistor Q1.

As already described in the first embodiment, the slope circuit 5 generates and outputs a slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the current detection circuit 4, and thereby outputs the slope voltage with respect to the input voltage _VIN . Even when the ratio of the output voltage V _OUT is small (when the pulse width of the switch voltage V _SW is narrow), current feedback is possible. However, in the aspect in which the slope circuit 5 generates and outputs a slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the current detection circuit 4, when the pulse width of the switch voltage V _SW increases, the lower MOS transistor The time during which the current flowing through the transistor Q2 can be detected (the time during which the lower MOS transistor Q2 is on) is shortened, and current feedback may not be performed. On the other hand, in the aspect in which the current mode control is performed by generating the slope voltage corresponding to the current flowing through the upper MOS transistor Q1 as in the prior art, when the pulse width of the switch voltage V _SW increases, the upper MOS transistor Q1 Since the time during which the current flowing through can be detected (the time during which the upper MOS transistor Q1 is on) becomes longer, there is no possibility that current feedback cannot be performed.

Therefore, the slope circuit 5 according to the present embodiment detects the current when the ratio of the output voltage to the input voltage of the switching power supply device 102 (V _OUT / V _IN ) is 50% or less in accordance with the instruction from the timing control circuit 1. A slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the circuit 4 is generated and output, and the upper MOS transistor detected by the current detection circuit 10 when V _OUT / V _IN is not less than 50%. A slope voltage corresponding to the current flowing through Q1 is generated and output. As a result, not only when the pulse width of the switch voltage V _SW becomes narrow, but also when the pulse width of the switch voltage V _SW becomes thick, current feedback becomes possible.

  The generation of the slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the current detection circuit 4 may be performed in the same manner as any of the generation examples already described in the first embodiment, for example. Further, since the generation of the slope voltage corresponding to the current flowing through the upper MOS transistor Q1 detected by the current detection circuit 10 is a known technique, a detailed description thereof will be omitted.

FIG. 12A is a timing chart showing an example of determining whether or not V _OUT / V _IN is 50% or less. The determination is made by switching the gate signal G1 from the low level to the high level when the set signal SET is switched from the low level to the high level, and changing the gate signal G1 from the high level to the low level when the reset signal RESET is switched from the low level to the high level. This is executed by the timing control circuit 1 for switching to the level.

  The timing control circuit 1 generates a divided clock signal DIV based on the set signal SET. The divided clock signal DIV is a signal obtained by dividing the set signal SET by 2, and the switching timing from the low level to the high level coincides with the set signal SET.

  Further, the timing control circuit 1 generates a detection clock signal DET based on the set signal SET and the divided clock signal DIV. The detection clock signal DET is switched from the low level to the high level at the same timing as the set signal SET and the divided clock signal DIV, the divided clock signal DIV is switched from the low level to the high level, and the set signal SET is changed from the low level. It switches from high level to low level at the timing when it does not switch to high level.

The timing control circuit 1 outputs V _OUT when the gate signal G1 is at a high level when the detection clock signal DET is switched from a high level to a low level (in this case, the switch voltage V _SW is at a high level). When it is determined that / V _IN is not 50% or less and the gate signal G1 is at a low level (in this case, the switch voltage V _SW is at a low level), it is determined that V _OUT / V _IN is 50% or less. To do.

FIG. 12B is a timing chart showing another example of determining whether or not V _OUT / V _IN is 50% or less. The determination is made by switching the gate signal G1 from the low level to the high level when the set signal SET is switched from the high level to the low level, and changing the gate signal G1 from the high level to the low level when the reset signal RESET is switched from the low level to the high level. This is executed by the timing control circuit 1 for switching to the level.

  The timing control circuit 1 generates a divided clock signal DIV based on the set signal SET. The divided clock signal DIV is a signal obtained by dividing the set signal SET by 2, and the switching timing from the high level to the low level coincides with the set signal SET.

  Further, the timing control circuit 1 generates a detection clock signal DET based on the set signal SET and the divided clock signal DIV. In the detection clock signal DET, the switching timing from the low level to the high level coincides with the switching timing from the high level to the low level of the set signal SET and the divided clock signal DIV, and the divided clock signal DIV is switched from the high level to the low level. And the set signal SET switches from the high level to the low level at a timing when the set signal SET does not switch from the high level to the low level.

The timing control circuit 1 outputs V _OUT when the gate signal G1 is at a high level when the detection clock signal DET is switched from a high level to a low level (in this case, the switch voltage V _SW is at a high level). When it is determined that / V _IN is not 50% or less and the gate signal G1 is at a low level (in this case, the switch voltage V _SW is at a low level), it is determined that V _OUT / V _IN is 50% or less. To do.

In the above description, when V _OUT / V _IN is 50% or less, the slope voltage corresponding to the current flowing through the lower MOS transistor Q 2 detected by the current detection circuit 4 is output from the slope circuit 5. 50% is merely an example, and other values may be used.

In the above description, when V _OUT / V _IN is not 50% or less, the slope voltage corresponding to the current flowing through the upper MOS transistor Q 1 detected by the current detection circuit 10 is output from the slope circuit 5. _A configuration in which the current mode control is not performed when _OUT / V _IN is not equal to or less than a predetermined value may be used to avoid the possibility that current feedback cannot be performed when the pulse width of the switch voltage V _SW becomes thick. For example, when the slope circuit 5 generates a pseudo slope voltage and V _OUT / V _IN is not more than a predetermined value, the slope voltage corresponding to the current flowing through the lower MOS transistor Q2 detected by the current detection circuit 4 Is output from the slope circuit 5 as an output voltage of the slope circuit 5, and when V _OUT / V _IN is not less than or equal to a predetermined value, the pseudo slope voltage of the slope circuit 5 is superposed on the pseudo slope voltage. What is necessary is just to make it output from the slope circuit 5 as an output voltage.

<Application>
Next, an application example of the switching power supply device 101 described above will be described. FIG. 13 is an external view showing a configuration example of a vehicle equipped with an in-vehicle device. The vehicle X of this configuration example includes onboard devices X11 to X17 and a battery (not shown) that supplies power to these onboard devices X11 to X17.

  The in-vehicle device X11 is an engine control unit that performs control related to the engine (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto cruise control).

  The in-vehicle device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The in-vehicle device X13 is a transmission control unit that performs control related to the transmission.

  The in-vehicle device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power Steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The in-vehicle device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The in-vehicle device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment item or a manufacturer option product such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, and an air conditioner.

  The in-vehicle device X17 is an electronic device that is arbitrarily attached to the vehicle X by the user, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [Electronic Toll Collection System].

  The switching power supply device 101 described above can be incorporated in any of the in-vehicle devices X11 to X17.

<Other variations>
The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  For example, in the above embodiment, the step-down switching power supply device has been described as an example. However, the application target of the present invention is not limited to this, and the step-up / step-down switching that can perform not only the step-down operation but also the step-up operation is possible. It is also possible to apply to a power supply device.

  As described above, the above embodiments are examples in all respects and should not be considered to be restrictive, and the technical scope of the present invention is not the description of the above embodiments, but the claims. It is to be understood that all changes that come within the scope of the claims, are equivalent in meaning to the claims, and fall within the scope of the claims.

  The present invention can be used for a current mode control type switching power supply device used in all fields (such as home appliance field, automobile field, industrial machine field, etc.).

DESCRIPTION OF SYMBOLS 1 Timing control circuit 2 Error amplifier 3 Reference voltage source 4, 10 Current detection circuit 4A, 5A Voltage current conversion circuit 5 Slope circuit 6 Comparator 7 Oscillator 8 Current source 9 Constant current source 101, 102 Switching power supply device C1 Output capacitor C2, C3 Capacitor L1 Inductor Q1 Upper MOS transistor Q2 Lower MOS transistor Q3-Q10 Transistors R1, R2 Voltage dividing resistor R3-R6 Resistor S1-S4 Switch X Vehicle X11-X17 In-vehicle device

Claims (10)

A first switch having a first end connected to an input voltage application end;
A second switch having a first end connected to a second end of the first switch and a second end connected to an application end of a voltage lower than the input voltage;
A current detector for detecting a current flowing through the second switch;
A control unit for controlling the first switch and the second switch according to the current detected by the current detection unit;
With
The controller is
An accumulator that accumulates information of the current detected by the current detector during a predetermined period while the first switch is in an off state;
A reflection unit that reflects the information of the current accumulated by the accumulation unit in the offset voltage of the slope voltage;
A slope setting unit for making the slope of the slope voltage slope constant;
Have
Controlling the first switch and the second switch according to the slope voltage;
The reflection unit is
Before the first switch is switched from OFF to ON, transmission of current information stored by the storage unit is started to reflect the current information stored by the storage unit in the offset voltage of the slope voltage. A current mode control type switching power supply.   The current mode control type switching power supply device according to claim 1, wherein the predetermined period is a constant time. The current detection unit is a voltage-current conversion circuit that converts a voltage corresponding to a current flowing through the second switch into a current,
The current mode control type switching power supply according to claim 1, wherein the storage unit and the reflection unit share a capacitor that charges the output current of the voltage-current conversion circuit. The inclination setting unit is
A constant current source;
A slope switch for conducting / cutting off a current path from the constant current source to the capacitor;
The current mode control type switching power supply device according to claim 3. 5. The current mode control type switching power supply device according to claim 3, wherein the storage unit further includes a charging switch that conducts / cuts off a current path from an output terminal of the voltage-current conversion circuit to the capacitor. 6. 6. The current mode control switching power supply device according to claim 3, wherein the storage unit includes a reset unit that discharges the capacitor and resets a charging voltage of the capacitor. 7. The controller is
An error amplifier that generates an error signal according to a difference between a voltage according to the output voltage and a reference voltage;
A comparator that compares the slope voltage with the error signal to generate a reset signal that is a comparison signal;
An oscillator that generates a set signal that is a clock signal of a predetermined frequency;
A timing control circuit for controlling on / off of the first switch and on / off of the second switch according to the set signal and the reset signal;
The current mode control type switching power supply unit according to any one of claims 1 to 6. The second switch is a MOS transistor;
The current mode control type switching power supply according to any one of claims 1 to 7, wherein the current detection unit detects a current flowing through the second switch by using a voltage across the ON resistance of the MOS transistor. An in-vehicle device comprising the current mode control type switching power supply device according to any one of claims 1 to 8. In-vehicle device according to claim 9,
A battery for supplying power to the in-vehicle device;
A vehicle comprising:

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