JPH02244200A - Pitch detecting circuit for processing voice signal - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to detect pitch frequencies at a high speed by including a signal pair outputting means, difference detecting means which detects the level differences of signal, integrating means, and peak detecting means. CONSTITUTION:This circuit includes a delay circuit 1 for which a bucket brigading device (BBD) is used, a buffer circuit 2 for which a sample-hold circuit is used, and an absolute difference computing section 3 connected to the output of the BBD delay circuit 1 and the buffer circuit 2. The circuit also includes a peak-hold circuit 4 connected to the output thereof, a coefft. multiplier 5 for multiplying a coefft. alpha, and a comparator 6 for comparing the output signals from the absolute difference computing section 3 and the multiplier 5. The absolute value of the level difference between the original input signal and the delayed signal thereof is determined and the total sum of every 16 steps of the input signals is computed to detect the min. value of the prescribed function, by which the pitch frequencies of the voice signal are obtd. The circuit is extremely simplified in this way and the pitch frequencies are detected at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pitch detection circuit for audio signal processing, and in particular, to an audio signal processing method that is capable of detecting the pisochi frequency of an audio signal through real-time processing. The present invention relates to a pitch detection circuit for use in a computer.

[Prior Art] Currently proposed speech analysis methods include short-time spectrum analysis, linear predictive analysis, and cepstral analysis. To perform analysis using these techniques, it is necessary to synchronize the analyzer with the input audio signal. At the same time, the feature values of audio signals generally vary depending on the speaker, and even for the same speaker, the feature values change during the vocalization process, so extraction of the feature values in real time is required.

Therefore, in speech analysis, it is necessary to detect sound source parameters, that is, pitch frequency, in parallel with spectrum analysis. Although various methods have been proposed as pitch frequency detection methods, there is currently no established method.

[Problems to be Solved by the Invention] There are many problems when processing using a digital computer or digital signal processor to satisfy the above requirements. That is, although complex processing can be performed with high precision, the amount of calculation becomes enormous, making real-time processing difficult. Furthermore, since an A/D converter, a D/A converter, etc. are required, processing time increases, and there are also problems in terms of increased hardware scale and cost.

For example, one for detecting the pitch frequency of an audio signal.
One known method is the autocorrelation method. In this method, the following autocorrelation function is defined and used.

In this method, by using equation (1), the pitch frequency is detected by calculating the product and sum of the original input signal and its delayed signal, and knowing the maximum value thereof. However, in order to simplify equation (1), it is necessary to create an N-stage delay device, an N-stage buffer corresponding to it, and an N-stage delay device.
two-variable multipliers are required. Further, in order to construct a two-manpower multiplier with high precision using an SC circuit, the circuit scale increases.

That is, the method using equation (1) has the problem that the circuit scale increases, and as a result, the pitch frequency cannot be detected at high speed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a pitch detection circuit for audio signal processing that can simplify the circuit configuration and detect pitch frequencies at high speed.

[Means for Solving the Problems] A pitch detection circuit for audio signal processing according to the present invention receives an input audio signal and detects a plurality of audio signal pairs separated by a predetermined time length at each predetermined sample interval. a signal pair output means for outputting; a difference detection means connected to the signal pair output means for detecting a signal level difference for each audio signal pair; and an integration means for integrating the signal output from the difference detection means with respect to a sample interval. , and peak detection means for detecting the peak of the signal output from the integration means.

[Function] In the pitch detection circuit for audio signal processing in this invention,
The signal pair output means outputs a plurality of audio signal pairs separated by a predetermined length of time at predetermined sample intervals. The difference detection means detects the level difference between each audio signal pair. The integrating means integrates the signal output from the difference detecting means. The pitch frequency of the input audio signal is detected by the peak detecting means detecting the peak of the signal output from the integrating means.

[Embodiments of the Invention] The following equation (2) defines a new function φ(k) based on the autocorrelation function in the embodiments of the invention.

ST! =F'16 (ABS: absolute m) where, x
(iT) is a discrete input audio signal, N is the number of samples,
T is the sample interval. Therefore, the frame length is N
It becomes T.

Equation (2) calculates the absolute value of the level difference between the original input signal and its delayed signal, and calculates the sum of the input signals every 16 steps. At this time, the pitch frequency of the audio signal is obtained by using kT as a parameter of the time component and detecting the minimum value of the function φ(k).

FIG. 2A is a waveform diagram showing an example of the input audio signal x (t). Moreover, FIG. 2B shows the signal x (
t) is a graph showing calculation results when formula (2) is applied. In FIG. 2B, the vertical axis shows the value of φ(k), and the horizontal axis shows the time axis (kT).

In this way, the pitch period (Tp) shown in FIG.
This is obtained as the time width (Tp) shown in Figure B.

That is, by knowing the value kT at which the minimum value of the function φ(k) is obtained, it is possible to know the pitch period Tp of the audio signal X(1).

FIG. 3 is a block diagram of a pitch detection circuit for audio signal processing showing an embodiment of the present invention. Referring to Figure 3,
This pitch detection circuit consists of a delay circuit 1 using a packet brigade device (hereinafter referred to as BBD), a buffer circuit 2 using a sample and hold circuit, and an absolute A difference calculation unit 3, a peak hold circuit 4 connected to the output of the absolute difference calculation unit 3, a coefficient multiplier 5 for multiplying the peak-held output signal by a coefficient α, the absolute difference calculation unit 3 and the multiplier. and a comparator 6 for comparing the output signals from 5.

FIG. 4A is a circuit diagram showing an example of the BBD delay circuit 1 and buffer circuit 2 shown in FIG. 3.

In this embodiment, 16 BBDIOs each connected in cascade are provided in the BBD delay circuit 1 in order to delay the input audio signal in 16 stages.

Since each BBDIO functions as a 16-stage delay element, it outputs a signal delayed by 256 stages (-16×16). Similarly, the buffer circuit 2 includes 16 sample and hold circuits 20. Each sample hold circuit 20 is
It includes a capacitor 23 that samples the output signal from each BBDIO as an amount of charge in response to a clock signal, and a unity gain buffer 21. Note that an example of the BBDlo circuit is shown in FIG. 4B.

By using the circuit shown in FIG. 4A, the output signals shown in the following equation (3) can be obtained from each of the BBD delay circuit 1 and the delay circuit 2.

FIG. 1A is a circuit diagram showing an example of the absolute difference calculating section shown in FIG. 3. FIG. 1B is a time chart of control signals for controlling the operation.

Referring to FIG. 1A, this absolute difference calculation unit includes a multiplexer 31 connected to receive output signals from the BBD delay circuit and the buffer circuit, and a multiplexer 31 connected to receive output signals from the BBD delay circuit and the buffer circuit.
, and an adder 34 connected to the outputs of the absolute difference detection circuits 32 and 33.

Since the multiplexer 31 is time-division multiplexed from the absolute difference detection circuit 32, the control signals INHI and INH2 are
Four analog switches operate in response to That is, the signal pairs output from BBD delay circuit 1 and buffer circuit 2, respectively, are provided to absolute difference detection circuits 32 and 33, respectively.

In the absolute difference detection circuit 32, switching elements 321 and 3 are activated in response to an externally applied clock signal CP2.
22 turns on. Output signal v from multiplexer 31
1 and v2 are applied to each electrode of a capacitor 323 via switching elements 321 and 322, respectively. Therefore, the potential difference between the signals v1 and v2 is sampled as the amount of charge charged by the capacitor 323. The charge charged in either electrode of the capacitor 323 is output to the adder 34. That is, a comparison circuit 325 is provided for comparing signals v1 and v2, and a signal φ indicating the comparison result is output from this circuit 325.
1 and φ2 are output. Switching elements 324 and 326 are provided between each electrode of capacitor 323 and ground, and one of these is turned on in response to one of signals φ1 and φ2. As a result, a signal indicating the absolute difference between signals v1 and v2 is provided to adder 34.

Adder 34 is constituted by an integrating circuit, and performs addition of signals output from absolute difference detection circuits 32 and 33. The added signal is output via a switching element 35 that operates in response to an external clock signal φ4.

FIG. 5 is a circuit diagram showing an example of the peak hold circuit 4 shown in FIG. 3. Referring to FIG. 5, this peak hold circuit 4 resets two operational amplifiers 41 and 42, an NMOS transistor 43 and a capacitor 45 connected in series between the power supply VDO and the ground, and the capacitor 45. and an NMOS transistor 44 for.

In operation, the input voltage Vin is the output voltage V.

When higher than ut, transistor 43 is turned on. Therefore, the capacitor 45 has voltage Vout equal to voltage Vin.
is charged until it becomes equal to . As a result, capacitor 4
The peak voltage held by 5 is outputted as an output voltage Vout via an operational amplifier 42 that constitutes a voltage follower.

FIG. 6A is a circuit diagram showing an example of coefficient multiplier 5 shown in FIG. 3. Further, FIG. 6B is a waveform diagram of clock signals φ1 and φ2 for controlling the counting multiplier shown in FIG. 6A. Referring to FIG. 6A, this coefficient multiplier 5 is
It includes switching elements 51 and 53 that operate in response to clock signals φ1 and φ2, a capacitor 52, an operational amplifier 54, a capacitor 55, and a switching element 56 that operates in response to clock signal φ2.

In this counting multiplier 5, an integrating circuit is constructed, and when the capacitance value of the capacitor 52 is C11 and the capacitance value of the capacitor 55 is Cf, the following relationship holds true.

Vout-(Ci/Cf) eVin-(4) Therefore, by appropriately setting the capacitance values Ci and Cf of capacitors 52 and 55, it is possible to multiply by an arbitrary coefficient (α shown in FIG. 3). .

FIG. 7A is a circuit diagram showing another example of the absolute difference detection circuit shown in FIG. 1A. Further, FIG. 7B shows clock signals φ1. FIG. 3 is a waveform diagram showing waveforms of φ2, 3°4.

Referring to FIG. 7A, this absolute difference detection circuit includes a difference detection section 70 and a control signal generation 8o. Control signal generator 8
0 outputs control signals 1, 1, 2, and 2 in response to the level difference between input voltages v1 and v2 and externally applied clock signals φ1 and φ2. Difference detection section 70
Switching elements 71a and 72a, 7 provided in
1b and 72b operate in response to signals 1, 1, and 2.2, respectively. Furthermore, the switching elements 73a and 74a, 73b and 74b receive a control signal 3 from the outside.
and 4. As a result, the difference detection section 7
0 outputs a signal corresponding to the absolute difference in level in response to input voltages v1 and V2.

The absolute difference detection circuit shown in FIG. 7A is superior to the absolute difference detection circuit shown in FIG. 1 in the following points when integrated. That is, in the absolute difference detection circuit shown in FIG. 1A, one capacitor 323 is provided to detect the difference between input terminals v1 and v2. When the capacitor 323 is provided in an integrated circuit, it will have a parasitic capacitance between each of its electrodes and the substrate. Since each parasitic capacitance varies in size depending on the distance from the substrate, it has an adverse effect on the output characteristics. On the other hand, in the absolute difference detection circuit shown in FIG. 7A, two capacitors 75a and 75b
is provided. The output terminal 76 of the absolute difference detection circuit is
Since the input is to the inverting input terminal (virtual ground) of the operational amplifier provided in the adder 34 shown in FIG. 1A, switching elements 73a and 74a (or 73b
and 74b) are turned on, the capacitor 75a
(or 75b) is not affected by the parasitic capacitance.

Therefore, when the absolute difference detection circuit shown in FIG. 7A is used, it is not affected by the parasitic capacitance associated with the integrated capacitors 75a and 75b, and as a result,
The absolute difference between input voltages v1 and V2 can be detected accurately.

FIG. 8 is a graph showing experimental data when the pitch frequency of an audio signal was determined using the pitch detection circuit shown in FIG. Referring to FIG. 8, the horizontal axis represents the frequency of the input audio signal, and the vertical axis represents the frequency detected by the pitch detection circuit. In the experiment, the coefficient α set in the counting multiplier shown in Fig. 3 was set as α-0, 15, 0, 20, 0,
Data were obtained for the cases where each setting was set to 25. In this graph, input frequencies of about 190 Hz or less are omitted because the trends in each case are similar. In this experiment, the delay steps of the BBD delay circuit were 16 steps, and the sample interval T was 0.125.
It is set as m5. Further, the human voice signal is a 3Vp-p sine wave.

As can be seen from FIG. 8, when the coefficient α was set to 0.20, the average error was 3%, and good results were obtained. 31
．． At frequencies below 25 Hz, the frame length of the delay stage is 3
2m5, it is theoretically impossible to detect the pitch frequency.

FIG. 9 is a graph showing the amplitude characteristics of the pitch detection circuit shown in FIG. 3. Referring to FIG. 9, the horizontal axis represents the voltage of the input audio signal, and the vertical axis represents the pitch frequency detected by the pitch detection circuit.

In the experiment, a 100 Hz sine wave was given as the input audio signal. As can be seen from FIG. 9, it is not possible to accurately obtain the pitch frequency where the voltage of the input audio signal is low, but it is shown that the pitch frequency can be accurately detected at approximately 3.2 V or higher. This is considered to be because when the input voltage is low, the attenuation caused by the delay circuit is large, so the absolute difference cannot be detected accurately. However, as long as the voltage of the human voice signal is amplified using an amplifier, the pitch frequency can be detected accurately without any problem.

FIGS. 10A and 10B are waveform diagrams showing examples of output from the synchroscope when pitch frequencies are determined for the vowels "a" and "i", respectively.

As shown in FIGS. 10A and 10B, respectively, pitch periods Tpl and Tp2 are obtained from the pulse width of the pitch detection pulse.

In this way, by using the pitch detection circuit for audio signal processing shown in Fig. 3, the enclosure can be greatly simplified compared to the conventional method, and as a result, the pitch frequency can be detected at high speed. I can do it.

This is because the pitch detection circuit shown in FIG. 3 performs processing on the real time axis using an analog circuit.

[Effects of the Invention] As described above, according to the present invention, the pitch frequency of the input audio signal is detected by detecting the zeta of the signal obtained by integrating the level difference between a pair of audio signals.
A pitch detection circuit for audio signal processing with a simplified circuit configuration and capable of operating at high speed was obtained.

[Brief explanation of drawings]

FIG. 1A is a circuit diagram showing an example of an absolute difference calculating section used in the circuit shown in FIG. 3. FIG. 1B is a time chart of control signals for controlling the absolute difference calculating section shown in FIG. 1A. FIG. 2A is a waveform diagram showing an example of a human voice signal. FIG. 2B is a graph showing changes in the function φ(k). FIG. 3 is a block diagram of a pitch detection circuit for audio signal processing showing an embodiment of the present invention. FIG. 4A is a circuit diagram showing the BBD delay circuit and buffer circuit shown in FIG. 3. FIG. 4B is a circuit diagram of a BBD used in the circuit shown in FIG. 4A. FIG. 5 is a circuit diagram showing an example of the peak hold circuit shown in FIG. 3. 6th
FIG. A is a circuit diagram showing an example of the coefficient multiplier shown in FIG. 3. FIG. 6B is a waveform diagram of a clock signal for controlling the coefficient multiplier shown in FIG. 6A. FIG. 7A is a circuit diagram showing another example of the absolute difference detection circuit shown in FIG. 1. 7th
FIG. B is a waveform diagram showing the waveform of a clock signal externally applied to the absolute difference detection circuit shown in FIG. 7A. FIG. 8 is a graph showing pitch detection characteristics of the pitch detection circuit shown in FIG. 3. FIG. 9 is a graph showing the amplitude characteristics of the pitch detection circuit shown in FIG. 3. FIGS. 10A and 10B are waveform diagrams showing output waveforms of the synchrocope. In the figure, 1 is a BBD delay circuit, 2 is a buffer circuit,
3 is an absolute difference calculation unit, 4 is a peak hold circuit, 5 is a counting multiplier, 6 is a comparator, 31 is a multiplexer, 3
2 and 33 are absolute difference detection circuits, and 34 is an adder.

Claims (1)

[Scope of Claims] Signal pair output means connected to receive an input audio signal and outputting a plurality of audio signal pairs separated by a predetermined length of time at predetermined sample intervals; difference detection means connected to the output means and detecting a signal level difference for each pair of audio signals; and difference detection means connected to the difference detection means and integrated the signal output from the difference detection means for the plurality of sample intervals. A pitch detection circuit for audio signal processing, comprising: an integrating means; and a peak detecting means connected to the integrating means and detecting a peak of a signal output from the integrating means.