CN114553195A - Duty ratio information extraction method, square wave voltage conversion circuit and duty ratio control circuit - Google Patents

Duty ratio information extraction method, square wave voltage conversion circuit and duty ratio control circuit Download PDF

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Publication number
CN114553195A
CN114553195A CN202210088253.3A CN202210088253A CN114553195A CN 114553195 A CN114553195 A CN 114553195A CN 202210088253 A CN202210088253 A CN 202210088253A CN 114553195 A CN114553195 A CN 114553195A
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signal
sampling
circuit
control
square wave
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冯林
关晶晶
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Shanghai Southchip Semiconductor Technology Co Ltd
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Shanghai Southchip Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

The invention relates to a method for extracting duty ratio information in a square wave signal, a square wave voltage conversion circuit and a duty ratio control circuit, and belongs to the field of analog electronic circuits. The method comprises the following steps: controlling current to charge a capacitor by using a square wave signal, and converting the square wave signal into a voltage signal on the capacitor; sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampling voltage signal; sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampling voltage signal; according to the invention, the square wave signal is converted into the voltage information in a manner of charging the capacitor and sampling and holding, so that the extraction of the duty ratio information in the square wave signal is realized.

Description

Duty ratio information extraction method, square wave voltage conversion circuit and duty ratio control circuit
Technical Field
The invention relates to the field of analog electronic circuits, in particular to a duty ratio information extraction method, a square wave voltage conversion circuit and a duty ratio control circuit.
Background
In circuit design, duty ratio information included in a certain square wave signal of a circuit is an important signal for circuit design. During the implementation of the circuit function, it is necessary to generate the corresponding control signal according to the duty ratio, either in a proportional relationship, an inverse relationship, or in other quantitative relationships. Therefore, the extraction of the duty ratio information in the square wave signal is realized, and the extraction is important for the generation of the control signal.
Disclosure of Invention
In view of this, the invention provides a duty ratio information extraction method, a square wave voltage conversion circuit and a duty ratio control circuit to realize extraction of duty ratio information in a square wave signal.
In order to achieve the purpose, the invention provides the following scheme:
a method of extracting duty cycle information in a square wave signal, the method comprising the steps of:
controlling current to charge a capacitor by using a square wave signal, and converting the square wave signal into a voltage signal on the capacitor;
sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampling voltage signal;
sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampling voltage signal; the ratio of the second sampling voltage signal to the first sampling voltage signal is the duty cycle characterized by the square wave signal.
Optionally, the sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampled voltage signal specifically includes:
generating a first sampling control signal and a second sampling control signal according to the rising edge of the square wave signal; the first sampling control signal represents a signal in which a period between a rising edge and a rising edge in an odd cycle in the square wave signal is an active control level, and the second sampling control signal represents a signal in which a period between a rising edge and a rising edge in an even cycle in the square wave signal is an active control level;
respectively sampling and holding the voltage signal on the capacitor according to the first sampling control signal and the second sampling control signal to obtain a first sampling branch signal and a second sampling branch signal;
and acquiring a union operation result of the first sampling branch signal and the second sampling branch signal as the first sampling voltage signal.
Optionally, the sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampled voltage signal specifically includes:
generating a third sampling control signal and a fourth sampling control signal according to the rising edge and the falling edge of the square wave signal; the third sampling control signal represents a signal in which a period between a rising edge and a falling edge in an odd cycle in the square wave signal is an active control level, and the fourth sampling control signal represents a signal in which a period between a rising edge and a falling edge in an even cycle in the square wave signal is an active control level;
respectively sampling and holding the voltage signal on the capacitor according to the third sampling control signal and the fourth sampling control signal to obtain a third sampling branch signal and a fourth sampling branch signal;
and acquiring a union operation result of the third sampling branch signal and the fourth sampling branch signal as the second sampling voltage signal.
A square wave voltage conversion circuit is used for realizing a duty ratio information extraction method in a square wave signal, and comprises the following steps: the circuit comprises a capacitor charging and discharging circuit, a first sampling hold circuit, a second sampling hold circuit and a logic control circuit;
the output end of the capacitor charging and discharging circuit is respectively connected with the input end of the first sampling holding circuit and the input end of the second sampling holding circuit;
the logic control circuit is respectively connected with the control end of the capacitor charging and discharging circuit, the control end of the first sampling holding circuit and the control end of the second sampling holding circuit;
the capacitor charging and discharging circuit is used for charging and discharging a capacitor according to the control of the logic control circuit;
the first sampling hold circuit is used for sampling and holding the voltage signal on the capacitor according to the control of the logic control circuit to obtain a first sampling voltage signal;
and the second sampling and holding circuit is used for sampling and holding the voltage signal on the capacitor according to the control of the logic control circuit to obtain a second sampling voltage signal.
Optionally, the logic control circuit is configured to generate a capacitance charge and discharge control signal, a first sampling control signal, a second sampling control signal, a third sampling control signal, a fourth sampling control signal, a first union operation control signal, and a second union operation control signal according to the square wave signal;
the capacitance charge and discharge control signal represents a signal of which the preset time period before the end of each period in the square wave signal is an effective control level;
the first sampling control signal represents a signal in which a period between a rising edge and a rising edge in an odd cycle in the square wave signal is an effective control level;
the second sampling control signal represents a signal in which a period between a rising edge and a rising edge in an even number of cycles in the square wave signal is an effective control level;
the third sampling control signal represents a signal in which a period between a rising edge and a falling edge in an odd cycle in the square wave signal is an effective control level;
the fourth sampling control signal represents a signal in which a period between a rising edge and a falling edge in an even-numbered cycle in the square wave signal is an effective control level;
the first collective operation control signal represents a signal of which an even cycle is an effective control level in the square wave signal;
the second union operation control signal represents a signal of which the odd cycle is an effective control level in the square wave signal.
Optionally, the capacitor charging and discharging circuit includes: the circuit comprises a current source, a first capacitor, a capacitor charge-discharge control switch and a first buffer circuit;
one end of the first capacitor is respectively connected with the current source and the input end of the first buffer circuit, and the other end of the first capacitor C1 is grounded;
the capacitor charge-discharge control switch is connected with the capacitor in parallel;
the control end of the capacitor charge-discharge control switch is used as the control end of the capacitor charge-discharge circuit and is connected with the logic control circuit;
and the output end of the first buffer circuit is used as the output end of the capacitor charging and discharging circuit and is respectively connected with the input end of the first sampling and holding circuit and the input end of the second sampling and holding circuit.
Optionally, the first sample-and-hold circuit includes a first sampling branch and a second sampling branch;
the first sampling branch circuit comprises a first sampling control switch, a second capacitor, a second buffer circuit and a first parallel operation control switch; the second sampling branch comprises a second sampling control switch, a third capacitor, a third buffer circuit and a second union operation control switch;
one end of the first sampling control switch and one end of the second sampling control switch are both connected with the output end of the capacitor charging and discharging circuit;
the other end of the first sampling control switch is respectively connected with one end of the second capacitor and one end of the second buffer circuit, the other end of the second capacitor is grounded, and the other end of the second buffer circuit is connected with one end of the first collective operation control switch;
the other end of the second sampling control switch is respectively connected with one end of the third capacitor and one end of the third buffer circuit, the other end of the third capacitor is grounded, and the other end of the third buffer circuit is connected with one end of the second union operation control switch;
the other end of the first parallel operation control switch is connected with the other end of the second parallel operation control switch;
the control end of the first sampling control switch, the control end of the second sampling control switch, the control end of the first parallel operation control switch and the control end of the second parallel operation control switch are respectively connected with the logic control circuit.
Optionally, the second sample-and-hold circuit includes a third sampling branch and a fourth sampling branch;
the third sampling branch comprises a third sampling control switch, a fourth capacitor, a fourth buffer circuit and a third union operation control switch; the fourth sampling branch comprises a fourth sampling control switch, a fifth capacitor, a fifth buffer circuit and a fourth union operation control switch;
one end of the third sampling control switch and one end of the fourth sampling control switch are both connected with the output end of the capacitor charging and discharging circuit;
the other end of the third sampling control switch is respectively connected with one end of the fourth capacitor and one end of the fourth buffer circuit, the other end of the fourth capacitor is grounded, and the other end of the fourth buffer circuit is connected with one end of the third union operation control switch;
the other end of the fourth sampling control switch is respectively connected with one end of the fifth capacitor and one end of the fifth buffer circuit, the other end of the fifth capacitor is grounded, and the other end of the fifth buffer circuit is connected with one end of the fourth union operation control switch;
the other end of the third parallel set operation control switch is connected with the other end of the fourth parallel set operation control switch;
and the control end of the third sampling control switch, the control end of the fourth sampling control switch, the control end of the third parallel operation control switch and the control end of the fourth parallel operation control switch are respectively connected with the logic control circuit.
A duty cycle control circuit comprises a square wave voltage conversion circuit and further comprises: the voltage-to-current conversion circuit, the current operation circuit and the current-to-voltage conversion circuit are connected in series;
the square wave voltage conversion circuit is used for converting a square wave signal into a first sampling voltage signal and a second sampling voltage signal, and the ratio of the second sampling voltage signal to the first sampling voltage signal is the duty ratio represented by the square wave signal;
the voltage-to-current circuit is used for respectively converting the first sampling voltage signal and the second sampling voltage signal into a first current signal and a second current signal; the ratio of the second current signal to the first current signal is the duty ratio characterized by the square wave signal;
the current operation circuit is used for operating an input current signal, the first current signal and the second current signal to obtain an output current signal;
the current-to-voltage circuit is used for converting the output current signal into an output voltage signal.
Optionally, the voltage-to-current circuit is further configured to convert an input voltage signal into the input current signal.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a method for extracting duty ratio information in a square wave signal, a square wave voltage conversion circuit and a duty ratio control circuit, wherein the method comprises the following steps: controlling current to charge a capacitor by using a square wave signal, and converting the square wave signal into a voltage signal on the capacitor; sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampling voltage signal; sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampling voltage signal; according to the invention, the square wave signal is converted into the voltage information in a manner of charging the capacitor and sampling and holding, so that the extraction of the duty ratio information in the square wave signal is realized.
Meanwhile, on the basis of duty ratio information extraction, the duty ratio control circuit further arranges a voltage-to-current circuit and the like, and realizes the improvement of the duty ratio change response speed in the control process by adopting a current element calculation mode.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a prior art control circuit based on duty cycle information of a square wave signal;
fig. 2 is a flowchart of a method for extracting duty ratio information from a square wave signal according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a square-wave to voltage conversion circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a control logic of a square-wave to voltage conversion circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a duty cycle control circuit according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a current computing circuit according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a multiplication-division operation circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a duty ratio information extraction method, a square wave voltage conversion circuit and a duty ratio control circuit so as to extract duty ratio information in square wave signals.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The prior art is implemented as shown in fig. 1, in which a duty cycle circuit and a filter circuit are added on the basis of a buffer circuit. The duty ratio circuit leads the duty ratio information of the square wave signal through a three-state switchInto the circuit. When the square wave signal is at high level, the switch is connected to Vout(ii) a When the wave signal is low, the switch is connected to ground. After the circuit is built, V-is VinDuty cycle circuit makes VoutD ═ V-, so that V is obtainedout＝Vin/D。
The disadvantage of this approach is the long settling time, V, of the stable operating point of the circuitoutIt takes a long time to build up gradually. In a fast response system, the change in duty cycle takes longer to be reflected in VoutAbove, this does not meet the design requirements. The invention provides an improved technical scheme aiming at the defect, which comprises the following specific steps:
example 1
As shown in fig. 2, in the method for extracting the duty ratio information in the square wave signal, the duty ratio information of the pulse signal is firstly converted into voltage by controlling a charge-discharge circuit and a sample-hold circuit of a capacitor, and the duty ratio information of the high level time and the period of the square wave signal is converted into two voltage signals with equal proportion; the method comprises the following steps:
step 101, controlling current to charge a capacitor by using a square wave signal, and converting the square wave signal into a voltage signal on the capacitor.
And 102, sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampling voltage signal.
Illustratively, the present invention implements real-time output of the first sampled voltage signal by two-way sampling and alternate sample-and-hold, that is, step 102 specifically includes: generating a first sampling control signal and a second sampling control signal according to the rising edge of the square wave signal; the first sampling control signal represents a signal in which a period between a rising edge and a rising edge in an odd cycle in the square wave signal is an active control level, and the second sampling control signal represents a signal in which a period between a rising edge and a rising edge in an even cycle in the square wave signal is an active control level; respectively sampling and holding the voltage signal on the capacitor according to the first sampling control signal and the second sampling control signal to obtain a first sampling branch signal and a second sampling branch signal; and acquiring a union operation result of the first sampling branch signal and the second sampling branch signal as a first sampling voltage signal.
103, sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampling voltage signal; the ratio of the second sampling voltage signal to the first sampling voltage signal is the duty cycle characterized by the square wave signal.
Illustratively, the present invention realizes outputting the second sampling voltage signal in real time by two-way sampling and alternate sampling and holding, that is, step 103 specifically includes: generating a third sampling control signal and a fourth sampling control signal according to the rising edge and the falling edge of the square wave signal; the third sampling control signal represents a signal in which a period between a rising edge and a falling edge in an odd cycle in the square wave signal is an active control level, and the fourth sampling control signal represents a signal in which a period between a rising edge and a falling edge in an even cycle in the square wave signal is an active control level; respectively sampling and holding the voltage signal on the capacitor according to the third sampling control signal and the fourth sampling control signal to obtain a third sampling branch signal and a fourth sampling branch signal; and acquiring a union operation result of the third sampling branch signal and the fourth sampling branch signal as the second sampling voltage signal.
Example 2
As shown in fig. 3, the present invention provides a square wave to voltage conversion circuit, which is used to implement the method for extracting duty ratio information from a square wave signal in embodiment 1, embodiment 2 of the present invention is an implementation manner of embodiment 1, but the implementation manner of embodiment 1 of the present invention is not limited to embodiment 2.
The square wave voltage conversion circuit comprises: the circuit comprises a capacitor charging and discharging circuit 1, a first sampling hold circuit 2, a second sampling hold circuit 3 and a logic control circuit 4; the output end of the capacitor charging and discharging circuit 1 is respectively connected with the input end of the first sample-and-hold circuit 2 and the input end of the second sample-and-hold circuit 3; the logic control circuit 4 is respectively connected with the control end of the capacitor charging and discharging circuit 1, the control end of the first sampling holding circuit 2 and the control end of the second sampling holding circuit 3; the capacitor charging and discharging circuit 1 is used for charging and discharging a capacitor according to the control of the logic control circuit 4; the first sampling and holding circuit 2 is used for sampling and holding the voltage signal on the capacitor according to the control of the logic control circuit 4 to obtain a first sampling voltage signal; the second sample-and-hold circuit 3 is configured to sample and hold the voltage signal on the capacitor according to the control of the logic control circuit 4, and obtain a second sampled voltage signal.
The working principle of the square wave voltage conversion circuit in the embodiment 2 of the invention is as follows: the high-low level logic signal (namely square wave signal) representing the duty ratio information is converted into a voltage signal on the capacitor through charging the capacitor by current, the sampling and holding of the voltage on the capacitor are controlled through the rising and falling edges of the input duty ratio signal, and the ratio of the voltage signal after sampling and holding is output to represent the duty ratio. And the voltage signal representing the duty ratio is output in real time through two-way sampling and alternate sampling and holding.
Based on the above working principle, as shown in fig. 4, a control logic schematic diagram of the square wave to voltage conversion circuit in embodiment 2 of the present invention converts time into voltage by charging a capacitor with current, wherein four sampling and holding circuits (a first sampling branch a, a second sampling branch B, a third sampling branch C, and a fourth sampling branch D) are alternately enabled by time division multiplexing, and two sampling circuits hold and sample two ways within each period, so as to realize real-time output of duty ratio information representing adjacent periods. The voltages at sampling Vc at ton are alternately controlled by STon _ n and STon _ n +1, and the voltages sampled by STon _ n and STon _ n +1 are output through Buffer circuits buffers (fourth Buffer circuit Buffer4 and fifth Buffer circuit Buffer5) alternately controlled by Channel1 and Channel2 by Channel _ C and Channel _ D. Likewise, ST _ n and ST _ n +1 alternately control the voltage at sample Vc at T, and Channel1 and Channel2 alternately control Channel _ a and Channel _ B to perform union operation on the voltages at sample Vc and sample ST _ n +1 and output (the union operation described herein is to take the signal with the larger amplitude of the two signals as the union operation result). VTonAnd VTThe sampling hold circuit is respectively provided with two paths, one pathOne path is used for sampling the voltage value of the current period, and the other path is used for holding the data of the previous period. And sampling is performed alternately, so that the function of sampling and holding is achieved.
Based on the above principle, an exemplary specific implementation manner of the square wave to voltage conversion circuit in embodiment 2 of the present invention is as follows:
as shown in fig. 3, the logic control circuit 4 is configured to generate a capacitance charge and discharge control signal Reset, a first sampling control signal ST1, a second sampling control signal ST2, a third sampling control signal STon1, a fourth sampling control signal STon2, a first parallel-collection operation control signal Channel1, and a second parallel-collection operation control signal Channel2 according to the square wave signal.
The capacitance charge and discharge control signal Reset represents a signal of which the preset time period before the end of each period in the square wave signal is an effective control level; the first sampling control signal ST1 represents a signal in which the period between a rising edge and a rising edge in an odd cycle in the square wave signal is an active control level; the second sampling control signal ST2 represents a signal in which the period between a rising edge and a rising edge in an even-numbered cycle in the square wave signal is an active control level; the third sampling control signal STon1 represents a signal in which a period between a rising edge and a falling edge in an odd cycle in the square wave signal is an active control level; the fourth sampling control signal STon2 represents a signal in which a period between a rising edge and a falling edge in an even-numbered cycle in the square wave signal is an active control level; the first parallel operation control signal Channel1 represents a signal of which the even period is an effective control level in the square wave signal; the second union operation control signal Channel2 represents a signal in which odd cycles in the square wave signal are active control levels.
The capacitor charging and discharging circuit 1 includes: the current source Ibias, the first capacitor C1, the capacitor charge-discharge control switch Reset _ n and the first Buffer circuit Buffer 1; one end of a first capacitor C1 is respectively connected with a current source Ibias and the input end of a first Buffer circuit Buffer1, and the other end of the first capacitor C1 is grounded; the capacitor charge-discharge control switch is connected with the capacitor in parallel; the control end of the capacitor charge-discharge control switch Reset _ n is used as the control end of the capacitor charge-discharge circuit, is connected with the logic control circuit and is used for inputting a capacitor charge-discharge control signal Reset output by the logic control circuit; the output end of the first Buffer circuit Buffer1 is used as the output end of the capacitor charging and discharging circuit, and is respectively connected with the input end of the first sample-and-hold circuit 2 and the input end of the second sample-and-hold circuit 3.
The first sample-and-hold circuit 2 comprises a first sampling branch a and a second sampling branch B;
the first sampling branch A comprises a first sampling control switch ST _ n, a second capacitor C2, a second Buffer circuit Buffer2 and a first parallel operation control switch Channel _ A; the second sampling branch B comprises a second sampling control switch ST _ n +1, a third capacitor C3, a third Buffer circuit Buffer3 and a second union operation control switch Channel _ B; one end of the first sampling control switch and one end of the second sampling control switch are both connected with the output end of the capacitor charging and discharging circuit; the other end of the first sampling control switch is respectively connected with one end of the second capacitor and one end of the second buffer circuit, the other end of the second capacitor is grounded, and the other end of the second buffer circuit is connected with one end of the first collective operation control switch; the other end of the second sampling control switch is respectively connected with one end of a third capacitor and one end of a third buffer circuit, the other end of the third capacitor is grounded, and the other end of the third buffer circuit is connected with one end of a second union operation control switch; the other end of the first parallel operation control switch is connected with the other end of the second parallel operation control switch; the control end of the first sampling control switch, the control end of the second sampling control switch, the control end of the first parallel operation control switch and the control end of the second parallel operation control switch are respectively connected with the logic control circuit.
The second sample-and-hold circuit 3 comprises a third sampling branch C and a fourth sampling branch D;
the third sampling branch C comprises a third sampling control switch STon _ n, a fourth capacitor C4, a fourth Buffer circuit Buffer4 and a third parallel-set operation control switch Channel _ C; the fourth sampling branch comprises a fourth sampling control switch STon _ n +1, a fifth capacitor C5, a fifth Buffer circuit Buffer5 and a fourth union operation control switch Channel _ D; one end of the third sampling control switch and one end of the fourth sampling control switch are both connected with the output end of the capacitor charging and discharging circuit; the other end of the third sampling control switch is respectively connected with one end of a fourth capacitor and one end of the fourth buffer circuit, the other end of the fourth capacitor is grounded, and the other end of the fourth buffer circuit is connected with one end of the third union operation control switch; the other end of the fourth sampling control switch is respectively connected with one end of a fifth capacitor and one end of the fifth buffer circuit, the other end of the fifth capacitor is grounded, and the other end of the fifth buffer circuit is connected with one end of a fourth union operation control switch; the other end of the third parallel set operation control switch is connected with the other end of the fourth parallel set operation control switch; and the control end of the third sampling control switch, the control end of the fourth sampling control switch, the control end of the third parallel operation control switch and the control end of the fourth parallel operation control switch are respectively connected with the logic control circuit.
The first sampling control switch ST _ n, the second sampling control switch ST _ n +1, the third sampling control switch STon _ n and the fourth sampling control switch STon _ n +1 are respectively controlled by a first sampling control signal ST1, a second sampling control signal ST2, a third sampling control signal STon1 and a fourth sampling control signal STon2 output by the logic control circuit.
The first parallel-collection operation control switch Channel _ A and the third parallel-collection operation control switch Channel _ C are controlled by a first parallel-collection operation control signal Channel1 output by the logic control circuit; the second and third parallel operation control switches Channel _ B and Channel _ D are controlled by a second parallel operation control signal Channel2 output by the logic control circuit.
The embodiment 2 of the present invention realizes the conversion from a square wave signal to a voltage, as shown in fig. 4, where Vduty is a pulse signal (i.e. a square wave signal) with a duty ratio D, and ton/T ═ D. The capacitor charge and discharge control signal Reset controls the charging and discharging of the first capacitor C1, and the Reset is discharged once every cycle and then recharged. And then sampling and holding are respectively carried out for the duration ton and T when the charging action is carried out. This converts an equal proportion of time to an equal proportion of voltage.
STon _ n and STon _ n +1 alternately control the voltage at sample Vc at ton and the voltage output by STon _ n and STon _ n +1 is alternately controlled by Channel _ C and Channel _ D via Buffer circuits Buffer4 and Buffer 5. Likewise, ST _ n and ST _ n +1 alternately control the voltage sampled at Vc and through Buffer circuits Buffer2 and Buffer3, Channel _ a and Channel _ B alternately control the voltage output sampled ST _ n and ST _ n + 1. VTonAnd VTThe sampling and holding circuit is respectively provided with two corresponding paths, wherein one path is used for sampling the voltage value of the current period, and the other path is used for holding the data of the previous period. And sampling is performed alternately, so that the function of sampling and holding is achieved. Each period Vc is periodically charged and discharged, when the Channel1 samples the voltage, the Channel2 holds the voltage V which is heldTAnd VTonAnd (6) outputting. The process of sample-and-hold is clearly seen from the waveform at point A, B, C and D. The A and B staggered period samples the Vc voltage at the charging time T and alternately holds. The C and D interleaving periods sample the Vc voltage at the charging time Ton and alternately hold. Then VTAnd VTonThe voltage at (a) is a voltage related to the duty cycle change.
The output voltage of the embodiment 2 of the invention can be quickly established, and the circuit is simple and has high response speed.
Example 3
As shown in fig. 5, the present invention further provides a duty cycle control circuit, which includes a square wave to voltage circuit (T2V), and further includes: arithmetic circuitry that can perform multiplication, division, and other arithmetic functions.
The arithmetic circuit is exemplified by a multiplication-division arithmetic circuit.
The multiplication-division operation circuit illustratively includes: a voltage-to-current circuit (V2I), a current arithmetic circuit (the current arithmetic circuit is exemplified by a current multiplication-division calculation circuit), and a current-to-voltage circuit (I2V); the square wave voltage conversion circuit is used for converting a square wave signal into a first sampling voltage signal and a second sampling voltage signal, and the ratio of the second sampling voltage signal to the first sampling voltage signal is the duty ratio represented by the square wave signal; the voltage-to-current circuit is used for respectively converting the first sampling voltage signal and the second sampling voltage signal into a first current signal and a second current signal; the ratio of the second current signal to the first current signal is the duty ratio represented by the square wave signal; the current operation circuit is used for operating an input current signal, a first current signal and the second current signal to obtain an output current signal; the current-to-voltage circuit is used for converting the output current signal into an output voltage signal.
Illustratively, the voltage-to-current circuit is further configured to convert an input voltage signal into the input current signal.
The working principle of the embodiment 3 of the invention is as follows: the input signal is input voltage Vin and square wave signal V with duty ratio Dduty. The square wave voltage conversion circuit (T2V) converts the square wave signal V into a square wave signaldutyConverted into a second sampling voltage signal VTonAnd a first sampling voltage signal VTTwo voltage signals, and the ratio of these two voltages is equal to the duty cycle D, i.e. VTon/VTD. The voltage-to-current circuit (V2I) further converts V intoTonAnd VTIs converted into a second current signal ITonAnd a first current signal ITAnd I isTonAnd ITIs equal to the duty cycle D.
At the same time, the input voltage VinIs also converted into a uniform input current I by a voltage-to-current circuit (V2I)VinThe subsequent treatment is convenient. I isTon、ITAnd IVinThe signal is operated by a current division calculation circuit to obtain I1/D＝IVin*IT/ITon＝IVinand/D. Finally, the current I is converted into the voltage I2V by a current-to-voltage circuit1/DIs converted into an output voltage signal Vout. To obtain Vout＝Vinand/D. It is noted that, in this method, the input signal of the system is not only the input voltage VinAnd a square wave signal V with a duty cycle DdutyOr may be the input current IinAnd a square wave signal V with a duty cycle Dduty，IinThe current multiplication and division calculation circuit can be directly input without passing through a voltage-to-current circuit.
For example, fig. 6 is a schematic circuit diagram of a current multiplication-division calculating circuit, and many practical current multiplication-division structure diagrams may be derived based on the schematic circuit diagram, and are within the scope of the invention.
In fig. 6, M is a Metal-Oxide-semiconductor field-effect-transistor (MOSFET), which represents a Metal-Oxide-semiconductor field-effect-transistor (MOSFET), abbreviated as a MOSFET, Q represents a triode, IA、IB、ICAnd IDAre respectively Q1、Q2、Q3And Q4The collector current of (a) then satisfies:
VBE1+VBE2＝VBE3+VBE4
due to VBE＝VT*ln(IC/IS) In which V isTIs the thermal voltage of a transistor ICIs the collector current of the transistor, ISIs the reverse saturation current of the transistor. Then can obtain
VT*ln(IA/IS)+VT*ln(IB/IS)＝VT*ln(ID/IS)+VT*ln(IC/IS)
ln(IA/IS)*(IB/IS)＝ln(ID/IS)*(IC/IS)
Namely:
IA*IB＝ID*IC
make IA＝IVin，IB＝IT，IC＝ITonCan obtain ID＝IA*IB/IC＝IVin*IT/ITon＝IVinand/D. And then, the Vout is obtained as Vin/D through the current-to-voltage conversion module.
According to the current multiplication-division calculation circuit of fig. 6, the corresponding specific multiplication-division calculation circuit is shown in fig. 7, AMPs are all amplifiers, M represents a mos tube, and Q represents a triode. Vin、VTAnd VTonConverted into currents through a simple voltage-to-current circuit and respectively input into a current multiplication-division calculation circuit IA、IBAnd ICAnd port, resulting output current I1/D＝IVinThe currents are mirrored by/D, M8 and M9, and the output voltage V is generated through a resistorout. The resistances in fig. 7 require an exact match.
In the specific implementation level of the technical scheme of the invention, many differences in details are provided, including: first, similarly, a square wave signal V is inputteddutyConversion to VTonAnd VTTwo voltage signals, and the ratio of these two voltages is equal to the duty cycle D. Then V will beTonAnd VTConverted into a current signal ITonAnd ITAnd I isTonAnd ITIs equal to the duty cycle D. At the same time, the input voltage VinIs also converted into a uniform current signal IVinThe subsequent treatment is convenient. The control timing of fig. 4 includes the control timing represented by the respective control timing signals, such as the control timing of STon _ n, STon _ n +1, ST _ n +1, and the two-way sample-and-hold concept represented by the control timing signals. VTonAnd VTThe sample hold control method and waveform of (1). The specific implementation of the multiplication-division operation of fig. 5 includes the multiplication-division implementation circuit of fig. 6 in combination with the implementation method of fig. 7, and the voltage V related to the duty ratio is obtained firstTAnd VTonThen connected with a voltage-to-current circuit to convert into a current I related to the duty ratioTAnd ITonThe voltage-to-current module can be generally implemented by an operational amplifier and a resistor, and it is easy to obtain that the output current is in direct proportion to the voltage and in inverse proportion to the resistor, which is not described in detail herein. And similarly, the current signal of the duty ratio is transmitted to the current multiplication and division calculation circuit. Directly operating by a current multiplication and division calculation circuit (as shown in figure 6) to obtain a current signal I1/D＝IVinD, finally converting the current I into the voltage through a current-to-voltage circuit1/DIs converted into an output voltage signal Vout。
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a method for extracting duty ratio information in a square wave signal, a square wave voltage conversion circuit and a duty ratio control circuit, wherein the method comprises the following steps: controlling current to charge a capacitor by using a square wave signal, and converting the square wave signal into a voltage signal on the capacitor; sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampling voltage signal; sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampling voltage signal; according to the invention, the square wave signal is converted into the voltage information in a manner of charging the capacitor and sampling and holding, so that the extraction of the duty ratio information in the square wave signal is realized.
Meanwhile, on the basis of duty ratio information extraction, the duty ratio control circuit further arranges a voltage-to-current circuit and the like, and realizes the improvement of the duty ratio change response speed in the control process by adopting a current element calculation mode.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (10)

1. A method for extracting duty ratio information in a square wave signal is characterized by comprising the following steps:
controlling current to charge a capacitor by using a square wave signal, and converting the square wave signal into a voltage signal on the capacitor;
sampling and holding the voltage signal on the capacitor according to the rising edge of the square wave signal to obtain a first sampling voltage signal;
sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampling voltage signal; the ratio of the second sampling voltage signal to the first sampling voltage signal is the duty cycle characterized by the square wave signal.
2. The method for extracting duty cycle information from a square wave signal according to claim 1, wherein the sampling and holding a voltage signal on a capacitor according to a rising edge of the square wave signal to obtain a first sampled voltage signal specifically comprises:
generating a first sampling control signal and a second sampling control signal according to the rising edge of the square wave signal; the first sampling control signal represents a signal in which a period between a rising edge and a rising edge in an odd cycle in the square wave signal is an active control level, and the second sampling control signal represents a signal in which a period between a rising edge and a rising edge in an even cycle in the square wave signal is an active control level;
respectively sampling and holding the voltage signal on the capacitor according to the first sampling control signal and the second sampling control signal to obtain a first sampling branch signal and a second sampling branch signal;
and acquiring a union operation result of the first sampling branch signal and the second sampling branch signal as the first sampling voltage signal.
3. The method for extracting duty cycle information from a square wave signal according to claim 1, wherein the sampling and holding the voltage signal on the capacitor according to the rising edge and the falling edge of the square wave signal to obtain a second sampled voltage signal specifically comprises:
generating a third sampling control signal and a fourth sampling control signal according to the rising edge and the falling edge of the square wave signal; the third sampling control signal represents a signal in which a period between a rising edge and a falling edge in an odd cycle in the square wave signal is an active control level, and the fourth sampling control signal represents a signal in which a period between a rising edge and a falling edge in an even cycle in the square wave signal is an active control level;
respectively sampling and holding the voltage signal on the capacitor according to the third sampling control signal and the fourth sampling control signal to obtain a third sampling branch signal and a fourth sampling branch signal;
and acquiring a union operation result of the third sampling branch signal and the fourth sampling branch signal as the second sampling voltage signal.
4. A square-wave to voltage conversion circuit, wherein the square-wave to voltage conversion circuit is used for implementing the method for extracting duty cycle information in a square-wave signal according to any one of claims 1 to 3, and the square-wave to voltage conversion circuit comprises: the circuit comprises a capacitor charging and discharging circuit, a first sampling hold circuit, a second sampling hold circuit and a logic control circuit;
the output end of the capacitor charging and discharging circuit is respectively connected with the input end of the first sampling holding circuit and the input end of the second sampling holding circuit;
the logic control circuit is respectively connected with the control end of the capacitor charging and discharging circuit, the control end of the first sampling holding circuit and the control end of the second sampling holding circuit;
the capacitor charging and discharging circuit is used for charging and discharging a capacitor according to the control of the logic control circuit;
the first sampling hold circuit is used for sampling and holding the voltage signal on the capacitor according to the control of the logic control circuit to obtain a first sampling voltage signal;
and the second sampling and holding circuit is used for sampling and holding the voltage signal on the capacitor according to the control of the logic control circuit to obtain a second sampling voltage signal.
5. The square wave voltage conversion circuit according to claim 4, wherein the logic control circuit is configured to generate a capacitance charge and discharge control signal, a first sampling control signal, a second sampling control signal, a third sampling control signal, a fourth sampling control signal, a first union operation control signal, and a second union operation control signal according to the square wave signal;
the capacitance charge and discharge control signal represents a signal of which the preset time period before the end of each period in the square wave signal is an effective control level;
the first sampling control signal represents a signal in which a period between a rising edge and a rising edge in an odd cycle in the square wave signal is an effective control level;
the second sampling control signal represents a signal in which a period between a rising edge and a rising edge in an even number of cycles in the square wave signal is an effective control level;
the third sampling control signal represents a signal in which a period between a rising edge and a falling edge in an odd cycle in the square wave signal is an effective control level;
the fourth sampling control signal represents a signal in which a period between a rising edge and a falling edge in an even-numbered cycle in the square wave signal is an effective control level;
the first collective operation control signal represents a signal of which an even cycle is an effective control level in the square wave signal;
the second union operation control signal represents a signal of which the odd cycle is an effective control level in the square wave signal.
6. The square wave voltage conversion circuit according to claim 4 or 5, wherein the capacitance charging and discharging circuit comprises: the circuit comprises a current source, a first capacitor, a capacitor charge-discharge control switch and a first buffer circuit;
one end of the first capacitor is respectively connected with the current source and the input end of the first buffer circuit, and the other end of the first capacitor C1 is grounded;
the capacitor charge-discharge control switch is connected with the capacitor in parallel;
the control end of the capacitor charge-discharge control switch is used as the control end of the capacitor charge-discharge circuit and is connected with the logic control circuit;
and the output end of the first buffer circuit is used as the output end of the capacitor charging and discharging circuit and is respectively connected with the input end of the first sampling and holding circuit and the input end of the second sampling and holding circuit.
7. The square wave to voltage conversion circuit according to claim 4 or 5, wherein the first sample-and-hold circuit comprises a first sampling branch and a second sampling branch;
the first sampling branch circuit comprises a first sampling control switch, a second capacitor, a second buffer circuit and a first parallel operation control switch; the second sampling branch comprises a second sampling control switch, a third capacitor, a third buffer circuit and a second union operation control switch;
one end of the first sampling control switch and one end of the second sampling control switch are both connected with the output end of the capacitor charging and discharging circuit;
the other end of the first sampling control switch is respectively connected with one end of the second capacitor and one end of the second buffer circuit, the other end of the second capacitor is grounded, and the other end of the second buffer circuit is connected with one end of the first collective operation control switch;
the other end of the second sampling control switch is respectively connected with one end of the third capacitor and one end of the third buffer circuit, the other end of the third capacitor is grounded, and the other end of the third buffer circuit is connected with one end of the second union operation control switch;
the other end of the first parallel operation control switch is connected with the other end of the second parallel operation control switch;
the control end of the first sampling control switch, the control end of the second sampling control switch, the control end of the first parallel operation control switch and the control end of the second parallel operation control switch are respectively connected with the logic control circuit.
8. The square wave to voltage conversion circuit according to claim 4 or 5, wherein the second sample-and-hold circuit comprises a third sampling branch and a fourth sampling branch;
the third sampling branch comprises a third sampling control switch, a fourth capacitor, a fourth buffer circuit and a third union operation control switch; the fourth sampling branch comprises a fourth sampling control switch, a fifth capacitor, a fifth buffer circuit and a fourth union operation control switch;
one end of the third sampling control switch and one end of the fourth sampling control switch are both connected with the output end of the capacitor charging and discharging circuit;
the other end of the third sampling control switch is respectively connected with one end of the fourth capacitor and one end of the fourth buffer circuit, the other end of the fourth capacitor is grounded, and the other end of the fourth buffer circuit is connected with one end of the third union operation control switch;
the other end of the fourth sampling control switch is respectively connected with one end of the fifth capacitor and one end of the fifth buffer circuit, the other end of the fifth capacitor is grounded, and the other end of the fifth buffer circuit is connected with one end of the fourth union operation control switch;
the other end of the third parallel set operation control switch is connected with the other end of the fourth parallel set operation control switch;
and the control end of the third sampling control switch, the control end of the fourth sampling control switch, the control end of the third parallel operation control switch and the control end of the fourth parallel operation control switch are respectively connected with the logic control circuit.
9. A duty cycle control circuit comprising the square wave to voltage conversion circuit of any of claims 4-8, further comprising: the voltage-to-current conversion circuit, the current operation circuit and the current-to-voltage conversion circuit are connected in series;
the square wave voltage conversion circuit is used for converting a square wave signal into a first sampling voltage signal and a second sampling voltage signal, and the ratio of the second sampling voltage signal to the first sampling voltage signal is the duty ratio represented by the square wave signal;
the voltage-to-current circuit is used for respectively converting the first sampling voltage signal and the second sampling voltage signal into a first current signal and a second current signal; the ratio of the second current signal to the first current signal is the duty ratio characterized by the square wave signal;
the current operation circuit is used for operating an input current signal, the first current signal and the second current signal to obtain an output current signal;
the current-to-voltage circuit is used for converting the output current signal into an output voltage signal.
10. The duty cycle control circuit of claim 9, wherein the voltage to current circuit is further configured to convert an input voltage signal to the input current signal.
CN202210088253.3A 2022-01-25 2022-01-25 Duty ratio information extraction method, square wave voltage conversion circuit and duty ratio control circuit Pending CN114553195A (en)

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CN202210088253.3A CN114553195A (en) 2022-01-25 2022-01-25 Duty ratio information extraction method, square wave voltage conversion circuit and duty ratio control circuit

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Application Number Priority Date Filing Date Title
CN202210088253.3A CN114553195A (en) 2022-01-25 2022-01-25 Duty ratio information extraction method, square wave voltage conversion circuit and duty ratio control circuit

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