JP6589751B2 - Charge pump circuit - Google Patents

Description

  The present invention relates to a charge pump circuit that boosts an input voltage input through an input terminal and outputs the boosted voltage through an output terminal.

  In the charge pump circuit, when the output terminal is grounded, an excessive current (hereinafter referred to as an overcurrent) is generated in the main power supply path (hereinafter referred to as the main path) from the input terminal to the output terminal via the backflow prevention diode. Call). Therefore, conventionally, a technique for preventing the occurrence of the overcurrent by blocking the main path at the time of output ground fault has been considered (for example, see Patent Document 1).

JP 2009-183111 A

  When the output terminal of the charge pump circuit is grounded, one terminal is connected not only to the overcurrent flowing from the input terminal to the output terminal, but also to the connection point where the diodes are connected with the operation of the driver of the charge pump circuit. A ripple current that flows intermittently from the capacitor to the output terminal is also generated.

  In the conventional technique described above, when the output is grounded, the current flowing from the input terminal to the output terminal can be suppressed low, but the generation of ripple current cannot be suppressed. For this reason, when the maximum value of the overcurrent exceeds the withstand voltage of the elements constituting the circuit due to the ripple current, there is a possibility that the elements may fail.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a charge pump circuit capable of preventing an excessive current from flowing when an output is grounded.

  The charge pump circuit (1, 31, 41, 51) according to claim 1 boosts an input voltage input through an input terminal (Pi) and outputs the boosted voltage through an output terminal (Po). A plurality of switching elements (D1, D2, D3) connected in series between the terminal and the output terminal, and a plurality of capacitors each having one terminal connected to each connection point where the switching elements are connected to each other ( C1, C2) and a drive circuit (2, 32, 52). The drive circuit is provided corresponding to each of the plurality of capacitors, and the first transistor (T1, T3, T51) interposed between the other terminal of the capacitor and the first power supply line (Li) that supplies the first voltage. , T52, T53, T55) and a second transistor (T2, T4) interposed between the other terminal of the capacitor and a second power supply line (Lg) for supplying a second voltage lower than the first voltage, and And a drive unit (7, 53) for complementarily turning on and off the first and second transistors. In such a configuration, the first transistor is an N-channel MOS transistor, and the drive unit uses the voltage of the power supply node (N3, N31, N32) to which the output voltage output via the output terminal is applied. An on-drive voltage for driving on the first transistor is generated.

  According to the above configuration, when the output terminal is grounded, the voltage of the power supply node becomes almost zero, and the drive unit cannot generate an on-drive voltage for turning on the first transistor, which is an N-channel MOS transistor. . Therefore, when the output terminal is grounded, the second voltage is not applied to the other terminal of the capacitor, and a ripple current that flows intermittently from the capacitor to the output terminal is not generated. Therefore, according to the above configuration, it is possible to obtain an excellent effect of preventing an excessive current from flowing when the output is grounded.

The figure which shows typically the structure of the charge pump circuit which concerns on 1st Embodiment. Timing chart schematically showing waveforms of clock signal, output voltage and power supply current The figure which shows typically the structure of the charge pump circuit which concerns on a 1st comparative example. Timing chart schematically showing waveforms of a clock signal, an output voltage, and a power supply current according to the first comparative example The figure which shows typically the structure of the charge pump circuit which concerns on a 2nd comparative example. The figure which shows typically the structure of the charge pump circuit which concerns on 2nd Embodiment. A diagram schematically showing an example of a specific configuration of a constant current circuit The figure which shows typically the structure of the charge pump circuit which concerns on 3rd Embodiment. The figure which shows typically the structure of the charge pump circuit which concerns on 4th Embodiment.

A plurality of embodiments of the present invention will be described below with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
A charge pump circuit 1 shown in FIG. 1 is provided, for example, in an electronic control device mounted on a vehicle, and boosts an input voltage Vi input through an input terminal Pi and outputs the boosted voltage through an output terminal Po.

  For example, a battery voltage output from an in-vehicle battery, a power supply voltage generated from the battery voltage, or the like is supplied to the input terminal Pi as the input voltage Vi. The output voltage Vo output from the output terminal Po is supplied to a load circuit (not shown). In the present embodiment, among the components of the charge pump circuit 1, the configuration excluding the capacitor Co is configured as a semiconductor integrated circuit, that is, an IC. The capacitor Co may be built in the IC.

  Between the input power supply line Li connected to the input terminal Pi and the output power supply line Lo connected to the output terminal Po, diodes D1, D2, and D3 are connected in series with the input power supply line Li side as an anode. Yes. One terminal of the capacitor C1 is connected to the connection point N1 where the diodes D1 and D2 are connected to each other. One terminal of a capacitor C2 is connected to a connection point N2 where the diodes D2 and D3 are connected to each other. A smoothing capacitor Co is connected between the cathode of the diode D3, that is, the output power supply line Lo, and the reference potential of the circuit, that is, the ground line Lg to which 0V is applied.

  The diodes D1 to D3 correspond to a plurality of switching elements connected in series between the input terminal Pi and the output terminal Po. The input voltage Vi corresponds to the first voltage, 0V corresponds to the second voltage lower than the first voltage, the input power supply line Li corresponds to the first power supply line, and the output power supply line Lo becomes the second power supply line. Equivalent to.

  Input voltages Vi and 0 V are alternately applied to the other terminals of the capacitors C1 and C2 by the operation of the driver 2 corresponding to the drive circuit. The driver 2 includes transistors T1 to T4, which are all N-channel MOS transistors, and a drive unit 7 composed of inverting buffers 3 to 6.

  The drain of the transistor T1 is connected to the input power supply line Li, and the source thereof is connected to the other terminal of the capacitor C1. The drain of the transistor T2 is connected to the other terminal of the capacitor C1, and the source thereof is connected to the ground line Lg. That is, the transistor T1 is provided corresponding to the capacitor C1, and corresponds to a first transistor interposed between the other terminal of the capacitor C1 and the input power supply line Li. The transistor T2 is provided corresponding to the capacitor C1, and corresponds to a second transistor interposed between the other terminal of the capacitor C1 and the ground line Lg.

  The drain of the transistor T3 is connected to the input power supply line Li, and the source thereof is connected to the other terminal of the capacitor C2. The drain of the transistor T4 is connected to the other terminal of the capacitor C2, and its source is connected to the ground line Lg. That is, the transistor T3 corresponds to the first transistor provided corresponding to the capacitor C2 and interposed between the other terminal of the capacitor C2 and the input power supply line Li. The transistor T4 is provided corresponding to the capacitor C2, and corresponds to a second transistor interposed between the other terminal of the capacitor C2 and the ground line Lg.

  The drive unit 7 complementarily turns on and off the transistors T1 and T2 and complementarily turns on and off the transistors T3 and T4 according to the clock signal CLK supplied through the clock terminal Pc. The clock signal CLK is also used in circuits other than the charge pump circuit 1. Therefore, even when an abnormality such as a ground fault occurs in the charge pump circuit 1 as described later, the supply of the clock signal CLK is not immediately stopped and the supply is continued. .

  The inverting buffer 3 receives the clock signal CLK and outputs the inverted signal. The inverting buffers 4 and 5 receive the output signal from the inverting buffer 3 and output the inverted signal. The inverting buffer 6 receives the output signal of the inverting buffer 4 and outputs the inverted signal. The output signal of the inverting buffer 5 is given to the gate of the transistor T1, and the output signal of the inverting buffer 3 is given to the gate of the transistor T2. The output signal of the inverting buffer 6 is given to the gate of the transistor T3, and the output signal of the inverting buffer 4 is given to the gate of the transistor T4.

  According to such a configuration, when one of the transistors T1 and T2 is turned on, the other is turned off, that is, turned on and off in a complementary manner. The transistors T3 and T4 are turned on and off in a complementary manner. Note that “complementarily turned on / off” in this specification does not exclude a case where a so-called dead time is provided during a period in which both transistors are turned off. In this case, the on / off timings of the transistors T1 and T4 are the same, and the on / off timings of the transistors T2 and T3 are the same.

  Here, the inverting buffers 3 and 4 are operated by receiving the input voltage Vi, and the inverting buffers 5 and 6 are voltages of the power supply node N3 connected to the output power supply line Lo, that is, output voltages. It operates by receiving the supply of Vo. For this reason, the high level of the output signal of the inverting buffers 3 and 4 becomes a voltage level equivalent to the input voltage Vi, and the high level of the output signal of the inverting buffers 5 and 6 becomes a voltage level equivalent to the output voltage Vo. That is, the inverting buffers 3 and 4 generate an on-drive voltage for turning on the transistors T2 and T4 using the input voltage Vi, and the inverting buffers 5 and 6 use the output voltage Vo to switch the transistors T1 and T3. An on drive voltage for on driving is generated.

Next, the operation of the above configuration will be described. In the following description, the current flowing from the input terminal Pi to the output terminal Po is referred to as “power supply current”.
[1] State of Each Part at Normal Time As shown in FIG. 2, the output voltage Vo has a voltage value in a desired range at the normal time when no abnormality occurs before time t1. In this case, the power supply current has a waveform with a slight pulsation that occurs at the timing when the clock signal CLK is inverted, but the current value is a value in a range that flows in a steady state.

[2] State of each part at the time of output ground fault When a ground fault occurs between the output terminal Po and the ground at time t1 in FIG. 2, the output voltage Vo becomes 0V. In this case, since an excessive current flows from the input terminal Pi to the output terminal Po via the diodes D1 to D3, the power supply current is higher than the value in the range that flows in the steady state. However, when the output terminal Po is grounded, the voltage of the output power supply line Lo and hence the power supply node N3 becomes 0V, and the drive unit 7 cannot turn on the high-side transistors T1 and T3. Therefore, when the output terminal Po is grounded, the input voltage Vi is not applied to the other terminals of the capacitors C1 and C2.

  Therefore, at the time of the output ground fault, the ripple current that intermittently flows from the capacitors C1 and C2 to the output terminal Po generated by alternately applying the input voltages Vi and 0V to the other terminals of the capacitors C1 and C2 does not occur. Therefore, as shown in FIG. 2, the power supply current becomes an excessive current, but the fluctuation accompanying the ripple current does not occur.

According to this embodiment described above, the following effects can be obtained.
In the charge pump circuit 1 of the present embodiment, the transistors T1 and T3 on the high side of the driving unit 7 are N-channel MOS transistors, and the transistors T1 and T3 are connected to the output power supply line Lo. It is configured to be driven by inversion buffers 5 and 6 that operate upon receiving a voltage supply. According to such a configuration, when the output terminal Po is grounded, the drive unit 7 cannot generate an on-drive voltage for driving the transistors T1 and T3 on. Therefore, at the time of an output ground fault, the input voltage Vi is not applied to the other terminals of the capacitors C1 and C2, and a ripple current that intermittently flows from the capacitors C1 and C2 to the output terminal Po does not occur. Therefore, according to the present embodiment, it is possible to obtain an excellent effect of preventing an excessive current from flowing when the output is grounded.

  Such an effect obtained by the present embodiment is further clarified by comparing with the configuration of the prior art. Therefore, in the following, two comparative examples corresponding to the configuration of the prior art will be described, and those comparative examples and the present embodiment will be compared. In each comparative example, the same reference numerals are given to substantially the same configurations as those of the present embodiment, and the description thereof is omitted.

<First comparative example>
As shown in FIG. 3, in the driver 12 of the charge pump circuit 11 of the first comparative example, the high-side transistors T11 and T13 are P-channel MOS transistors. The drive unit 13 includes inversion buffers 14 to 16 that operate by receiving the supply of the input voltage Vi.

  The inverting buffers 14 and 15 receive the clock signal CLK and output the inverted signal. The inverting buffer 16 receives the output signal of the inverting buffer 15 and outputs the inverted signal. The output signal of the inverting buffer 14 is given to the gates of the transistors T11 and T2, and the output signal of the inverting buffer 16 is given to the gates of the transistors T13 and T4.

<Comparison between the first comparative example and this embodiment>
In the first comparative example, even when the output terminal Po is grounded, the drive unit 13 can turn on and off all the transistors including the high-side transistors T11 and T13 in the same manner as in the normal state. For this reason, the input voltages Vi and 0V are alternately applied to the other terminals of the capacitors C1 and C2 even during an output ground fault, and a ripple current that flows intermittently from the capacitors C1 and C2 to the output terminal Po is generated. As a result, as shown in FIG. 4, a large fluctuation corresponding to the ripple current component occurs in the power supply current at the time of output ground fault. Such large fluctuations in the power supply current may lead to problems such as failure of elements constituting the circuit and increase in radiation noise.

  On the other hand, in the charge pump circuit 1 of the present embodiment, when the output terminal Po is grounded, the ripple current is not generated. Therefore, during an output ground fault, a larger current flows from the input terminal Pi to the output terminal Po than during a steady state, but the current does not fluctuate further. Therefore, according to the present embodiment, it is possible to prevent the failure of the elements constituting the circuit at the time of the output ground fault and to suppress the occurrence of an emission problem such as an increase in radiation noise.

<Second Comparative Example>
As shown in FIG. 5, the driver 22 of the charge pump circuit 21 of the second comparative example has the same configuration as the driver 12 of the first comparative example. However, in this case, an output ground fault detection circuit 23, a filter circuit 24, a NOR circuit 25, and a cutoff switch 26 are added. The output ground fault detection circuit 23 detects a ground fault at the output terminal Po by monitoring the output voltage Vo, and outputs a detection signal that becomes a high level when a ground fault is detected.

  The detection signal output from the output ground fault detection circuit 23 is given to one input terminal of the NOR circuit 25 through the filter circuit 24. The other terminal of the NOR circuit 25 is supplied with the clock signal CLK, and the output signal is supplied to the input terminals of the inverting buffers 14 and 15. The cutoff switch 26 is interposed between the input terminal Pi and the anode of the diode D1, and is turned on when the output signal of the filter circuit 24 is at the low level and turned off when the output signal is at the high level.

<Comparison between the second comparative example and this embodiment>
In the second comparative example, the output voltage Vo is monitored to stop the on-drive of the high-side transistors T11 and T13 by the drive unit 13 in the event of an output ground fault, and the main power supply extends from the input terminal Pi to the output terminal Po. The route is cut off. However, in this case, the filter time in the filter circuit 24 needs to be set. If the filter time is set to a short value, there is a risk of erroneous detection at start-up. If the filter time is set to a long value, a relatively long time is required until detection after a ground fault. There is a risk of device failure. That is, in the charge pump circuit 21 of the second comparative example, it is difficult to achieve both prevention of erroneous detection at startup and improvement of detection accuracy.

  On the other hand, in the charge pump circuit 1 of the present embodiment, when the output terminal Po is grounded, the voltage of the power supply node N3 becomes 0 V accordingly, and thus the high-side transistors T1 and T3 are automatically turned on. A configuration in which driving is impossible is adopted. In other words, in the present embodiment, since the ground fault detection based on the output voltage Vo or the like and the control of stopping the operation of the driver based on the detection result are not necessary, the filter as in the second comparative example is not used. Various problems related to time setting do not occur.

  Further, according to the present embodiment, the circuit for detecting the ground fault of the output terminal Po, which is necessary in the second comparative example, the comparator for binarizing the detection signal, and the like are unnecessary. Compared to the comparative example, it is possible to realize suppression of overcurrent at the time of output ground fault with a simple circuit configuration.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. 6 and 7.
As shown in FIG. 6, the driver 32 of the charge pump circuit 31 according to the present embodiment includes, in addition to the configuration included in the driver 2 according to the first embodiment, constant current circuits 33 to 36 that flow a constant current, a diode D31, D32 is provided. The constant current circuits 33 to 36 control the current flowing between the terminals to be constant. The diodes D31 and D32 correspond to rectifying elements and are provided to prevent backflow from the output terminal Po to the input terminal Pi.

  One terminal of the constant current circuits 33 and 35 is connected to the output power supply line Lo, and one terminal of the constant current circuits 34 and 36 is connected to the input power supply line Li. The other terminal of the constant current circuit 33 is connected to the power supply node N31. The other terminal of the constant current circuit 34 is connected to the power supply node N31 via the diode D31 in the forward direction. The other terminal of the constant current circuit 35 is connected to the power supply node N32. The other terminal of the constant current circuit 36 is connected to the power supply node N32 via the diode D32 in the forward direction.

  With such a configuration, the output voltage Vo is applied to the power supply nodes N31 and N32, and the input voltage Vi is applied via the diodes D31 and D32 in the forward direction. In this case, the inverting buffers 5 and 6 operate by receiving the voltages supplied from the power supply nodes N31 and N32.

  In such a configuration, the constant current circuits 33 to 36 limit the current supplied to the inverting buffers 5 and 6 from the input terminal Pi or the output terminal Po. The constant current circuits 34 and 36 have a function of limiting the current flowing from the input terminal Pi to the output terminal Po through a path not passing through the diodes D1 to D3, for example, when the output terminal Po is grounded. It has and corresponds to a current limiting part.

  Furthermore, the constant current circuits 33 and 35 also have a function of reducing the voltage supplied to the inverting buffers 5 and 6. That is, if the constant current circuits 33 and 35 are not provided, the output voltage Vo itself is supplied to the power supply nodes N31 and N32. Since the output voltage Vo is a voltage obtained by boosting the input voltage Vi, its voltage value is relatively high. Therefore, when the constant current circuits 33 and 35 are not provided, it is necessary to increase the breakdown voltage of the inverting buffers 5 and 6. On the other hand, if the constant current circuits 33 and 35 are provided as in this embodiment, a voltage lower than the output voltage Vo is applied to the power supply nodes N31 and N32 due to the voltage drop, so that the inverting buffers 5 and 6 are provided. There is no need to increase the breakdown voltage.

  As a specific configuration of the constant current circuits 33 to 36, for example, a configuration as shown in FIG. 7 can be adopted. The configuration of FIG. 7A includes transistors T31 and T32 and a current source 37. The transistors T31 and T32 are both P-channel MOS transistors. Between the sources and drains of the transistors T31 and T32, diodes D33 and D34, which are parasitic elements thereof, are connected with the source side as an anode.

  The diodes D33 and D34 do not have to be parasitic elements of the transistors T31 and T32, and separate elements may be provided. The diode D34 corresponds to a voltage limiting unit. Furthermore, when this specific configuration is applied to the constant current circuits 34 and 36, the diodes D33 and D34 may be omitted.

  The transistors T31 and T32 are connected so as to constitute a current mirror circuit. The source of the transistor T31 is connected to the ground line Lg via the current source 37. The drains of the transistors T31 and T32 are connected to the terminal P31. The source of the transistor T32 is connected to the terminal P32. Of the terminals P31 and P32, the terminal P32 is a terminal on the power supply nodes N31 and N32 side. According to such a configuration, the current flowing between the terminals P31 and P32 is controlled to be equal to the current value of the current source 37.

  The configuration of FIG. 7B includes transistors T33 and T34 and a current source 38. The transistors T33 and T34 are both PNP type bipolar transistors. Between the collectors and emitters of the transistors T33 and T34, diodes D35 and D36, which are their parasitic elements, are connected with the collector side as an anode.

  Note that the diodes D35 and D36 do not have to be parasitic elements of the transistors T33 and T34 but may be provided separately. The diode D36 corresponds to a voltage limiting unit. Furthermore, when this specific configuration is applied to the constant current circuits 34 and 36, the diodes D35 and D36 may be omitted.

  The transistors T33 and T34 are connected so as to constitute a current mirror circuit. The collector of the transistor T33 is connected to the ground line Lg via the current source 38. The emitters of the transistors T33 and T34 are connected to the terminal P33. The collector of the transistor T34 is connected to the terminal P34. Of the terminals P33 and P34, the terminal P34 is a terminal on the power supply nodes N31 and N32 side. According to such a configuration, the current flowing between the terminals P33 and P34 is controlled to be equal to the current value of the current source 38.

  In the configuration of the first embodiment, since the capacitor Co is charged by the input voltage Vi and the output voltage Vo is sufficiently increased at startup, the high-side transistors T1 and T3 cannot be turned on, There was room for improvement in the rising speed. In order to improve such a point, in the charge pump circuit 31 of this embodiment, voltage supply to the power supply nodes N31 and N32 is duplicated.

That is, in the charge pump circuit 31, a voltage slightly lower than the input voltage Vi, specifically, the voltage Vs shown in the following equation (1) is applied to the power supply nodes N31 and N32 even when the output voltage Vo is low at the time of startup or the like. Have been supplied. However, the voltage drop by the constant current circuits 34 and 36 is Vd, and the forward voltage of the diodes D31 and D32 is Vf.
Vs = Vi−Vd−Vf (1)

  Therefore, even when the output voltage Vo rises sufficiently at the time of startup, if the input voltage Vi rises until the voltage Vs becomes a voltage at which the inversion buffers 5 and 6 can generate the on-drive voltage, The high-side transistors T1 and T3 can be turned on. Therefore, according to the present embodiment, it is possible to shorten the time required for the output voltage Vo to reach a desired voltage value at the start-up, that is, to increase the rising speed at the start-up.

  In the present embodiment, the constant current circuits 34 and 36 are provided in the paths from the input terminal Pi to the power supply nodes N31 and N32. Therefore, when the output terminal Po is grounded, it flows through a path from the input terminal Pi through the power supply node N31 to the output terminal Po and a path from the input terminal Pi through the power supply node N32 to the output terminal Po. The current can be limited.

  Furthermore, in the present embodiment, as shown in FIG. 7, the constant current circuits 33 and 35 are provided with diodes D34 and D36 whose cathodes are on the terminals P31 and P33 side, that is, on the output terminal Po side. According to such a configuration, when the output terminal Po is grounded, a path “input terminal Pi → constant current circuit 34 → diode D31 → power source node N31 → diode D34 or D36 of constant current circuit 33 → output terminal Po”. Then, a current flows through a path “input terminal Pi → constant current circuit 36 → diode D32 → power supply node N32 → diode D34 or D36 of constant current circuit 35 → output terminal Po”.

  Therefore, at the time of output ground fault, the voltage of the power supply nodes N31 and N32 is limited to a voltage higher than 0V by the forward voltage of the diode D34 or D36, and the drive unit 7 is turned on to drive the transistors T1 and T3 on. The voltage cannot be generated. Therefore, according to this embodiment, the same effect as that of the first embodiment, that is, an effect that an excessive current can be prevented from flowing when the output is grounded can be obtained.

(Third embodiment)
The third embodiment will be described below with reference to FIG.
As shown in FIG. 8, the charge pump circuit 41 of the present embodiment has a current limit circuit 42 corresponding to the main path current limiting unit added to the charge pump circuit 31 of the second embodiment. The current limit circuit 42 is provided so as to be interposed in series between the input power supply line Li and the anode of the diode D1. The current limit circuit 42 limits the current of the main path from the input terminal Pi to the output terminal Po via the diodes D1 to D3.

  According to such a configuration, when the output terminal Po is grounded, the current flowing from the input terminal Pi to the output terminal Po via the diodes D1 to D3 is limited. Also in this case, as in the first embodiment, a ripple current that intermittently flows from the capacitors C1 and C2 to the output terminal Po does not occur during an output ground fault. Therefore, according to this embodiment, the power supply current that flows when the output is grounded can be further reduced.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIG.
As shown in FIG. 9, the driver 52 of the charge pump circuit 51 of the present embodiment has a configuration on the high side that is different from the driver 2 of the first embodiment. That is, the high-side transistors T51 and T52 are both P-channel MOS transistors. The source of the transistor T51 is connected to the input power supply line Li, and the drain thereof is connected to the other terminal of the capacitor C1. The source of the transistor T52 is connected to the input power supply line Li, and the drain thereof is connected to the other terminal of the capacitor C2.

  A resistor R51 is connected between the source and gate of the transistor T51. The gate of the transistor T51 is connected to the drain of the transistor T53, which is an N-channel MOS transistor. The source of the transistor T53 is connected to the ground line Lg.

  The gate of the transistor T53 is connected to the power supply node N3 via the resistor R52, and is connected to the drain of the transistor T54 which is an N-channel type MOS transistor. The source of the transistor T54 is connected to the ground line Lg, and the output signal of the inverting buffer 3 is given to the gate thereof.

  A resistor R53 is connected between the source and gate of the transistor T52. The gate of the transistor T52 is connected to the drain of the transistor T55, which is an N-channel MOS transistor. The source of the transistor T55 is connected to the ground line Lg.

  The gate of the transistor T55 is connected to the power supply node N3 via the resistor R54, and is connected to the drain of the transistor T56, which is an N-channel MOS transistor. The source of the transistor T56 is connected to the ground line Lg, and the output signal of the inverting buffer 4 is given to the gate thereof.

  In this case, transistors T51 and T53 correspond to the first transistor provided corresponding to capacitor C1, and transistors T52 and T55 correspond to the first transistor provided corresponding to capacitor C2. The inversion buffers 3 and 4, the transistors T54 and T56, and the resistors R52 and R54 constitute a drive unit 53.

  According to such a configuration, when the output terminal Po is grounded, the drive unit 53 cannot generate an on-drive voltage for turning on the transistors T53 and T55, and thus the transistors T51 and T52 are turned on. Can not do. Therefore, at the time of an output ground fault, the input voltage Vi is not applied to the other terminals of the capacitors C1 and C2, and a ripple current that intermittently flows from the capacitors C1 and C2 to the output terminal Po does not occur. Therefore, also in the present embodiment, as in the first embodiment, it is possible to prevent an excessive current from flowing when the output is grounded.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above and described in drawing, In the range which does not deviate from the summary, it can change, combine or expand arbitrarily.
In the second embodiment, the specific configuration of the constant current circuits 33 to 36 is not limited to that shown in FIG. 7 and can be changed as appropriate. Further, a resistor element may be provided instead of the constant current circuits 33 to 36, and the current may be limited by the resistor element. Further, the constant current circuits 33 and 35 may be omitted if the inversion buffers 5 and 6 are allowed to have a high breakdown voltage.

  The plurality of switching elements connected in series between the input terminal Pi and the output terminal Po are not limited to the diodes D1 to D3, and may be switching elements such as MOS transistors, for example.

A current limit circuit 42 may be added to the charge pump circuit 31 of the second embodiment and the charge pump circuit 51 of the fourth embodiment.
The present invention can be applied to all charge pump circuits that boost the input voltage input through the input terminal and output the boosted voltage through the output terminal. Therefore, the number of stages of the charge pump is not limited to two, and may be three or more.

  DESCRIPTION OF SYMBOLS 1, 31, 41, 51 ... Charge pump circuit 2, 32, 52 ... Driver, 7, 53 ... Drive part, C1, C2 ... Capacitor, D1-D3 ... Diode, Lg ... Ground line, Li ... Input power supply line, N3, N31, N32... Power supply node, T1 to T4, T51, T52, T53, T55.

Claims (8)

A charge pump circuit (1, 31, 41, 51) that boosts an input voltage input through an input terminal (Pi) and outputs the boosted voltage through an output terminal (Po),
A plurality of switching elements (D1, D2, D3) connected in series between the input terminal and the output terminal;
A plurality of capacitors (C1, C2) each having one terminal connected to each connection point where the switching elements are connected;
A first transistor (T1, T3, T51, T52) provided corresponding to each of the plurality of capacitors and interposed between the other terminal of the capacitor and a first power supply line (Li) for supplying a first voltage. , T53, T55) and a second transistor (T2, T4) interposed between the other terminal of the capacitor and a second power supply line (Lg) for supplying a second voltage lower than the first voltage, and A drive circuit (2, 32, 52) including a drive unit (7, 53) that complementarily turns on and off the first and second transistors;
With
The first transistor is an N-channel MOS transistor,
The driving unit generates a charge for generating an on-drive voltage for driving the first transistor on using a voltage of a power supply node (N3, N31, N32) to which an output voltage output through the output terminal is applied. Pump circuit.   The charge pump circuit according to claim 1, wherein the output voltage is supplied to the power supply nodes (N31, N32), and the input voltage is supplied through a rectifying element (D31, D32) in a forward direction.   The charge pump circuit according to claim 2, further comprising a current limiting unit (34, 36) configured to limit a current flowing from the input terminal to the output terminal through a path not passing through the switching element.   The charge pump circuit according to claim 3, wherein the current limiting unit includes a constant current circuit that allows a constant current to flow.   The charge pump circuit according to claim 3, wherein the current limiting unit includes a resistance element.   When a current flows from the input terminal to the output terminal through a path not passing through the switching element, the voltage of the power supply node is limited to a voltage value lower than a voltage necessary for driving the first transistor on. The charge pump circuit according to any one of claims 3 to 5, further comprising a voltage limiting unit (D34, D36).   The charge according to any one of claims 1 to 6, further comprising a main path current limiting unit (42) configured to limit a current flowing from the input terminal to the output terminal via a path via the switching element. Pump circuit. The drive unit turns on and off the first and second transistors according to a clock signal,
The charge pump circuit according to any one of claims 1 to 7, wherein the clock signal is supplied even in an abnormality in which an abnormality in which the output terminal has a ground fault occurs.

Images