JP2017130654A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2017130654A JP2017130654A JP2017002257A JP2017002257A JP2017130654A JP 2017130654 A JP2017130654 A JP 2017130654A JP 2017002257 A JP2017002257 A JP 2017002257A JP 2017002257 A JP2017002257 A JP 2017002257A JP 2017130654 A JP2017130654 A JP 2017130654A
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Classifications
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- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
Abstract
Description
本実施の形態では、半導体装置の一形態を、図1乃至図12を用いて説明する。
本発明の一態様である容量素子を使用した、半導体装置(記憶装置)の一例を図1乃至図8に示す。なお、図6(A)は、図1乃至図4を回路図で表したものである。図7は、図1乃至図4に示す半導体装置が形成される領域の端部を示す。
図6(A)、および図1乃至図4に示す半導体装置は、トランジスタ300と、トランジスタ200、および容量素子100を有している。
図6(B)に示す半導体装置は、トランジスタ300を有さない点で図6(A)に示した半導体装置と異なる。この場合も図6(A)に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。
本発明の一態様の半導体装置は、図1に示すようにトランジスタ300、トランジスタ200、容量素子100を有する。トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。
また、本実施の形態の変形例として、図2に示すように、導電体244、および導電体246を形成してもよい。つまり、絶縁体280にプラグとなる導電体244を埋め込み、導電体244上に、バリア性を有する導電体を用いて、配線となる導電体246を設けてもよい。なお、この場合、導電体246は、バリア性だけでなく、耐酸化性が高い導電体を用いることが好ましい。当該構成とすることで、バリア性を有する導電体を用いて、配線を形成することで、バリア層281を別途設ける必要はない。
また、本実施の形態の変形例の一例を、図3に示す。図3は、図1と、トランジスタ300、およびトランジスタ200の構成が異なる。
また、本実施の形態の変形例の一例を、図4に示す。図4は、図2と、トランジスタ300、およびトランジスタ200の構成が異なる。
また、本実施の形態の変形例の一例を、図5に示す。図5は、図4と、トランジスタ200の構成が異なる。
本実施の形態では、上記構成例で示した半導体装置の作製方法の一例について、図8乃至図19を用いて説明する。
本実施の形態では、半導体装置の一形態を、図20乃至図30を用いて説明する。
以下では、本発明の一態様に係るトランジスタの一例について説明する。図20(A)、図20(B)、および図20(C)は、本発明の一態様に係るトランジスタの上面図および断面図である。図20(A)は上面図であり、図20(B)は、図20(A)に示す一点鎖線X1−X2、図20(C)は、一点鎖線Y1−Y2に対応する断面図である。なお、図20(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
図21には、トランジスタ200に適応できる構造の一例を示す。図21(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図21(A)において一部の膜は省略されている。また、図21(B)は、図21(A)に示す一点鎖線X1−X2に対応する断面図であり、図21(C)はY1−Y2に対応する断面図である。
図22には、トランジスタ200に適応できる構造の一例を示す。図22(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図22(A)において一部の膜は省略されている。また、図22(B)は、図22(A)に示す一点鎖線X1−X2に対応する断面図であり、図22(C)はY1−Y2に対応する断面図である。
図23には、トランジスタ200に適応できる構造の一例を示す。図23(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図23(A)において一部の膜は省略されている。また、図23(B)は、図23(A)に示す一点鎖線X1−X2に対応する断面図であり、図23(C)はY1−Y2に対応する断面図である。
図24には、トランジスタ200に適応できる構造の一例を示す。図24(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図24(A)において一部の膜は省略されている。また、図24(B)は、図24(A)に示す一点鎖線X1−X2に対応する断面図であり、図24(C)はY1−Y2に対応する断面図である。
図25には、トランジスタ200に適応できる構造の一例を示す。図25(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図25(A)において一部の膜は省略されている。また、図25(B)は、図25(A)に示す一点鎖線X1−X2に対応する断面図であり、図25(C)はY1−Y2に対応する断面図である。
図26には、トランジスタ200に適応できる構造の一例を示す。図26(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図26(A)において一部の膜は省略されている。また、図26(B)は、図26(A)に示す一点鎖線X1−X2に対応する断面図であり、図26(C)はY1−Y2に対応する断面図である。
以下に、図20に示したトランジスタの作製方法の一例を図27乃至図30を参照して説明する。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する酸化物半導体について、図34乃至図39を用いて以下説明を行う。
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
次に、酸化物半導体のキャリア密度について、以下に説明を行う。
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した半導体装置の回路の一例について説明する。
以下では、本発明の一態様に係るトランジスタなどを利用した半導体装置の回路の一例について、図40、および図41を用いて説明する。
図40に示す半導体装置は、トランジスタ3500、配線3006を有する点で先の実施の形態で説明した半導体装置と異なる。この場合も先の実施の形態に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。また、トランジスタ3500としては上記のトランジスタ200と同様のトランジスタを用いればよい。
半導体装置(記憶装置)の変形例について、図41に示す回路図を用いて説明する。
本実施の形態では、上述の実施の形態で説明したOSトランジスタを適用可能な回路構成の一例について、図42乃至図45を用いて説明する。
本実施の形態では、上述の実施の形態で説明したOSトランジスタを有する複数の回路を有する半導体装置の一例について、図46乃至図52を用いて説明する。
本実施の形態においては、本発明の一態様に係るトランジスタや上述した記憶装置などの半導体装置を含むCPUの一例について説明する。
図53に示す半導体装置400は、CPUコア401、パワーマネージメントユニット421および周辺回路422を有する。パワーマネージメントユニット421は、パワーコントローラ402、およびパワースイッチ403を有する。周辺回路422は、キャッシュメモリを有するキャッシュ404、バスインターフェース(BUS I/F)405、及びデバッグインターフェース(Debug I/F)406を有する。CPUコア401は、データバス423、制御装置407、PC(プログラムカウンタ)408、パイプラインレジスタ409、パイプラインレジスタ410、ALU(Arithmetic logic unit)411、及びレジスタファイル412を有する。CPUコア401と、キャッシュ404等の周辺回路422とのデータのやり取りは、データバス423を介して行われる。
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した撮像装置の一例について説明する。
以下では、本発明の一態様に係る撮像装置について説明する。
撮像装置2200が有する1つの画素2211を複数の副画素2212で構成し、それぞれの副画素2212に特定の波長域の光を透過するフィルタ(カラーフィルタ)を組み合わせることで、カラー画像表示を実現するための情報を取得することができる。
以下では、シリコンを用いたトランジスタと、酸化物半導体を用いたトランジスタと、を用いて画素を構成する一例について説明する。各トランジスタは上記実施の形態に示すものと同様のトランジスタを用いることができる。
本実施の形態においては、本発明の一態様に係る半導体ウエハ、チップおよび電子部品について説明する。
図59(A)は、ダイシング処理が行なわれる前の基板711の上面図を示している。基板711としては、例えば、半導体基板(「半導体ウエハ」ともいう。)を用いることができる。基板711上には、複数の回路領域712が設けられている。回路領域712には、本発明の一態様に係る半導体装置や、CPU、RFタグ、またはイメージセンサなどを設けることができる。
チップ715を電子部品に適用する例について、図60を用いて説明する。なお、電子部品は、半導体パッケージ、またはIC用パッケージともいう。電子部品は、端子取り出し方向や、端子の形状に応じて、複数の規格や名称が存在する。
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した電子機器について説明する。
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図61に示す。
110 絶縁体
112 導電体
116 導電体
130 絶縁体
150 絶縁体
200 トランジスタ
205 導電体
205a 導電体
205A 導電体
205b 導電体
205B 導電体
210 絶縁体
212 絶縁体
213 絶縁体
214 絶縁体
216 絶縁体
218 導電体
218a 導電体
218b 導電体
218c 導電体
220 絶縁体
222 絶縁体
224 絶縁体
230 酸化物
230a 酸化物
230A 酸化物
230b 酸化物
230B 酸化物
230c 酸化物
230d 酸化物
240a 導電体
240A 導電膜
240b 導電体
240B 導電層
241a 導電体
241b 導電体
244 導電体
244a 導電体
244A 導電膜
244b 導電体
244B 導電膜
244c 導電体
244d 導電体
246 導電体
250 絶縁体
260 導電体
260a 導電体
260A 導電膜
260b 導電体
260c 導電体
270 絶縁体
271 バリア層
279 絶縁体
280 絶縁体
281 バリア層
281a バリア層
281A バリア膜
281b バリア層
281c バリア層
281d バリア層
282 絶縁体
285 絶縁体
286 絶縁体
290 レジストマスク
292 レジストマスク
294 レジストマスク
296 レジストマスク
300 トランジスタ
311 基板
312 半導体領域
314 絶縁体
316 導電体
318a 低抵抗領域
318b 低抵抗領域
320 絶縁体
322 絶縁体
324 絶縁体
326 絶縁体
328 導電体
328a 導電体
328b 導電体
328c 導電体
330 導電体
330a 導電体
330b 導電体
330c 導電体
350 絶縁体
352 絶縁体
354 絶縁体
356 導電体
356a 導電体
356b 導電体
356c 導電体
358 絶縁体
400 半導体装置
401 CPUコア
402 パワーコントローラ
403 パワースイッチ
404 キャッシュ
405 バスインターフェース
406 デバッグインターフェース
407 制御装置
408 PC
409 パイプラインレジスタ
410 パイプラインレジスタ
411 ALU
412 レジスタファイル
421 パワーマネージメントユニット
422 周辺回路
423 データバス
500 半導体装置
501 記憶回路
502 記憶回路
503 記憶回路
504 回路
509 トランジスタ
510 トランジスタ
512 トランジスタ
513 トランジスタ
515 トランジスタ
517 トランジスタ
518 トランジスタ
519 容量素子
520 容量素子
540 配線
541 配線
542 配線
543 配線
544 配線
711 基板
712 回路領域
713 分離領域
714 分離線
715 チップ
750 電子部品
752 プリント基板
753 半導体装置
754 実装基板
755 リード
800 インバータ
810 OSトランジスタ
820 OSトランジスタ
831 信号波形
832 信号波形
840 破線
841 実線
850 OSトランジスタ
860 CMOSインバータ
900 半導体装置
901 電源回路
902 回路
903 電圧生成回路
903A 電圧生成回路
903B 電圧生成回路
903C 電圧生成回路
903D 電圧生成回路
903E 電圧生成回路
904 回路
905 電圧生成回路
905A 電圧生成回路
905E 電圧生成回路
906 回路
911 トランジスタ
912 トランジスタ
912A トランジスタ
912B トランジスタ
921 制御回路
922 トランジスタ
1901 筐体
1902 筐体
1903 表示部
1904 表示部
1905 マイクロフォン
1906 スピーカー
1907 操作キー
1908 スタイラス
1911 筐体
1912 筐体
1913 表示部
1914 表示部
1915 接続部
1916 操作キー
1921 筐体
1922 表示部
1923 キーボード
1924 ポインティングデバイス
1931 筐体
1932 冷蔵室用扉
1933 冷凍室用扉
1941 筐体
1942 筐体
1943 表示部
1944 操作キー
1945 レンズ
1946 接続部
1951 車体
1952 車輪
1953 ダッシュボード
1954 ライト
2200 撮像装置
2201 スイッチ
2202 スイッチ
2203 スイッチ
2210 画素部
2211 画素
2212 副画素
2212B 副画素
2212G 副画素
2212R 副画素
2220 光電変換素子
2230 画素回路
2231 配線
2247 配線
2248 配線
2249 配線
2250 配線
2253 配線
2254 フィルタ
2254B フィルタ
2254G フィルタ
2254R フィルタ
2255 レンズ
2256 光
2257 配線
2260 周辺回路
2270 周辺回路
2280 周辺回路
2290 周辺回路
2291 光源
2300 シリコン基板
2310 層
2320 層
2330 層
2340 層
2351 トランジスタ
2352 トランジスタ
2353 トランジスタ
2360 フォトダイオード
2361 アノード
2363 低抵抗領域
2370 プラグ
2371 配線
2372 配線
2373 配線
2379 絶縁体
2380 絶縁体
2381 絶縁体
2390a 導電体
2390b 導電体
2390c 導電体
2390d 導電体
2390e 導電体
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
3006 配線
3200 トランジスタ
3500 トランジスタ
4001 配線
4003 配線
4005 配線
4006 配線
4007 配線
4008 配線
4009 配線
4021 層
4023 層
4100 トランジスタ
4200 トランジスタ
4300 トランジスタ
4400 トランジスタ
4500 容量素子
4600 容量素子
Claims (7)
- 第1のトランジスタと、
前記第1のトランジスタ上の第1の絶縁体と、
前記第1の絶縁体上の第2のトランジスタと、
前記第2のトランジスタ上の第2の絶縁体と、
前記第2の絶縁体上の容量素子と、を有し、
前記第1の絶縁体は、酸素、及び水素に対してバリア性を有し、
前記第2のトランジスタは、酸化物半導体を有し、
前記第2の絶縁体は、過剰酸素領域を有し、
前記容量素子は、第1の電極、および第2の電極と、前記第1の電極と第2の電極との間に誘電体を有し、
前記誘電体は、酸素、及び水素に対してバリア性を有する第3の絶縁体を有し、
前記第2のトランジスタが設けられた領域の外縁において、前記第1の絶縁体と、前記第3の絶縁体とが接することにより、前記第2のトランジスタ、および前記第2の絶縁体は、前記第1の絶縁体、及び前記第3の絶縁体とに、包囲されていることを特徴とする半導体装置。 - 請求項1において、
前記第1の絶縁体、および前記第3の絶縁体は、酸化アルミニウムであることを特徴とする半導体装置。 - 請求項1または請求項2に記載の半導体装置を複数個有し、ダイシング用の領域を有する半導体ウエハ。
- 基板上に第1のトランジスタを形成し、
前記第1のトランジスタ上に、酸素、及び水素に対してバリア性を有する第1の絶縁体を形成し、
前記第1の絶縁体上に、第1の導電体を形成し、
前記第1の導電体上に、第2の絶縁体を形成し、
前記第2の絶縁体上に、high−k材料を用いて第3の絶縁体を形成し、
前記第3の絶縁体上に、第4の絶縁体を形成し、
前記第4の絶縁体上に、第1の酸化物半導体を形成し、
前記第1の酸化物半導体上に、第2の導電体を形成し、
前記第2の導電体を、島状に加工し、
前記島状の第2の導電体をマスクとして、前記第1の酸化物半導体を、島状に加工し、
前記島状の第2の導電体を加工することで、第3の導電体、および第4の導電体を形成し、
前記第1の酸化物半導体、前記第3の導電体、および前記第4の導電体上に、第2の酸化物半導体を形成した後、加熱処理を行い、
前記第2の酸化物半導体上に、第5の絶縁体を形成し、
前記第5の絶縁体上に、島状の第5の導電体を形成することで、第2のトランジスタを形成し、
前記第2のトランジスタ上に、第6の絶縁体を形成し、
前記第6の絶縁体に、前記第2のトランジスタに達する開口を形成し、
前記開口、および前記第6の絶縁体上に、第6の導電体を形成し、
前記第6の導電体上に、酸素、及び水素に対してバリア性を有するバリア層を形成し、
前記バリア層、および前記第6の絶縁体に対して、酸素プラズマ処理を行った後、前記バリア層、および前記第6の絶縁体上に、酸素、及び水素に対してバリア性を有する第7の絶縁体を形成し、
前記第7の絶縁体を介して、前記第6の導電体と重畳する領域に、第7の導電体を形成することで、容量を形成することを特徴とする半導体装置の作製方法。 - 請求項4において、
前記バリア層は、ALD法により形成された窒化タンタルであることを特徴とする半導体装置の作製方法。 - 請求項4において、
前記バリア層は、ALD法により形成された酸化アルミニウムであることを特徴とする半導体装置の作製方法。 - 請求項4乃至請求項6のいずれか一項において、
前記第7の導電体は、スパッタリング法により形成された酸化アルミニウムであることを特徴とする半導体装置の作製方法。
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