JP2017040561A - Semiconductor chip testing device and semiconductor chip testing method - Google Patents

Semiconductor chip testing device and semiconductor chip testing method Download PDF

Info

Publication number
JP2017040561A
JP2017040561A JP2015162476A JP2015162476A JP2017040561A JP 2017040561 A JP2017040561 A JP 2017040561A JP 2015162476 A JP2015162476 A JP 2015162476A JP 2015162476 A JP2015162476 A JP 2015162476A JP 2017040561 A JP2017040561 A JP 2017040561A
Authority
JP
Japan
Prior art keywords
subject
semiconductor chip
gas
jig
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015162476A
Other languages
Japanese (ja)
Other versions
JP6504971B2 (en
Inventor
保志 高木
Yasushi Takagi
保志 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2015162476A priority Critical patent/JP6504971B2/en
Publication of JP2017040561A publication Critical patent/JP2017040561A/en
Application granted granted Critical
Publication of JP6504971B2 publication Critical patent/JP6504971B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of preventing generation of electrical discharge at a time of measuring electrical characteristics of a test object.SOLUTION: The semiconductor chip testing device is provided with: a lower fixture 8; a contact pin 1; an upper fixture 7 which is disposed above a semiconductor chip 6, which is the test object, and to which the contact pin 1 is secured; an insulation wall 3 that is disposed at a position surrounding side surfaces of the semiconductor chip 6 and is capable of sealing the semiconductor chip 6 cooperatively with the upper fixture 7 and the lower fixture 8; gas injection ports 2 disposed in the upper fixture 7 so as to be capable of injecting an insulation gas toward the surfaces of the semiconductor chip 6; and a gas supply part 12 that supplies the insulation gas to the gas injection ports 2. The gas supply part 12 is configured to supply the insulation gas to the gas injection ports 2 at a preset cycle when the semiconductor chip 6 is placed on the lower fixture 8 without being sealed.SELECTED DRAWING: Figure 1

Description

本発明は、半導体チップのテスト装置およびテスト方法に関するものである。   The present invention relates to a semiconductor chip test apparatus and a test method.

従来の半導体チップテストでは、半導体チップの終端部がシュリンクされ、電極間の距離が短くなると、耐圧試験または遮断試験などの高電圧印加測定時に半導体チップの終端部で放電が起きるなどの問題があった。   In the conventional semiconductor chip test, when the end portion of the semiconductor chip is shrunk and the distance between the electrodes is shortened, there is a problem that discharge occurs at the end portion of the semiconductor chip during high voltage application measurement such as a withstand voltage test or a break test. It was.

例えば、特許文献１には、次のようなプローブ装置が開示されている。被検査チップのおもて側電極（ゲート電極およびソース電極）にそれぞれ対応するプローブ針の先端が接触している状態では、環状突起部の頂部がコンタクトプレートの下面に接触または近接して、コンタクトプレートと載置台との間の隙間が少なくとも雰囲気に関して塞がるようになっている。そして、ガス供給機構からのガス供給により囲繞室内に形成される正圧雰囲気の圧力をさらに効率的に高くすることで、半導体デバイスの電気的特性検査をウエハレベルで行う際にウエハ表面付近でスパーク（放電）が発生することを簡便かつ効率的に防止している。   For example, Patent Document 1 discloses the following probe device. When the tip of the probe needle corresponding to each of the front side electrodes (gate electrode and source electrode) of the chip to be inspected is in contact, the top of the annular protrusion is in contact with or close to the lower surface of the contact plate. The gap between the plate and the mounting table is closed at least with respect to the atmosphere. Further, by increasing the pressure of the positive pressure atmosphere formed in the enclosed chamber by the gas supply from the gas supply mechanism more efficiently, the electrical characteristics of the semiconductor device are sparked in the vicinity of the wafer surface at the wafer level. (Discharge) is easily and efficiently prevented from occurring.

特開２０１５−３５５７７号公報JP 2015-35577 A

しかしながら、半導体チップの表面に異物が付着している場合、半導体チップの電気的特性の測定時に高電圧側のチップ端部とＧＮＤ側のチップ表面電極間に電流経路が発生し放電する可能性がある。   However, if foreign matter adheres to the surface of the semiconductor chip, there is a possibility that a current path is generated between the chip end on the high voltage side and the chip surface electrode on the GND side during electrical characteristic measurement of the semiconductor chip and discharge occurs. is there.

そこで、本発明は、被検体の電気的特性の測定時に放電の発生を抑制することが可能な技術を提供することを目的とする。   Therefore, an object of the present invention is to provide a technique capable of suppressing the occurrence of discharge when measuring the electrical characteristics of a subject.

本発明に係る半導体チップテスト装置は、被検体である半導体チップが載置される下治具と、前記被検体の表面に接触させて前記被検体の電気的特性を測定するためのコンタクトピンと、前記被検体の上側に配置され、かつ、前記コンタクトピンが固定される上治具と、前記被検体の側面を囲む位置に配置され、かつ、前記上治具と前記下治具とで前記被検体を密閉可能な絶縁壁と、前記上治具において、前記被検体の表面に向けて絶縁性ガスを噴出可能に配置されるガス噴出口と、前記ガス噴出口に前記絶縁性ガスを供給するガス供給部とを備え、前記ガス供給部は、前記被検体が前記下治具に載置されかつ前記被検体が密閉されていない状態で、予め定められた周期で前記絶縁性ガスを前記ガス噴出口に供給するものである。   A semiconductor chip test apparatus according to the present invention includes a lower jig on which a semiconductor chip as a subject is placed, a contact pin for measuring the electrical characteristics of the subject in contact with the surface of the subject, The upper jig, which is arranged on the upper side of the subject and to which the contact pin is fixed, is arranged at a position surrounding the side surface of the subject, and the upper jig and the lower jig are used to An insulating wall capable of sealing a specimen, a gas outlet arranged in the upper jig so as to be able to eject an insulating gas toward the surface of the subject, and supplying the insulating gas to the gas outlet A gas supply unit, and the gas supply unit supplies the insulating gas to the gas at a predetermined cycle in a state where the object is placed on the lower jig and the object is not sealed. It is supplied to the spout.

本発明によれば、ガス供給部は、被検体が下治具に載置されかつ被検体が密閉されていない状態で、予め定められた周期で絶縁性ガスをガス噴出口に供給する。   According to the present invention, the gas supply unit supplies the insulating gas to the gas outlet at a predetermined cycle in a state where the subject is placed on the lower jig and the subject is not sealed.

したがって、被検体の表面に異物が付着している場合、被検体の電気的特性の測定時に被検体の端部と表面との間に電流経路が生じ放電する可能性があるが、ガス噴出口から予め定められた周期で絶縁性ガスが被検体の表面に向けて噴出される。これにより、被検体の表面に付着した異物を除去することができるため、被検体の電気的特性の測定時に放電が発生することを抑制できる。   Therefore, if foreign matter is attached to the surface of the subject, there is a possibility that a current path will be generated between the end of the subject and the surface during measurement of the electrical characteristics of the subject and the discharge may occur. Insulating gas is ejected toward the surface of the subject at a predetermined cycle. As a result, the foreign matter adhering to the surface of the subject can be removed, so that it is possible to suppress the occurrence of discharge when measuring the electrical characteristics of the subject.

実施の形態１に係る半導体チップテスト装置（コンタクト前）の断面図である。1 is a cross-sectional view of a semiconductor chip test apparatus (before contact) according to a first embodiment. 半導体チップテスト装置（コンタクト時）の断面図である。It is sectional drawing of a semiconductor chip test apparatus (at the time of contact). 下治具の平面図である。It is a top view of a lower jig. 上治具の底面図である。It is a bottom view of an upper jig.

＜実施の形態１＞
本発明の実施の形態１について、図面を用いて以下に説明する。図１は、実施の形態１に係る半導体チップテスト装置の断面図であり、コンタクト前、すなわち、半導体チップの電気的特性の測定における直前の状態を示す図である。図２は、半導体チップテスト装置の断面図であり、コンタクト時、すなわち、半導体チップの電気的特性の測定時の状態を示す図である。図３は、下治具８の平面図であり、図４は、上治具７の底面図である。 <Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of the semiconductor chip test apparatus according to the first embodiment, showing a state before contact, that is, immediately before measurement of electrical characteristics of a semiconductor chip. FIG. 2 is a cross-sectional view of the semiconductor chip test apparatus, and shows a state at the time of contact, that is, at the time of measuring the electrical characteristics of the semiconductor chip. FIG. 3 is a plan view of the lower jig 8, and FIG. 4 is a bottom view of the upper jig 7.

図１に示すように、下治具８、コンタクトピン１、上治具７、絶縁壁３、ガス噴出口２、ガス供給部１２、排気口４、吸着口５、および排気部１４を備えている。   As shown in FIG. 1, a lower jig 8, a contact pin 1, an upper jig 7, an insulating wall 3, a gas outlet 2, a gas supply unit 12, an exhaust port 4, an adsorption port 5, and an exhaust unit 14 are provided. Yes.

図１と図３に示すように、下治具８は、被検体である半導体チップ６を載置するための台座である。下治具８には、排気口４および吸着口５が設けられている。吸着口５は、下治具８に対して上下方向に貫通状に形成され、吸着口５の一端は、下治具８における半導体チップ６が載置される領域の内側に形成されている。吸着口５の他端は、排気管１４ａを介して排気部１４と接続され、排気部１４の駆動により吸着口５を介して半導体チップ６を吸着して固定する。排気口４は、下治具８に対して上下方向に貫通状に形成され、排気口４の一端は、下治具８における半導体チップ６が載置される領域の外側に設けられている。排気口４の他端は、排気管１４ａを介して排気部１４と接続され、排気部１４の駆動により半導体チップ６の周辺の空気を排気する。   As shown in FIGS. 1 and 3, the lower jig 8 is a pedestal for placing a semiconductor chip 6 as a subject. The lower jig 8 is provided with an exhaust port 4 and an adsorption port 5. The suction port 5 is formed in a vertically penetrating manner with respect to the lower jig 8, and one end of the suction port 5 is formed inside a region of the lower jig 8 where the semiconductor chip 6 is placed. The other end of the suction port 5 is connected to the exhaust unit 14 through the exhaust pipe 14 a, and the semiconductor chip 6 is sucked and fixed through the suction port 5 by driving the exhaust unit 14. The exhaust port 4 is formed in a vertically penetrating manner with respect to the lower jig 8, and one end of the exhaust port 4 is provided outside the region of the lower jig 8 where the semiconductor chip 6 is placed. The other end of the exhaust port 4 is connected to the exhaust unit 14 via the exhaust pipe 14 a, and the air around the semiconductor chip 6 is exhausted by driving the exhaust unit 14.

図１と図４に示すように、上治具７は、半導体チップ６の上側、すなわち、下治具８の上側に配置され、下治具８に対して上下方向に昇降可能に構成されている。上治具７には、コンタクトピン１、ガス噴出口２、および絶縁壁３が設けられている。コンタクトピン１は、下治具８に載置された半導体チップ６の表面に接触させて半導体チップ６の電気的特性を測定するための部材である。コンタクトピン１は、上治具７における半導体チップ６が載置される領域の内側に対応する位置に固定されている。ここで、電気的特性の測定とは、耐圧試験または遮断試験などの高電圧印加測定を含むものである。   As shown in FIGS. 1 and 4, the upper jig 7 is arranged on the upper side of the semiconductor chip 6, that is, on the upper side of the lower jig 8, and is configured to be movable up and down with respect to the lower jig 8. Yes. The upper jig 7 is provided with a contact pin 1, a gas outlet 2, and an insulating wall 3. The contact pin 1 is a member for measuring the electrical characteristics of the semiconductor chip 6 by making contact with the surface of the semiconductor chip 6 placed on the lower jig 8. The contact pin 1 is fixed at a position corresponding to the inside of the region where the semiconductor chip 6 is placed in the upper jig 7. Here, the measurement of electrical characteristics includes high voltage application measurement such as withstand voltage test or interruption test.

絶縁壁３は、上治具７の下面に配置されている。より具体的には、上治具７の下面に溝（図示省略）が形成されており、溝に絶縁壁３が装着されている。また、絶縁壁３は、図３に示すように、平面視にて、半導体チップ６と排気口４よりも外側に配置されており、すなわち、絶縁壁３は、半導体チップ６の側面を囲む位置に配置されている。絶縁壁３は、上治具７とともに下治具８に対して昇降可能に構成されている。図２に示すように、半導体チップ６は、上治具７が下降位置に位置する状態で上治具７と下治具８と絶縁壁３とで密閉される。   The insulating wall 3 is disposed on the lower surface of the upper jig 7. More specifically, a groove (not shown) is formed on the lower surface of the upper jig 7, and the insulating wall 3 is attached to the groove. Further, as shown in FIG. 3, the insulating wall 3 is disposed outside the semiconductor chip 6 and the exhaust port 4 in a plan view. That is, the insulating wall 3 surrounds the side surface of the semiconductor chip 6. Is arranged. The insulating wall 3 is configured to be movable up and down with respect to the lower jig 8 together with the upper jig 7. As shown in FIG. 2, the semiconductor chip 6 is sealed with the upper jig 7, the lower jig 8, and the insulating wall 3 in a state where the upper jig 7 is located at the lowered position.

ガス噴出口２は、上治具７に対して上下方向に貫通状に形成され、ガス噴出口２の一端は、下治具８に載置された半導体チップ６の表面に向けられている。より具体的には、ガス噴出口２は複数（例えば２つ）設けられ、一方は、図１において半導体チップ６の中心に対して左上に配置され右下に向けられている。他方は、図１において半導体チップ６の中心に対して右上に配置され左下に向けられている。ガス噴出口２の他端は供給管１２ａを介してガス供給部１２と接続されている。ガス供給部１２は、ガス噴出口２に絶縁性ガスを供給し、ガス噴出口２から半導体チップ６の表面に向けて絶縁性ガスを噴出させる。ここで、絶縁性ガスとは、例えばＳＦ６（六フッ化硫黄）である。   The gas ejection port 2 is formed in a vertically penetrating manner with respect to the upper jig 7, and one end of the gas ejection port 2 is directed to the surface of the semiconductor chip 6 placed on the lower jig 8. More specifically, a plurality of (for example, two) gas ejection ports 2 are provided, and one of them is arranged at the upper left with respect to the center of the semiconductor chip 6 in FIG. The other is arranged in the upper right with respect to the center of the semiconductor chip 6 in FIG. The other end of the gas outlet 2 is connected to the gas supply unit 12 through a supply pipe 12a. The gas supply unit 12 supplies an insulating gas to the gas ejection port 2 and ejects the insulating gas from the gas ejection port 2 toward the surface of the semiconductor chip 6. Here, the insulating gas is, for example, SF6 (sulfur hexafluoride).

次に、半導体チップテスト方法について説明する。最初に、上治具７が上昇位置に位置する状態（すなわち、半導体チップ６が密閉されていない状態）で、ガス噴出口２から下治具８に載置された半導体チップ６の表面に向けて予め定められた周期で絶縁性ガスを噴出する（工程ａ）。ガス噴出口２から半導体チップ６の表面に向けて絶縁性ガスを噴出することで、半導体チップ６の表面に付着している異物が除去される。ここで、絶縁性ガスの噴出の周期は、例えば５Ｈｚから３０Ｈｚ程度である。また、絶縁性ガスの噴出時間は例えば１秒程度であり、噴出量は例えば１６００Ｐａから３２００Ｐａ程度の圧力である。   Next, a semiconductor chip test method will be described. First, in a state where the upper jig 7 is located at the raised position (that is, in a state where the semiconductor chip 6 is not sealed), it is directed from the gas outlet 2 to the surface of the semiconductor chip 6 placed on the lower jig 8. Insulating gas is ejected at a predetermined cycle (step a). By ejecting the insulating gas from the gas ejection port 2 toward the surface of the semiconductor chip 6, foreign matters attached to the surface of the semiconductor chip 6 are removed. Here, the period of ejection of the insulating gas is, for example, about 5 Hz to 30 Hz. Further, the ejection time of the insulating gas is, for example, about 1 second, and the ejection amount is, for example, a pressure of about 1600 Pa to 3200 Pa.

次に、上治具７を下降させて、上治具７が下降位置に到達すると、コンタクトピン１の先端が半導体チップ６の表面に接触すると同時に絶縁壁３の下端が下治具８の表面に接触する。これにより、上治具７と下治具８と絶縁壁３とで半導体チップ６が密閉される（工程ｂ）。   Next, when the upper jig 7 is lowered and the upper jig 7 reaches the lowered position, the tip of the contact pin 1 contacts the surface of the semiconductor chip 6 and at the same time the lower end of the insulating wall 3 is the surface of the lower jig 8. To touch. Thereby, the semiconductor chip 6 is sealed by the upper jig 7, the lower jig 8, and the insulating wall 3 (step b).

ここで、コンタクトピン１として先端が収縮できるようスプリングを兼ね備えたピンが採用されている。半導体チップ６の厚みのばらつきにより、コンタクトピン１の先端が半導体チップ６の表面に接触していない、または絶縁壁３が下治具８の表面に接触していないことを防ぐためである。また、絶縁壁３として柔らかい部材が採用されている。   Here, a pin having a spring so that the tip can be contracted is employed as the contact pin 1. This is to prevent the tip of the contact pin 1 from being in contact with the surface of the semiconductor chip 6 or the insulating wall 3 from being in contact with the surface of the lower jig 8 due to variations in the thickness of the semiconductor chip 6. Further, a soft member is employed as the insulating wall 3.

次に、ガス供給部１２は、上治具７と下治具８と絶縁壁３とで密閉された空間が予め定められた圧力になるまで絶縁性ガスを供給する。ここで、予め定められた圧力とは、例えば０．３ＭＰａから０．６ＭＰａ程度である。   Next, the gas supply unit 12 supplies the insulating gas until the space sealed by the upper jig 7, the lower jig 8, and the insulating wall 3 reaches a predetermined pressure. Here, the predetermined pressure is, for example, about 0.3 MPa to 0.6 MPa.

次に、密閉された空間を絶縁性ガスにより予め定められた圧力にした状態で、半導体チップ６の電気的特性を測定する（工程ｃ）。半導体チップ６の電気的特性の測定時に最も放電が発生しやすい場所は、電圧を印加したときの高電位面とＧＮＤ面の最短距離である、半導体チップ６の高電圧印加電極端部とＧＮＤ電極端部との間である。半導体チップ６を密閉した空間に絶縁性ガスを満たすことで、半導体チップ６における高電圧印加電極端部とＧＮＤ電極端部との間の絶縁性を高めることができる。これにより、半導体チップ６の電気的特性の測定時に放電が発生することを一層抑制できる。   Next, the electrical characteristics of the semiconductor chip 6 are measured in a state where the sealed space is set to a predetermined pressure with an insulating gas (step c). The place where discharge is most likely to occur when measuring the electrical characteristics of the semiconductor chip 6 is the shortest distance between the high potential surface and the GND surface when a voltage is applied. Between extremes. By filling the space in which the semiconductor chip 6 is sealed with an insulating gas, the insulation between the high voltage application electrode end and the GND electrode end in the semiconductor chip 6 can be enhanced. Thereby, it can further suppress that discharge generate | occur | produces at the time of the measurement of the electrical property of the semiconductor chip 6. FIG.

しかし、ウエハプロセス性能およびウエハ材料の性質向上に伴い、半導体チップ６の終端部がシュリンクされることで電極間の距離が短くなり、絶縁性ガスを満たしても放電する可能性がある。その場合は、絶縁性ガスの圧力を高くすることで放電を抑制することができる。   However, as the wafer process performance and the properties of the wafer material are improved, the end portion of the semiconductor chip 6 is shrunk to shorten the distance between the electrodes, and there is a possibility of discharging even if the insulating gas is filled. In that case, the discharge can be suppressed by increasing the pressure of the insulating gas.

測定後、排気部１４は、密閉された空間に存在する絶縁性ガスを下治具８に設けられた排気口４を介して排気する。なお、絶縁性ガスは下治具８の排気口４から排出されるが、排出された絶縁性ガスを回収し、再度、ガス供給部１２から絶縁性ガスを供給する、すなわち絶縁性ガスを再使用することで、絶縁性ガスの使用量を削減することができる。また、半導体チップ６の吸着と絶縁性ガスの排気について１つの排気部１４が行うことで、装置の小型化および軽量化を図ることができ、ひいては装置の低コスト化を図ることができる。   After the measurement, the exhaust unit 14 exhausts the insulating gas existing in the sealed space through the exhaust port 4 provided in the lower jig 8. The insulating gas is discharged from the exhaust port 4 of the lower jig 8. The discharged insulating gas is collected and supplied again from the gas supply unit 12, that is, the insulating gas is recycled. By using it, the usage-amount of insulating gas can be reduced. Further, the single exhaust unit 14 performs the adsorption of the semiconductor chip 6 and the exhaust of the insulating gas, whereby the apparatus can be reduced in size and weight, and the cost of the apparatus can be reduced.

なお、ガス供給部１２が、上治具７と下治具８と絶縁壁３とで密閉された空間が予め定められた圧力になるまで絶縁性ガスを供給する工程は必須ではなく、この工程を省略することも可能である。   It is not essential that the gas supply unit 12 supply the insulating gas until the space sealed by the upper jig 7, the lower jig 8 and the insulating wall 3 reaches a predetermined pressure. Can be omitted.

以上のように、実施の形態１に係る半導体チップテスト装置および半導体チップテスト方法では、ガス供給部１２は、被検体である半導体チップ６が下治具８に載置されかつ半導体チップ６が密閉されていない状態で、予め定められた周期で絶縁性ガスをガス噴出口２に供給する。   As described above, in the semiconductor chip test apparatus and the semiconductor chip test method according to the first embodiment, the gas supply unit 12 includes the semiconductor chip 6 as the subject placed on the lower jig 8 and the semiconductor chip 6 sealed. In the state which is not carried out, insulating gas is supplied to the gas jet nozzle 2 with a predetermined period.

したがって、半導体チップ６の表面に異物が付着している場合、半導体チップ６の電気的特性の測定時に半導体チップ６の端部と表面との間に電流経路が生じ放電する可能性があるが、ガス噴出口２から予め定められた周期で絶縁性ガスが半導体チップ６の表面に向けて噴出される。これにより、半導体チップ６の表面に付着した異物を除去することができるため、半導体チップ６の電気的特性の測定時に放電が発生することを抑制できる。   Therefore, when foreign matter is attached to the surface of the semiconductor chip 6, there is a possibility that a current path is generated between the end of the semiconductor chip 6 and the surface during measurement of the electrical characteristics of the semiconductor chip 6, and discharge occurs. Insulating gas is ejected from the gas ejection port 2 toward the surface of the semiconductor chip 6 at a predetermined cycle. Thereby, since the foreign material adhering to the surface of the semiconductor chip 6 can be removed, it is possible to suppress the occurrence of discharge when measuring the electrical characteristics of the semiconductor chip 6.

ガス供給部１２は、予め定められた周期で絶縁性ガスをガス噴出口２に供給した後であって、半導体チップ６が密閉された状態で、密閉された空間が予め定められた圧力になるまで絶縁性ガスをガス噴出口２に供給する。   The gas supply unit 12 supplies the insulating gas to the gas outlet 2 at a predetermined cycle, and the sealed space becomes a predetermined pressure in a state where the semiconductor chip 6 is sealed. Insulating gas is supplied to the gas outlet 2 until.

したがって、半導体チップ６を密閉した空間に絶縁性ガスを満たすことで、半導体チップ６における高電圧印加電極端部とＧＮＤ電極端部との間の絶縁性を高めることができる。これにより、半導体チップ６の電気的特性の測定時に放電が発生することを一層抑制できる。   Therefore, by filling the space in which the semiconductor chip 6 is sealed with the insulating gas, the insulation between the high voltage application electrode end and the GND electrode end in the semiconductor chip 6 can be enhanced. Thereby, it can further suppress that discharge generate | occur | produces at the time of the measurement of the electrical property of the semiconductor chip 6. FIG.

＜実施の形態２＞
次に、図１と図２を用いて、実施の形態２に係る半導体チップテスト装置および半導体チップテスト方法について説明する。なお、実施の形態２において、実施の形態１で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 2>
Next, a semiconductor chip test apparatus and a semiconductor chip test method according to the second embodiment will be described with reference to FIGS. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

実施の形態２に係る半導体チップテスト装置は、実施の形態１に係る半導体チップテスト装置と同じ構成であるが、排気部１４の機能が実施の形態１の場合と異なっており、排気部１４は、半導体チップ６が密閉された状態で、密閉された空間の空気を排気し負圧にする。   The semiconductor chip test apparatus according to the second embodiment has the same configuration as that of the semiconductor chip test apparatus according to the first embodiment, but the function of the exhaust unit 14 is different from that in the first embodiment. With the semiconductor chip 6 sealed, the air in the sealed space is exhausted to a negative pressure.

次に、半導体チップテスト方法について説明する。最初に、図１と図２に示すように、上治具７を下降させて、上治具７が下降位置に到達すると、コンタクトピン１の先端が半導体チップ６の表面に接触すると同時に絶縁壁３の下端が下治具８の表面に接触する。これにより、上治具７と下治具８と絶縁壁３とで半導体チップ６が密閉される（工程ｄ）。   Next, a semiconductor chip test method will be described. First, as shown in FIGS. 1 and 2, when the upper jig 7 is lowered and the upper jig 7 reaches the lowered position, the tip of the contact pin 1 comes into contact with the surface of the semiconductor chip 6 and at the same time, the insulating wall. The lower end of 3 comes into contact with the surface of the lower jig 8. Thereby, the semiconductor chip 6 is sealed by the upper jig 7, the lower jig 8, and the insulating wall 3 (step d).

次に、排気部１４は、半導体チップ６が密閉された状態で、密閉された空間の空気を排気口４から排気させることで密閉された空間を負圧にする（工程ｅ）。密閉された空間を負圧にすることで、半導体チップ６の表面に付着した異物が除去され、除去された異物は密閉された空間から排気口４を介して排出される。次に、密閉された空間を負圧にした状態で、半導体チップ６の電気的特性を測定する（工程ｆ）。   Next, the exhaust part 14 makes the sealed space negative pressure by exhausting air in the sealed space from the exhaust port 4 in a state where the semiconductor chip 6 is sealed (step e). By setting the sealed space to a negative pressure, the foreign matter adhering to the surface of the semiconductor chip 6 is removed, and the removed foreign matter is discharged from the sealed space through the exhaust port 4. Next, the electrical characteristics of the semiconductor chip 6 are measured in a state where the sealed space is set to a negative pressure (step f).

以上のように、実施の形態２に係る半導体チップテスト装置および半導体チップテスト方法では、排気部１４は被検体が密閉された状態で、密閉された空間の空気を排気し負圧にする。したがって、負圧にすることで、半導体チップ６の表面に付着した異物を除去し、除去した異物を密閉された空間から排気口４を介して排出することができるため、半導体チップ６の電気的特性の測定時に放電が発生することを抑制できる。   As described above, in the semiconductor chip test apparatus and the semiconductor chip test method according to the second embodiment, the exhaust unit 14 exhausts the air in the sealed space to a negative pressure while the subject is sealed. Therefore, by setting the negative pressure, the foreign matter attached to the surface of the semiconductor chip 6 can be removed, and the removed foreign matter can be discharged from the sealed space through the exhaust port 4. It is possible to suppress the occurrence of discharge during the measurement of characteristics.

また、実施の形態２では、工程ｄを行う前に、実施の形態１の工程ａを行うことも可能である。具体的には、ガス供給部１２は、排気部１４により排気を行う前であって、半導体チップ６が下治具８に載置されかつ半導体チップ６が密閉されていない状態で、予め定められた周期で絶縁性ガスをガス噴出口２に供給する。この場合、半導体チップ６の電気的特性の測定前にも、半導体チップ６の表面に付着した異物を除去することができるため、密閉された空間を負圧にした場合のみよりも、半導体チップ６の電気的特性の測定時に放電が発生することを一層抑制できる。   In the second embodiment, step a in the first embodiment can be performed before performing step d. Specifically, the gas supply unit 12 is determined in advance in a state in which the semiconductor chip 6 is placed on the lower jig 8 and the semiconductor chip 6 is not sealed before being exhausted by the exhaust unit 14. Insulating gas is supplied to the gas outlet 2 at a predetermined cycle. In this case, since the foreign matter adhering to the surface of the semiconductor chip 6 can be removed before the measurement of the electrical characteristics of the semiconductor chip 6, the semiconductor chip 6 is more effective than the case where the sealed space is set to a negative pressure. It is possible to further suppress the occurrence of discharge during the measurement of the electrical characteristics.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

１ コンタクトピン、２ ガス噴出口、３ 絶縁壁、６ 半導体チップ、７ 上治具、８ 下治具、１２ ガス供給部、１４ 排気部。   1 contact pin, 2 gas ejection port, 3 insulating wall, 6 semiconductor chip, 7 upper jig, 8 lower jig, 12 gas supply part, 14 exhaust part.

Claims (6)

被検体である半導体チップが載置される下治具と、
前記被検体の表面に接触させて前記被検体の電気的特性を測定するためのコンタクトピンと、
前記被検体の上側に配置され、かつ、前記コンタクトピンが固定される上治具と、
前記被検体の側面を囲む位置に配置され、かつ、前記上治具と前記下治具とで前記被検体を密閉可能な絶縁壁と、
前記上治具において、前記被検体の表面に向けて絶縁性ガスを噴出可能に配置されるガス噴出口と、
前記ガス噴出口に前記絶縁性ガスを供給するガス供給部と、
を備え、
前記ガス供給部は、前記被検体が前記下治具に載置されかつ前記被検体が密閉されていない状態で、予め定められた周期で前記絶縁性ガスを前記ガス噴出口に供給する、半導体チップテスト装置。 A lower jig on which a semiconductor chip as an object is placed;
A contact pin for contacting the surface of the subject to measure the electrical characteristics of the subject;
An upper jig which is arranged on the upper side of the subject and to which the contact pin is fixed;
An insulating wall disposed at a position surrounding the side surface of the subject and capable of sealing the subject with the upper jig and the lower jig;
In the upper jig, a gas outlet arranged to be able to eject an insulating gas toward the surface of the subject;
A gas supply unit for supplying the insulating gas to the gas outlet;
With
The gas supply unit supplies the insulating gas to the gas outlet at a predetermined cycle in a state where the subject is placed on the lower jig and the subject is not sealed. Chip test device. 前記ガス供給部は、前記予め定められた周期で前記絶縁性ガスを前記ガス噴出口に供給した後であって、前記被検体が密閉された状態で、密閉された空間が予め定められた圧力になるまで前記絶縁性ガスを前記ガス噴出口に供給する、請求項１記載の半導体チップテスト装置。   The gas supply unit is configured to supply the insulating gas to the gas outlet at the predetermined cycle, and in a state where the subject is sealed, the sealed space has a predetermined pressure. The semiconductor chip test apparatus according to claim 1, wherein the insulating gas is supplied to the gas ejection port until it becomes. 被検体である半導体チップが載置される下治具と、
前記被検体の表面に接触させて前記被検体の電気的特性を測定するためのコンタクトピンと、
前記被検体の上側に配置され、かつ、前記コンタクトピンが固定される上治具と、
前記被検体の側面を囲む位置に配置され、かつ、前記上治具と前記下治具とで前記被検体を密閉可能な絶縁壁と、
前記被検体が密閉された状態で、密閉された空間の空気を排気し負圧にする排気部と、
を備える、半導体チップテスト装置。 A lower jig on which a semiconductor chip as an object is placed;
A contact pin for contacting the surface of the subject to measure the electrical characteristics of the subject;
An upper jig which is arranged on the upper side of the subject and to which the contact pin is fixed;
An insulating wall disposed at a position surrounding the side surface of the subject and capable of sealing the subject with the upper jig and the lower jig;
An exhaust part for exhausting the air in the sealed space and making it negative pressure in a state where the subject is sealed;
A semiconductor chip test apparatus. 前記上治具において、前記被検体の表面に向けて絶縁性ガスを噴出可能に配置されるガス噴出口と、
前記ガス噴出口に前記絶縁性ガスを供給するガス供給部と、
をさらに備え、
前記ガス供給部は、前記排気部により排気を行う前であって、前記被検体が前記下治具に載置されかつ前記被検体が密閉されていない状態で、予め定められた周期で前記絶縁性ガスを前記ガス噴出口に供給する、請求項３記載の半導体チップテスト装置。 In the upper jig, a gas outlet arranged to be able to eject an insulating gas toward the surface of the subject;
A gas supply unit for supplying the insulating gas to the gas outlet;
Further comprising
The gas supply unit is configured to perform the insulation at a predetermined cycle before the exhaust is exhausted by the exhaust unit and in a state where the subject is placed on the lower jig and the subject is not sealed. The semiconductor chip test apparatus according to claim 3, wherein a sex gas is supplied to the gas ejection port. （ａ）下治具に載置された被検体である半導体チップの表面に向けて予め定められた周期で絶縁性ガスを噴出する工程と、
（ｂ）前記被検体の上側に配置された上治具と、前記下治具と、前記被検体の側面を囲む位置に配置された絶縁壁とで前記被検体を密閉する工程と、
（ｃ）前記被検体を密閉した状態で前記被検体の電気的特性を測定する工程と、
を備える、半導体チップテスト方法。 (A) a step of ejecting an insulating gas at a predetermined cycle toward the surface of a semiconductor chip that is an object placed on a lower jig;
(B) sealing the subject with an upper jig arranged on the upper side of the subject, the lower jig, and an insulating wall arranged at a position surrounding the side surface of the subject;
(C) measuring the electrical characteristics of the subject in a state where the subject is sealed;
A semiconductor chip test method comprising: （ｄ）被検体である半導体チップが載置された下治具と、前記被検体の上側に配置された上治具と、前記被検体の側面を囲む位置に配置された絶縁壁とで前記被検体を密閉する工程と、
（ｅ）密閉された空間の空気を排気し負圧にする工程と、
（ｆ）密閉された空間を負圧にした状態で前記被検体の電気的特性を測定する工程と、
を備える、半導体チップテスト方法。 (D) The lower jig on which the semiconductor chip as the subject is placed, the upper jig arranged on the upper side of the subject, and the insulating wall arranged at a position surrounding the side surface of the subject. Sealing the subject; and
(E) exhausting the air in the sealed space to a negative pressure;
(F) measuring the electrical characteristics of the subject in a state where the sealed space is under negative pressure;
A semiconductor chip test method comprising:
JP2015162476A 2015-08-20 2015-08-20 Semiconductor chip test apparatus and semiconductor chip test method Active JP6504971B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015162476A JP6504971B2 (en) 2015-08-20 2015-08-20 Semiconductor chip test apparatus and semiconductor chip test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015162476A JP6504971B2 (en) 2015-08-20 2015-08-20 Semiconductor chip test apparatus and semiconductor chip test method

Publications (2)

Publication Number Publication Date
JP2017040561A true JP2017040561A (en) 2017-02-23
JP6504971B2 JP6504971B2 (en) 2019-04-24

Family

ID=58203752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015162476A Active JP6504971B2 (en) 2015-08-20 2015-08-20 Semiconductor chip test apparatus and semiconductor chip test method

Country Status (1)

Country Link
JP (1) JP6504971B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019212707A (en) * 2018-06-01 2019-12-12 三菱電機株式会社 Semiconductor device evaluation apparatus and semiconductor device evaluation method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7422642B2 (en) 2020-10-27 2024-01-26 三菱電機株式会社 Semiconductor test equipment and semiconductor test method

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02106050A (en) * 1988-10-14 1990-04-18 Matsushita Electric Ind Co Ltd Measuring method for semiconductor device and probe apparatus
JPH0637121A (en) * 1992-07-16 1994-02-10 Hitachi Ltd Method and device for removing foreign matter
JPH11238770A (en) * 1998-02-23 1999-08-31 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit inspecting device
JP2000164648A (en) * 1998-11-25 2000-06-16 Miyazaki Oki Electric Co Ltd Electrical property measuring device and method
JP2007050352A (en) * 2005-08-18 2007-03-01 Fujifilm Corp Method and apparatus for removing foreign substance from imaging device
WO2012026036A1 (en) * 2010-08-27 2012-03-01 株式会社アドバンテスト Testing method for semiconductor wafer, semiconductor wafer transport device, and semiconductor wafer testing device
JP2012189674A (en) * 2011-03-09 2012-10-04 Seiko Epson Corp Manufacturing method of electro-optical device, and element substrate inspection device for electro-optical device
JP2013030647A (en) * 2011-07-29 2013-02-07 Sharp Corp High voltage test method
US20130043875A1 (en) * 2011-08-21 2013-02-21 Bruker Nano, Inc. Testing of electroluminescent semiconductor wafers
JP2013258386A (en) * 2012-06-14 2013-12-26 Sharp Corp Inspection device
JP2014145615A (en) * 2013-01-28 2014-08-14 Mitsubishi Electric Corp Semiconductor evaluation device and semiconductor evaluation method
JP2015035577A (en) * 2013-07-11 2015-02-19 東京エレクトロン株式会社 Probe device
JP2015053416A (en) * 2013-09-09 2015-03-19 豊田合成株式会社 Manufacturing method and manufacturing device of group iii nitride semiconductor light emitting element and substrate cleaning method

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02106050A (en) * 1988-10-14 1990-04-18 Matsushita Electric Ind Co Ltd Measuring method for semiconductor device and probe apparatus
JPH0637121A (en) * 1992-07-16 1994-02-10 Hitachi Ltd Method and device for removing foreign matter
JPH11238770A (en) * 1998-02-23 1999-08-31 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit inspecting device
JP2000164648A (en) * 1998-11-25 2000-06-16 Miyazaki Oki Electric Co Ltd Electrical property measuring device and method
JP2007050352A (en) * 2005-08-18 2007-03-01 Fujifilm Corp Method and apparatus for removing foreign substance from imaging device
WO2012026036A1 (en) * 2010-08-27 2012-03-01 株式会社アドバンテスト Testing method for semiconductor wafer, semiconductor wafer transport device, and semiconductor wafer testing device
JP2012189674A (en) * 2011-03-09 2012-10-04 Seiko Epson Corp Manufacturing method of electro-optical device, and element substrate inspection device for electro-optical device
JP2013030647A (en) * 2011-07-29 2013-02-07 Sharp Corp High voltage test method
US20130043875A1 (en) * 2011-08-21 2013-02-21 Bruker Nano, Inc. Testing of electroluminescent semiconductor wafers
JP2013258386A (en) * 2012-06-14 2013-12-26 Sharp Corp Inspection device
JP2014145615A (en) * 2013-01-28 2014-08-14 Mitsubishi Electric Corp Semiconductor evaluation device and semiconductor evaluation method
JP2015035577A (en) * 2013-07-11 2015-02-19 東京エレクトロン株式会社 Probe device
JP2015053416A (en) * 2013-09-09 2015-03-19 豊田合成株式会社 Manufacturing method and manufacturing device of group iii nitride semiconductor light emitting element and substrate cleaning method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019212707A (en) * 2018-06-01 2019-12-12 三菱電機株式会社 Semiconductor device evaluation apparatus and semiconductor device evaluation method
JP7038605B2 (en) 2018-06-01 2022-03-18 三菱電機株式会社 Semiconductor device evaluation device and semiconductor device evaluation method

Also Published As

Publication number Publication date
JP6504971B2 (en) 2019-04-24

Similar Documents

Publication Publication Date Title
JP4369963B2 (en) Inspecting method of insulator for spark plug
KR101799990B1 (en) Probe apparatus
JP6084469B2 (en) Semiconductor evaluation apparatus and semiconductor evaluation method
JP4557814B2 (en) Plasma processing equipment
US9291664B2 (en) Device for high voltage testing of semiconductor components
WO2013183741A1 (en) Substrate inspection device
TW201333472A (en) Semiconductor testing apparatus
JP6504971B2 (en) Semiconductor chip test apparatus and semiconductor chip test method
KR20150009876A (en) Leak inspection apparatus for battery and inspection method of a leak of the battery using the same
TWI494575B (en) Check the device
CN106415292B (en) Radio frequency test seat
WO2014112215A1 (en) Pressure resistance measuring apparatus and pressure resistance measuring method
CN111223792A (en) Chemical liquid supply device and semiconductor processing device having the same
JP7038605B2 (en) Semiconductor device evaluation device and semiconductor device evaluation method
KR101371982B1 (en) Test system using vacuum and fluid, and method thereof
CN114859199A (en) Auxiliary mechanism for high-voltage testing device of semiconductor device and testing method
CN107870294B (en) Evaluation device and evaluation method of semiconductor device
JP6223317B2 (en) Semiconductor inspection apparatus and semiconductor inspection method
JP2016004912A (en) Measuring apparatus, measuring method
CN117146893B (en) Air tightness insulation detection device and detection method thereof
JP6747374B2 (en) Semiconductor device evaluation apparatus and semiconductor device evaluation method
TW202232618A (en) Evaluating a contact between a wafer and an electrostatic chuck
JP2022156307A (en) Contactor and semiconductor inspection device
KR101680219B1 (en) Proving chamber and proving method
JP2019168424A (en) Connection terminal and method for inspecting semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20171106

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180809

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180821

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181003

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190226

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190326

R150 Certificate of patent or registration of utility model

Ref document number: 6504971

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250