JP6504971B2 - Semiconductor chip test apparatus and semiconductor chip test method - Google Patents

Description

  The present invention relates to a test apparatus and test method for a semiconductor chip.

  In the conventional semiconductor chip test, there is a problem that when the terminal end of the semiconductor chip is shrunk and the distance between the electrodes becomes short, discharge occurs at the terminal end of the semiconductor chip at the time of high voltage application measurement such as withstand voltage test or interruption test. The

  For example, Patent Document 1 discloses the following probe apparatus. When the tip of the probe needle corresponding to the front side electrode (gate electrode and source electrode) of the chip to be inspected is in contact, the top of the annular projection contacts or approaches the lower surface of the contact plate. The gap between the plate and the mounting table is at least closed with respect to the atmosphere. Then, the pressure of the positive pressure atmosphere formed in the enclosure by the gas supply from the gas supply mechanism is increased more efficiently, so that the electric characteristic inspection of the semiconductor device is performed at the wafer level when the spark is observed near the wafer surface. (Discharge) is prevented simply and efficiently from occurring.

JP, 2015-35577, A

  However, if foreign matter adheres to the surface of the semiconductor chip, a current path may be generated between the chip end on the high voltage side and the chip surface electrode on the GND side during measurement of the electrical characteristics of the semiconductor chip, and discharge may occur. is there.

  Then, an object of the present invention is to provide art which can control generating of electric discharge at the time of measurement of an electrical property of a subject.

A semiconductor chip test apparatus according to the present invention comprises: a lower jig on which a semiconductor chip as a subject is mounted; An upper jig disposed on the upper side of the subject and to which the contact pin is fixed, and a position surrounding the side surface of the subject, and the upper jig and the lower jig perform the subject An insulating wall capable of sealing a sample, a gas outlet formed vertically penetrating with respect to the upper jig , and disposed so as to be able to eject an insulating gas toward the surface of the subject, the gas And a gas supply unit for supplying the insulating gas to a jet nozzle, wherein the gas supply unit is predetermined in a state where the subject is placed on the lower jig and the subject is not sealed. cycle in supplying the insulating gas to the gas port The insulating gas is injected toward the surface of the subject, and in the state where the subject is sealed, the insulating gas is injected into the gas jet port until the sealed space reaches a predetermined pressure. Supply and spout .
In another semiconductor chip test apparatus according to the present invention, a lower jig on which a semiconductor chip which is a subject is mounted and a surface of the subject are brought into contact to measure electrical characteristics of the subject Contact pins, an upper jig disposed above the subject, and an upper jig to which the contact pins are fixed, and a position surrounding a side surface of the subject, and the upper jig and the lower jig And an exhaust unit for exhausting air in a sealed space to a negative pressure in a state in which the subject is sealed, and the upper jig in the upper jig. And a gas supply unit configured to supply the insulating gas to the gas injection port, the gas supply unit configured to discharge the exhaust gas by the exhaust unit. Before the test, the subject is placed on the lower jig Re and wherein in a state in which the subject is not sealed, and supplies the insulating gas to the gas ejection port at a predetermined period.
Further, in the semiconductor chip test method according to the present invention, the gas formed vertically penetrating the upper jig in a state where the object is placed on the lower jig and the object is not sealed. A step of spouting an insulating gas at a predetermined cycle toward the surface of the semiconductor chip as the subject from a spout, an upper jig disposed on the upper side of the subject, and the lower jig; And a step of sealing the subject with an insulating wall disposed at a position surrounding the side surface of the subject, and supplying the insulating gas to the gas jet port until the sealed space reaches a predetermined pressure. And a step of measuring an electrical property of the subject in a state in which the subject is sealed.
In another semiconductor chip test method according to the present invention, the object is placed on the lower jig and the object is not sealed, and the object is tested from the gas jet port formed on the upper jig. A step of injecting an insulating gas toward the surface of the semiconductor chip in a predetermined cycle, the lower jig on which the semiconductor chip as the subject is mounted, and the upper side of the subject Sealing the object with the upper jig and an insulating wall disposed at a position surrounding the side surface of the object, exhausting the air in the sealed space to a negative pressure, and the sealing Measuring the electrical characteristics of the subject under negative pressure in the space.

  According to the present invention, the gas supply unit supplies the insulating gas to the gas jet port at a predetermined cycle in a state where the subject is placed on the lower jig and the subject is not sealed.

  Therefore, when foreign matter adheres to the surface of the subject, a current path may be generated between the end of the subject and the surface when the electrical property of the subject is measured, and a discharge may occur. The insulating gas is jetted toward the surface of the subject at a predetermined cycle. As a result, the foreign matter attached to the surface of the subject can be removed, so that the occurrence of the discharge at the time of measurement of the electrical characteristics of the subject can be suppressed.

FIG. 1 is a cross-sectional view of a semiconductor chip test apparatus (before contact) according to a first embodiment. It is sectional drawing of a semiconductor chip test device (at the time of a contact). It is a top view of a lower jig. It is a bottom view of an upper jig.

Embodiment 1
The first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of the semiconductor chip test apparatus according to the first embodiment, showing a state before contact, that is, immediately before measurement of the electrical characteristics of the semiconductor chip. FIG. 2 is a cross-sectional view of the semiconductor chip test apparatus, showing a state at the time of contact, that is, at the time of measurement of the electrical characteristics of the semiconductor chip. FIG. 3 is a plan view of the lower jig 8, and FIG. 4 is a bottom view of the upper jig 7.

  As shown in FIG. 1, the lower jig 8, the contact pin 1, the upper jig 7, the insulating wall 3, the gas jet port 2, the gas supply unit 12, the exhaust port 4, the suction port 5, and the exhaust section 14 There is.

  As shown in FIG. 1 and FIG. 3, the lower jig 8 is a pedestal for mounting the semiconductor chip 6 which is the subject. The lower jig 8 is provided with an exhaust port 4 and a suction port 5. The suction port 5 is formed to penetrate in the vertical direction with respect to the lower jig 8, and one end of the suction port 5 is formed inside the area of the lower jig 8 on which the semiconductor chip 6 is mounted. The other end of the suction port 5 is connected to the exhaust unit 14 via the exhaust pipe 14a, and the semiconductor chip 6 is adsorbed and fixed via the suction port 5 by the drive of the exhaust unit 14. The exhaust port 4 is formed to penetrate vertically to the lower jig 8, and one end of the exhaust port 4 is provided outside the area of the lower jig 8 on which the semiconductor chip 6 is mounted. The other end of the exhaust port 4 is connected to the exhaust unit 14 via the exhaust pipe 14 a, and the air around the semiconductor chip 6 is exhausted by driving the exhaust unit 14.

  As shown in FIGS. 1 and 4, the upper jig 7 is disposed on the upper side of the semiconductor chip 6, that is, the upper side of the lower jig 8, and is configured to be vertically movable relative to the lower jig 8. There is. The upper jig 7 is provided with a contact pin 1, a gas injection port 2, and an insulating wall 3. The contact pin 1 is a member that is brought into contact with the surface of the semiconductor chip 6 mounted on the lower jig 8 to measure the electrical characteristics of the semiconductor chip 6. The contact pin 1 is fixed at a position corresponding to the inside of the region of the upper jig 7 on which the semiconductor chip 6 is mounted. Here, the measurement of the electrical characteristics includes high voltage application measurement such as withstand voltage test or interruption test.

  The insulating wall 3 is disposed on the lower surface of the upper jig 7. More specifically, a groove (not shown) is formed on the lower surface of the upper jig 7, and the insulating wall 3 is attached to the groove. Further, as shown in FIG. 3, the insulating wall 3 is disposed outside the semiconductor chip 6 and the exhaust port 4 in plan view, that is, the insulating wall 3 is a position surrounding the side surface of the semiconductor chip 6. Is located in The insulating wall 3 is configured to be movable up and down with respect to the lower jig 8 together with the upper jig 7. As shown in FIG. 2, the semiconductor chip 6 is sealed by the upper jig 7, the lower jig 8, and the insulating wall 3 in a state where the upper jig 7 is at the lowered position.

  The gas spout 2 is formed to penetrate in the vertical direction with respect to the upper jig 7, and one end of the gas spout 2 is directed to the surface of the semiconductor chip 6 mounted on the lower jig 8. More specifically, a plurality of (for example, two) gas jet outlets 2 are provided, one of which is disposed on the upper left with respect to the center of the semiconductor chip 6 in FIG. 1 and directed to the lower right. The other is disposed on the upper right with respect to the center of the semiconductor chip 6 in FIG. 1 and directed to the lower left. The other end of the gas spout 2 is connected to the gas supply unit 12 via a supply pipe 12a. The gas supply unit 12 supplies the insulating gas to the gas injection port 2 and ejects the insulating gas from the gas injection port 2 toward the surface of the semiconductor chip 6. Here, the insulating gas is, for example, SF6 (sulfur hexafluoride).

  Next, a semiconductor chip test method will be described. First, with the upper jig 7 positioned at the raised position (that is, the state in which the semiconductor chip 6 is not sealed), the gas jet port 2 faces the surface of the semiconductor chip 6 mounted on the lower jig 8. Insulating gas is ejected at a predetermined cycle (step a). By injecting the insulating gas from the gas jet nozzle 2 toward the surface of the semiconductor chip 6, foreign matter adhering to the surface of the semiconductor chip 6 is removed. Here, the discharge period of the insulating gas is, for example, about 5 Hz to 30 Hz. Further, the injection time of the insulating gas is, for example, about 1 second, and the injection amount is, for example, a pressure of about 1600 Pa to 3200 Pa.

  Next, the upper jig 7 is lowered, and when the upper jig 7 reaches the lowered position, the tip of the contact pin 1 contacts the surface of the semiconductor chip 6 and the lower end of the insulating wall 3 is the surface of the lower jig 8 Contact Thus, the semiconductor chip 6 is sealed by the upper jig 7, the lower jig 8 and the insulating wall 3 (step b).

  Here, a pin having a spring is adopted as the contact pin 1 so that the tip can be contracted. This is to prevent the tip of the contact pin 1 from contacting the surface of the semiconductor chip 6 or the insulating wall 3 from contacting the surface of the lower jig 8 due to the variation in thickness of the semiconductor chip 6. Moreover, a soft member is employed as the insulating wall 3.

  Next, the gas supply unit 12 supplies the insulating gas until the space sealed by the upper jig 7, the lower jig 8 and the insulating wall 3 reaches a predetermined pressure. Here, the predetermined pressure is, for example, about 0.3 MPa to about 0.6 MPa.

  Next, the electrical characteristics of the semiconductor chip 6 are measured (step c) with the sealed space at a predetermined pressure by the insulating gas. The place where discharge is most likely to occur when measuring the electrical characteristics of the semiconductor chip 6 is the shortest distance between the high potential surface and the GND surface when a voltage is applied. Between the extreme part. By filling the space in which the semiconductor chip 6 is sealed with the insulating gas, the insulation between the high voltage application electrode end and the GND electrode end in the semiconductor chip 6 can be enhanced. This can further suppress the occurrence of discharge when measuring the electrical characteristics of the semiconductor chip 6.

  However, with the improvement of the wafer process performance and the properties of the wafer material, the terminal portion of the semiconductor chip 6 is shrunk to shorten the distance between the electrodes, and even if the insulating gas is filled, a discharge may occur. In that case, the discharge can be suppressed by increasing the pressure of the insulating gas.

  After the measurement, the exhaust unit 14 exhausts the insulating gas present in the sealed space through the exhaust port 4 provided in the lower jig 8. Although the insulating gas is discharged from the exhaust port 4 of the lower jig 8, the discharged insulating gas is recovered, and the insulating gas is supplied again from the gas supply unit 12, that is, the insulating gas is reopened. By using it, the amount of insulating gas used can be reduced. In addition, since the single exhaust unit 14 performs the adsorption of the semiconductor chip 6 and the exhaust of the insulating gas, the size and weight of the device can be reduced, and the cost of the device can be reduced.

  Note that the step of supplying the insulating gas until the space sealed by the upper jig 7, the lower jig 8 and the insulating wall 3 reaches a predetermined pressure is not essential, and this step is not essential. It is also possible to omit

  As described above, in the semiconductor chip test apparatus and the semiconductor chip test method according to the first embodiment, in the gas supply unit 12, the semiconductor chip 6 as the object is placed on the lower jig 8 and the semiconductor chip 6 is sealed. The insulating gas is supplied to the gas spout 2 at a predetermined cycle in a state where it is not turned on.

  Therefore, when foreign matter adheres to the surface of the semiconductor chip 6, a current path may occur between the end of the semiconductor chip 6 and the surface when the electrical characteristics of the semiconductor chip 6 are measured, and a discharge may occur. An insulating gas is jetted from the gas jet nozzle 2 toward the surface of the semiconductor chip 6 at a predetermined cycle. As a result, the foreign matter attached to the surface of the semiconductor chip 6 can be removed, so that the occurrence of the discharge at the time of measurement of the electrical characteristics of the semiconductor chip 6 can be suppressed.

  The gas supply unit 12 supplies the insulating gas to the gas jet nozzle 2 at a predetermined cycle, and in a state in which the semiconductor chip 6 is sealed, the sealed space has a predetermined pressure. Insulating gas is supplied to the gas spout 2 up to

  Therefore, by filling the space in which the semiconductor chip 6 is sealed with the insulating gas, the insulation between the high voltage application electrode end and the GND electrode end in the semiconductor chip 6 can be enhanced. This can further suppress the occurrence of discharge when measuring the electrical characteristics of the semiconductor chip 6.

Second Embodiment
Next, a semiconductor chip test apparatus and a semiconductor chip test method according to the second embodiment will be described using FIGS. 1 and 2. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The semiconductor chip test apparatus according to the second embodiment has the same configuration as the semiconductor chip test apparatus according to the first embodiment, but the function of the exhaust unit 14 is different from that of the first embodiment, and the exhaust unit 14 is With the semiconductor chip 6 sealed, the air in the sealed space is evacuated to a negative pressure.

  Next, a semiconductor chip test method will be described. First, as shown in FIGS. 1 and 2, when the upper jig 7 is lowered and the upper jig 7 reaches the lowered position, the tip of the contact pin 1 contacts the surface of the semiconductor chip 6 and at the same time the insulating wall The lower end of 3 contacts the surface of the lower jig 8. Thereby, the semiconductor chip 6 is sealed by the upper jig 7, the lower jig 8 and the insulating wall 3 (step d).

  Next, with the semiconductor chip 6 sealed, the exhaust unit 14 exhausts the air in the sealed space from the exhaust port 4 to make the sealed space negative pressure (step e). By applying negative pressure to the sealed space, foreign matter attached to the surface of the semiconductor chip 6 is removed, and the removed foreign matter is discharged from the sealed space through the exhaust port 4. Next, in a state where the sealed space is under negative pressure, the electrical characteristics of the semiconductor chip 6 are measured (step f).

  As described above, in the semiconductor chip test apparatus and the semiconductor chip test method according to the second embodiment, the exhaust unit 14 exhausts the air in the sealed space to a negative pressure in a state in which the object is sealed. Therefore, by applying a negative pressure, foreign matter attached to the surface of the semiconductor chip 6 can be removed, and the removed foreign matter can be discharged from the sealed space through the exhaust port 4. It is possible to suppress the occurrence of discharge when measuring the characteristics.

  Moreover, in the second embodiment, the step a of the first embodiment can be performed before the step d. Specifically, the gas supply unit 12 is previously determined in a state in which the semiconductor chip 6 is mounted on the lower jig 8 and the semiconductor chip 6 is not sealed before exhausting by the exhaust unit 14. Insulating gas is supplied to the gas spout 2 at a constant cycle. In this case, since the foreign matter attached to the surface of the semiconductor chip 6 can be removed even before the measurement of the electrical characteristics of the semiconductor chip 6, the semiconductor chip 6 is more than only when the sealed space is negative pressure. It is possible to further suppress the occurrence of discharge at the time of measurement of the electrical characteristics of

  In the present invention, within the scope of the invention, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

  1 contact pin, 2 gas outlet, 3 insulating wall, 6 semiconductor chip, 7 upper jig, 8 lower jig, 12 gas supply part, 14 exhaust part.

Claims (5)

A lower jig on which a semiconductor chip which is a subject is placed;
A contact pin for contacting the surface of the subject and measuring the electrical property of the subject;
An upper jig disposed on the upper side of the subject and to which the contact pin is fixed;
An insulating wall disposed at a position surrounding the side surface of the subject and capable of sealing the subject by the upper jig and the lower jig;
A gas ejection port formed in a penetrating shape in the vertical direction with respect to the upper jig , and disposed so as to be able to eject an insulating gas toward the surface of the subject;
A gas supply unit for supplying the insulating gas to the gas injection port;
Equipped with
Wherein the gas supply unit, the state where placed on and the subject to the subject is the lower jig is not sealed, by supplying the insulating gas to the gas ejection port in a predetermined cycle The insulating gas is jetted toward the surface of the subject, and the insulating gas is supplied to the gas jet port until the sealed space reaches a predetermined pressure in a state where the subject is sealed. ejecting Te, semiconductor chip test device. A lower jig on which a semiconductor chip which is a subject is placed;
A contact pin for contacting the surface of the subject and measuring the electrical property of the subject;
An upper jig disposed on the upper side of the subject and to which the contact pin is fixed;
An insulating wall disposed at a position surrounding the side surface of the subject and capable of sealing the subject by the upper jig and the lower jig;
An exhaust unit that exhausts air in a sealed space to make the negative pressure in a state in which the subject is sealed;
In the upper jig, a gas ejection port disposed so as to be capable of ejecting an insulating gas toward the surface of the subject;
A gas supply unit for supplying the insulating gas to the gas injection port;
Bei to give a,
The gas supply unit is the insulating device at a predetermined cycle in a state in which the subject is placed on the lower jig and the subject is not sealed before the gas is exhausted by the exhaust unit. supplying sex gas to the gas ejection port, semiconductors chip test device. In a state where the subject is placed on the lower jig and the subject is not sealed , the surface of the semiconductor chip which is the subject from the gas jet formed vertically penetrating to the upper jig. Spouting the insulating gas at a predetermined cycle toward the
A step of sealing the subject with an upper jig which is arranged on the upper side of the front Symbol subject, and the lower jig, and the insulating wall which is disposed at a position surrounding the side face of the subject,
Supplying the insulating gas to the gas outlet and injecting the insulating gas until the sealed space reaches a predetermined pressure;
And measuring the electrical characteristics of the subject in a state sealing the pre Symbol subject,
A semiconductor chip test method comprising: In a state in which the subject is placed on the lower jig and the subject is not sealed, a cycle predetermined from the gas jet port formed on the upper jig toward the surface of the semiconductor chip as the subject Spouting the insulating gas at
Wherein in said lower jig on which the semiconductor chip is mounted is subject wherein said upper jig arranged on the upper side of the subject, and the insulating wall which is disposed at a position surrounding the side face of the subject A process of sealing the subject;
A step of negative pressure to evacuate the air-tight closed spaces,
And measuring the electrical characteristics of the subject while the enclosed space to a negative pressure,
A semiconductor chip test method comprising: 4. The method according to claim 3, further comprising: recovering the insulating gas present in the sealed space, and ejecting the recovered insulating gas from the gas jet port toward the surface of the subject. The semiconductor chip test method as described in 4.

Images