WO2012026036A1 - Testing method for semiconductor wafer, semiconductor wafer transport device, and semiconductor wafer testing device - Google Patents

Testing method for semiconductor wafer, semiconductor wafer transport device, and semiconductor wafer testing device Download PDF

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Publication number
WO2012026036A1
WO2012026036A1 PCT/JP2010/064608 JP2010064608W WO2012026036A1 WO 2012026036 A1 WO2012026036 A1 WO 2012026036A1 JP 2010064608 W JP2010064608 W JP 2010064608W WO 2012026036 A1 WO2012026036 A1 WO 2012026036A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
probe card
testing
holding member
sealed space
Prior art date
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PCT/JP2010/064608
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French (fr)
Japanese (ja)
Inventor
敏之 清川
Original Assignee
株式会社アドバンテスト
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Filing date
Publication date
Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to JP2011525332A priority Critical patent/JP5368565B2/en
Priority to PCT/JP2010/064608 priority patent/WO2012026036A1/en
Priority to TW100121381A priority patent/TW201209429A/en
Publication of WO2012026036A1 publication Critical patent/WO2012026036A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2887—Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates

Definitions

  • the present invention relates to a semiconductor wafer test method for testing an electronic device under test such as an integrated circuit element formed on a semiconductor wafer (hereinafter also referred to as DUT (Device (Under Test)) using a probe card, and
  • DUT Device (Under Test)
  • the present invention relates to a semiconductor wafer transfer apparatus and a semiconductor wafer test apparatus used for testing.
  • a probe card used for a DUT test in a wafer state for example, a cantilever type probe card having a probe needle and a vertical type probe card having a pogo pin are conventionally known (for example, see Patent Document 1). ).
  • the semiconductor wafer in order to ensure electrical contact between the contact of the probe card and the electrode of the semiconductor wafer, the semiconductor wafer is moved toward the probe card by a predetermined amount ( (For example, 100 ⁇ m) It is necessary to push up (overdrive).
  • a predetermined amount (For example, 100 ⁇ m) It is necessary to push up (overdrive).
  • a prober having a chuck for sucking and holding a semiconductor wafer and a Z stage for raising and lowering the chuck is used in a semiconductor wafer test using the probe card.
  • the problem to be solved by the present invention is to provide a semiconductor wafer test method, a semiconductor wafer transfer apparatus, and a semiconductor wafer test apparatus capable of reducing the cost.
  • a method for testing a semiconductor wafer according to the present invention is a method for testing a semiconductor wafer using a probe card, wherein a sealed space is formed between the holding member for holding the semiconductor wafer and the probe card.
  • a sealing step; a decompression step of decompressing the sealed space; and a moving step of moving the holding member by a predetermined amount toward the probe card in a state where the sealed space is decompressed (See claim 1).
  • the probe card may include a cantilever type probe card or a vertical type probe card (see claim 2).
  • the semiconductor wafer testing method includes a detection step of detecting electrical contact between the semiconductor wafer and the probe card, and the moving step is performed based on a detection result in the detection step. It may include moving a member toward the probe card (see claim 3).
  • the moving step may include advancing the holding member toward the probe card by moving means for moving the holding member (see claim 4).
  • the depressurization step is performed so that the adsorption force (F P ) generated along with the depressurization in the sealed space is equal to or less than a necessary pressing force (F N ) required for pressing the probe card ( F P ⁇ F N ), and may include reducing the pressure in the sealed space (see claim 5).
  • the moving step may include retreating the contact means that is in contact with the holding member (see claim 6).
  • the adsorption force (F P ) generated with the pressure reduction in the sealed space is larger than the necessary pressing force (F N ) required for pressing the probe card. (F P > F N ), which may include reducing the pressure in the sealed space (see claim 7).
  • a semiconductor wafer transfer device is a semiconductor wafer transfer device used for testing a semiconductor wafer using a probe card, the holding member holding the semiconductor wafer, the probe card, and the holding member A sealing means for forming a sealed space between them, a decompressing means for decompressing the sealed space, and a movement for moving the holding member relative to the probe card in a state where the sealed space is decompressed by the decompressing means. Means (refer to claim 8).
  • the probe card may include a cantilever type probe card or a vertical type probe card (see claim 9).
  • the holding member may have a mounting surface on which the semiconductor wafer is mounted, and the sealing means may include an annular seal member provided on the mounting surface (see claim 10). ).
  • a semiconductor wafer transfer apparatus is a semiconductor wafer transfer apparatus used for testing a semiconductor wafer using a probe card, the holding member holding the semiconductor wafer, the probe card, and the holding member.
  • a contact means including: a sealing means for forming a sealed space between; a pressure reducing means for reducing the pressure of the sealed space; a contact part that contacts the holding member; and a drive part that moves the contact part. (Refer to claim 11).
  • the probe card may include a cantilever type probe card or a vertical type probe card (see claim 12).
  • the holding member may have a mounting surface on which the semiconductor wafer is mounted
  • the sealing means may include an annular seal member provided on the mounting surface (see claim 13).
  • the driving unit may include a motor connected to a ball screw mechanism or a piezoelectric element (see claim 14).
  • the plurality of contact means may be arranged at substantially equal intervals along the circumferential direction so as to contact the outer peripheral portion of the holding member (see claim 15).
  • a semiconductor wafer test apparatus is a semiconductor wafer test apparatus for testing a semiconductor wafer using a probe card, the test apparatus main body to which the probe card is electrically connected, and the semiconductor wafer described above And a conveying device (see claim 16).
  • the semiconductor wafer and the probe card are brought into electrical contact under reduced pressure, it is not necessary to increase the rigidity of the holding member and the probe card for holding the semiconductor wafer, and the cost can be reduced.
  • the holding member is moved toward the probe card while maintaining the reduced pressure, it is possible to cope with a probe card of a type that requires stroke management.
  • FIG. 1 is a schematic side view showing an overall configuration of a semiconductor wafer test apparatus in a first embodiment of the present invention.
  • FIG. 2 is an enlarged cross-sectional view of a portion II in FIG.
  • FIG. 3 is a plan view showing the wafer prober in the first embodiment of the present invention.
  • 4 is a cross-sectional view taken along line IV-IV in FIG.
  • FIG. 5 is a flowchart showing a semiconductor wafer test method according to the first embodiment of the present invention.
  • FIG. 6 is an enlarged cross-sectional view showing step S12 of FIG.
  • FIG. 7 is an enlarged cross-sectional view showing step S14 of FIG.
  • FIG. 8 is a schematic side view showing the overall configuration of the semiconductor wafer testing apparatus in the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a wafer tray in the second embodiment of the present invention.
  • FIG. 10 is a plan view showing a stage in the second embodiment of the present invention.
  • 11 is a cross-sectional view taken along line XI-XI in FIG.
  • FIG. 12 is a cross-sectional view showing the configuration of the mechanical stopper in the second embodiment of the present invention.
  • FIG. 13 is a bottom view showing the layout of the mechanical stopper in the second embodiment of the present invention.
  • FIG. 14 is a flowchart showing a semiconductor wafer test method according to the second embodiment of the present invention.
  • FIG. 15 is an enlarged sectional view showing steps S22 to S24 in FIG.
  • ⁇ First Embodiment> 1 and 2 are diagrams showing a semiconductor wafer test apparatus in the present embodiment.
  • the semiconductor wafer test apparatus 1 in this embodiment is an apparatus for testing the electrical characteristics of a DUT built in a semiconductor wafer 100. As shown in FIG. 1, a test head 10, an interface assembly 20, and a wafer And a prober 30.
  • the semiconductor probe 100 when testing the DUT, the semiconductor probe 100 is made to face the probe card 21 of the interface assembly 20 by the wafer prober 30, and in this state, the second vacuum pump 42 (see FIG. 3) The semiconductor wafer 100 is brought into contact with the probe card 21 by reducing the pressure in the space 37 (see FIGS. 6 and 7). Further, from this state, the wafer prober 30 pushes the semiconductor wafer 100 toward the probe card 21 by a predetermined amount. When the semiconductor wafer 100 and the probe card 21 are reliably brought into contact with each other by this pushing, a test signal is inputted / outputted from the test head 10 to the DUT of the semiconductor wafer 100 to execute a DUT test.
  • the stroke management required for the cantilever type or vertical type probe card is adopted while adopting the decompression method as a method for bringing the semiconductor wafer 100 and the interface assembly 20 into contact with each other. It also has the function.
  • the interface assembly 20 includes a probe card 21 that is in electrical contact with the semiconductor wafer 100, a performance board 24 connected to the test head 10, and the probe card 21 and the performance board 24. And an interposer 22 that performs pitch conversion of the transmission path.
  • the probe card 21 is a so-called cantilever type probe card having a card substrate 211 on which wiring or the like is formed and a large number of probe needles 212 mounted on the substrate 21.
  • the probe card 21 in the present embodiment is not particularly limited to the above as long as it is of a type that requires a predetermined amount of overdrive after contact with the semiconductor wafer 100.
  • a so-called vertical (vertical) type probe card having a card substrate and a large number of pogo pins standing on the card substrate may be used.
  • the interposer 22 that electrically connects the probe card 21 and the performance board 24 is composed of, for example, a pitch conversion substrate such as a silicon substrate, a ceramic substrate, or a glass substrate, anisotropic conductive rubber, or the like.
  • the narrow pitch on the side is converted into a relatively wide pitch on the performance board 24 side.
  • the interposer 22 is not particularly limited to the above as long as the transmission path pitch conversion is performed between the probe card 21 and the performance board 24.
  • the performance board 24 is electrically connected to the probe card 21 via the interposer 22, it is electrically connected to the pin electronics housed in the test head 10 via a connector, cable, or the like not shown.
  • the test head 10 is electrically connected to a tester (main frame) via a cable, for example.
  • the test head 10 and the tester in the present embodiment correspond to an example of a test apparatus main body in the present invention.
  • An annular seal member 23 is interposed between the upper surface of the probe card 21 and the lower surface of the performance board 24, and an internal space 25 is formed between the probe card 21 and the performance board 24.
  • the interposer 22 is accommodated in the internal space 25.
  • 3 and 4 are views showing a wafer prober in the present embodiment.
  • the wafer prober 30 includes a chuck 33 that holds the semiconductor wafer 100 by suction and a stage 60 that moves the chuck 33 relative to the interface assembly 20.
  • the wafer prober 30 in the present embodiment corresponds to an example of a semiconductor wafer transfer apparatus in the present invention.
  • the chuck 33 is a substantially disk-shaped member having a flat upper surface 331 on which the semiconductor wafer 100 is placed, and the upper surface 331 of the chuck 33 has a larger diameter than the semiconductor wafer 100. have.
  • the chuck 33 in the present embodiment corresponds to an example of the holding member in the present invention.
  • annular grooves 332 On the upper surface 331 of the chuck 33, three annular grooves 332 having a smaller diameter than the semiconductor wafer 100 are formed concentrically. These annular grooves 332 communicate with a suction passage 333 formed in the chuck 33.
  • the suction passage 333 is connected to the first vacuum pump 41 via the suction port 334.
  • the semiconductor wafer 100 is attracted and held by the chuck 33 due to the negative pressure generated in the annular groove 332.
  • the shape and number of the annular grooves 332 are not particularly limited.
  • a pressure reducing passage 335 is formed in the chuck 33.
  • the decompression passage 335 is opened by a suction hole 336 positioned further outside the outermost annular groove 332 on the upper surface 331.
  • the pressure reducing passage 335 is connected to the second vacuum pump 42 via a pressure reducing port 337.
  • the second vacuum pump 42 in the present embodiment corresponds to an example of a decompression unit in the present invention.
  • annular seal member 34 is provided in the vicinity of the outer peripheral portion of the upper surface 331 of the chuck 33.
  • the seal member 34 for example, a packing made of silicone rubber can be exemplified.
  • a sealed space 37 is formed between the upper surface 331 of the chuck 33 and the probe card 21 by the seal member 34.
  • the seal member 34 of this embodiment has a degree of freedom (flexibility) along the Z direction (FIG. 1) that can sufficiently allow the movement of the chuck 33 after the pressure reduction of the second pump 42. ing.
  • a cooling passage 338 is formed in the chuck 33, and a heater 35 and a temperature sensor 36 are embedded.
  • the cooling passage 338 is connected to the chiller 43 via a pair of cooling ports 339.
  • the chuck 33 described above is fixed to the tip of the stage 32.
  • the stage 32 is composed of a motor, a ball screw mechanism, and the like (not shown). As shown in FIG. 1, the stage 32 moves in a three-dimensional manner (XYZ direction) and rotates around the Z axis. It is possible to make it.
  • the stage 32 can move the semiconductor wafer 100 sucked and held by the chuck 33 to a position facing the interface assembly 20 and press it against the probe card 21.
  • the stage 32 in the present embodiment corresponds to an example of a moving unit in the present invention.
  • FIG. 5 is a flowchart showing a semiconductor wafer testing method in the present embodiment
  • FIGS. 6 and 7 are views showing steps S12 and S14 of FIG.
  • step S ⁇ b> 11 of FIG. 5 the stage 32 of the wafer prober 30 moves the chuck 33 holding the semiconductor wafer 100 to a position facing the probe card 21.
  • the stage 32 raises the chuck 33 until the seal member 34 of the chuck 33 comes into close contact with the card substrate 211 of the probe card 21.
  • the stage 32 stops.
  • step S12 of FIG. 5 as shown in FIG. 6, the second vacuum pump 42 is operated to depressurize the sealed space 37.
  • the suction force F P that occurs with the vacuum in the closed space 37 required pressing force required to press all the probes 212 having the probe card 21 F N (e.g.
  • the second vacuum so as to be substantially the same (F P ⁇ F N ) about 200 to 300 [kgf] (about 1.96 ⁇ 10 3 [N] to 2.94 ⁇ 10 3 [N]))
  • the pump 42 is controlled.
  • slightly weaker than the required pressing force F N is attraction force F P (F P ⁇ F N )
  • the test head 10 detects electrical contact between the electrode 110 of the semiconductor wafer 100 and the probe needle 212 of the probe card 21 (step S13). ).
  • step S14 in FIG. 5 using this detection as a trigger, as shown in FIG. 100 ⁇ m). Due to this rise, the probe needle 212 of the probe card 21 bites into the electrode 110 of the semiconductor wafer 100, so that the probe needle 212 and the electrode 110 are reliably in contact with each other.
  • step S15 of FIG. 5 the test head 10 inputs / outputs a test signal to / from the DUT of the semiconductor wafer 100 via the interface assembly 20, whereby the DUT test is executed.
  • a conventional pressing type wafer prober that simply presses a semiconductor wafer against the probe card from below, it is necessary to increase the rigidity of the chuck, stage, and probe card stiffener.
  • the semiconductor wafer 100 and the probe card 21 are brought into electrical contact with each other by decompression, so that the chuck 33, the stage 32, or the probe card 21 is compared with the chuck of a conventional pressing type prober.
  • the rigidity of the stiffener can be reduced, and the cost of the semiconductor wafer test apparatus 1 can be reduced.
  • the chuck 33 is raised by the stage 32 while maintaining the reduced pressure, so that it is possible to cope with a case where a probe card of a type that requires stroke management is used.
  • the probe needle 212 may be plastically deformed.
  • Second Embodiment 8 is a schematic side view showing the overall configuration of the semiconductor wafer testing apparatus in the present embodiment
  • FIG. 9 is a cross-sectional view showing a wafer tray in the present embodiment
  • FIGS. 10 and 11 are views showing a stage in the present embodiment
  • FIG. FIG. 13 is a sectional view showing the configuration of the mechanical stopper in the present embodiment
  • FIG. 13 is a bottom view showing the layout of the mechanical stopper in the present embodiment.
  • the semiconductor wafer test apparatus 1B in this embodiment includes a test head 10, an interface assembly 20, and a wafer prober 30B as shown in FIG. Since the configuration of the test head 10 and the interface assembly 20 is the same as that of the first embodiment, the same reference numerals are given and description thereof is omitted.
  • the wafer tray 50 is attached to the stage 60 instead of the chuck 33, and (2) a front end holding portion 61 that detachably holds the wafer tray 50 is provided on the stage 60. Furthermore, (3) it is different from the first embodiment in that it includes a mechanical stopper 70 that comes into contact with the wafer tray 50.
  • the wafer tray 50 in this embodiment has a configuration similar to that of the chuck 33 described in the first embodiment. As shown in FIG. 9, the wafer tray 50 has a substantially circular shape having a flat upper surface 501 on which the semiconductor wafer 100 is placed. It is a plate-like member, and the upper surface 501 of the wafer tray 50 has a larger diameter than the semiconductor wafer 100.
  • the wafer tray 50 in the present embodiment corresponds to an example of a holding member in the present invention.
  • annular grooves 502 On the upper surface 501 of the wafer tray 50, three annular grooves 502 having a smaller diameter than the semiconductor wafer 100 are formed concentrically. These annular grooves 502 communicate with a suction passage 503 formed in the wafer tray 50.
  • the adsorption passage 503 is connected to a first vacuum pump (not shown) via an adsorption port 504.
  • the semiconductor wafer 100 is attracted and held on the wafer tray 50 by the negative pressure generated in the annular groove 502.
  • the shape and number of the annular grooves 502 are not particularly limited.
  • a pressure reducing passage 505 is formed in the wafer tray 50.
  • the decompression passage 505 is opened by a suction hole 506 positioned further outside the outermost annular groove 502 on the upper surface 501.
  • the pressure reducing passage 505 is connected to a second vacuum pump (not shown) via a pressure reducing port 507.
  • the 2nd vacuum pump in this embodiment is equivalent to an example of the decompression means in the present invention.
  • annular seal member 51 is provided in the vicinity of the outer peripheral portion of the upper surface 501 of the wafer tray 50.
  • the seal member 51 for example, packing made of silicone rubber can be exemplified.
  • the sealing member 51 forms a sealed space 53 (see FIG. 15) between the upper surface 501 of the wafer tray 50 and the probe card 21.
  • the seal member 51 of the present embodiment has a degree of freedom (flexibility) along the Z direction (FIG. 8) enough to allow the movement of the wafer tray 50 after the pressure reduction of the second pump. Yes.
  • a cooling passage 508 is formed in the wafer tray 50 and a heater 52 and a temperature sensor (not shown) are embedded to adjust the temperature of the semiconductor wafer 100. Is possible.
  • the wafer tray 50 described above is detachably held by the stage 60 and can be moved.
  • a stage 60 is shared by a plurality of test heads and the semiconductor wafer 100 under test is held on the wafer tray 50, while the stage 60 performs other operations (other wafer trays 50). And the operation rate of the entire semiconductor wafer testing apparatus can be improved.
  • the stage 60 includes a motor and a ball screw mechanism that are not particularly shown, and as shown in FIG. 1, the wafer tray 50 is moved three-dimensionally (XYZ direction) and rotated about the Z axis. It is possible to make it.
  • the stage 60 in the present embodiment corresponds to an example of the moving device in the present invention.
  • the stage 60 in the present embodiment has a tip holding portion 61 that holds the wafer tray 50 in a detachable manner.
  • the tip holding portion 61 is formed of a disk-like member having a flat upper surface 611 on which the wafer tray 50 is placed.
  • the upper surface 611 has a size that is approximately the same as the wafer tray 50.
  • Three annular grooves 612 having a smaller diameter than the semiconductor wafer 100 are concentrically formed on the upper surface 611 of the tip holding portion 61. These annular grooves 612 communicate with a suction passage 613 formed in the tip holding portion 61.
  • the suction passage 613 is connected to the third vacuum pump 62 via the suction port 614.
  • the shape and number of the annular grooves 612 are not particularly limited. Further, guide pins may be provided upright on the upper surface 611 of the tip holding portion 61, and guide holes may be formed on the lower surface of the wafer tray 50, and the wafer tray 50 may be guided to the tip holding portion 61 by these guide pins and guide holes.
  • the mechanical stopper 70 includes a motor 71, a ball screw mechanism 72, and a contact member 73 as shown in FIG.
  • the mechanical stopper 70 in the present embodiment corresponds to an example of the contact means in the present invention.
  • the motor 71 is composed of, for example, a servo motor or a pulse motor, and the stroke can be numerically managed.
  • the ball screw mechanism 72 is connected to the drive shaft of the motor 71, and converts the rotational drive force generated by the motor 71 into a linear drive force along the Z direction.
  • the contact member 73 is attached to a ball screw mechanism, and can be moved in the Z-axis direction by the driving force of the motor 71 converted by the ball screw mechanism 72.
  • a piezoelectric element (piezo element) may be used instead of the motor 71 and the ball screw mechanism 72.
  • the mechanical stopper 70 is attached to the periphery of the opening 31 a into which the probe card 21 is inserted in the head plate 31 of the wafer prober 30. Normally, the motor 71 is stopped and the contact member 73 is attached to the wafer tray 50. It abuts on the outer periphery and functions as a stopper. Then, as will be described later, for example, with the electrical contact between the electrode 110 of the semiconductor wafer 100 and the probe needle 212 of the probe card 21 as a trigger, the motor 71 is driven to retract the contact member 73 by a predetermined amount (eg, about 100 ⁇ m) It is supposed to be.
  • a predetermined amount eg, about 100 ⁇ m
  • FIG. 13 is a view of the interface assembly 20 and the wafer prober 30 as viewed from below.
  • the direction of the main surface of the wafer tray 50 can also be controlled by the mechanical stoppers 70.
  • the number of mechanical stoppers 70 is not particularly limited as long as it is three or more, and the mechanical stoppers 70 are preferably arranged evenly, but are not particularly limited thereto.
  • the mechanical stopper 70 may be provided on the wafer tray 50, and the contact member 73 may be in contact with the head plate 31 of the wafer prober 30B.
  • FIG. 14 is a flowchart showing a method for testing a semiconductor wafer in the present embodiment
  • FIG. 15 is an enlarged sectional view showing steps S22 to S24 in FIG.
  • step S21 of FIG. 14 the stage 60 of the wafer prober 30B moves the wafer tray 50 holding the semiconductor wafer 100 to a position facing the probe card 21.
  • the stage 60 raises the wafer tray 50 until the seal member 51 of the wafer tray 50 comes into close contact with the card substrate 211 of the probe card 21.
  • the stage 60 stops.
  • step S22 of FIG. 14 as shown in FIG. 15, the second vacuum pump is operated to depressurize the sealed space 53.
  • the suction force F P that occurs with the vacuum in the closed space 53 the pressing force needed for all probes 212 having the probe card 21 F N (e.g. 200 ⁇ 300 [kgf ] (Approximately 1.96 ⁇ 10 3 [N] to 2.94 ⁇ 10 3 [N])), the second vacuum pump is controlled to be slightly stronger (F P > F N ).
  • the test head 10 detects electrical contact between the electrode 110 of the semiconductor wafer 100 and the probe needle 212 of the probe card 21 (step S23). ).
  • the stage 60 moves down from the wafer tray 50 in order to perform other operations (such as movement and alignment of other wafer trays 50).
  • step S24 of FIG. 14 using this detection as a trigger, as shown in FIG. 15, the motor 71 of the mechanical stopper 70 is driven to retract the contact member 73 by a predetermined amount (for example, 100 ⁇ m).
  • the suction force F P by decompression, because the stronger a little than the required pressing force F N of the probe needle 212 (F P> F N) , along with the retraction of the contact member 73
  • the wafer tray 50 further approaches the probe card 21.
  • the probe needle 212 of the probe card 21 bites into the electrode 110 of the semiconductor wafer 100, so that the probe needle 212 and the electrode 110 come into contact with each other.
  • step S25 of FIG. 14 the test head 10 inputs / outputs a test signal to / from the DUT of the semiconductor wafer 100 via the interface assembly 20, whereby the DUT test is executed.
  • the rigidity of the stiffener of the wafer tray 50, the stage 60, or the probe card 21 can be reduced, and the semiconductor The cost of the wafer test apparatus 1B can be reduced.
  • the contact member 73 of the mechanical stopper 70 is retracted while maintaining the reduced pressure, so that it is possible to cope with the case where a probe card of a type that requires stroke management is used.
  • the mechanical stopper 70 in this embodiment is also compatible with cantilever type and vertical type probe cards that require stroke management. It becomes possible to do.
  • the planar direction of the wafer tray 50 can be controlled.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

A method for testing a semiconductor wafer (100) using a probe card (21) comprises a step (S11) for forming a sealed space (37) between a chuck (33) and the probe card (21), a step (S12) for reducing the pressure in the sealed space (37), and a step (S14) for moving the chuck (33) a prescribed amount toward the probe card (21) in a state of reduced pressure in the sealed space (37).

Description

半導体ウェハの試験方法、半導体ウェハ搬送装置、及び半導体ウェハ試験装置Semiconductor wafer test method, semiconductor wafer transfer device, and semiconductor wafer test device
　本発明は、半導体ウェハに形成された集積回路素子等の被試験電子部品（以下、ＤＵＴ（Device Under Test）とも称する。）を、プローブカードを用いて試験する半導体ウェハの試験方法、並びに、その試験に用いられる半導体ウェハ搬送装置及び半導体ウェハ試験装置に関する。 The present invention relates to a semiconductor wafer test method for testing an electronic device under test such as an integrated circuit element formed on a semiconductor wafer (hereinafter also referred to as DUT (Device （Under Test)) using a probe card, and The present invention relates to a semiconductor wafer transfer apparatus and a semiconductor wafer test apparatus used for testing.
　ウェハ状態でのＤＵＴのテストに用いられるプローブカードとして、例えば、プローブ針を有するカンチレバー型プローブカードや、ポゴピンを有するバーチカル（垂直）型プローブカードが従来から知られている（例えば、特許文献１参照）。 As a probe card used for a DUT test in a wafer state, for example, a cantilever type probe card having a probe needle and a vertical type probe card having a pogo pin are conventionally known (for example, see Patent Document 1). ).
　こうしたプローブカードでは、プローブカードの接触子と半導体ウェハの電極との電気的な接触を確実なものとするため、接触子と電極とが接触してから半導体ウェハをプローブカードに向かって所定量（例えば１００μｍ）押し上げる（オーバドライブさせる）必要がある。 In such a probe card, in order to ensure electrical contact between the contact of the probe card and the electrode of the semiconductor wafer, the semiconductor wafer is moved toward the probe card by a predetermined amount ( (For example, 100 μm) It is necessary to push up (overdrive).
　このようなストローク管理を行うために、上記のプローブカードを用いた半導体ウェハの試験では、半導体ウェハを吸着保持するチャックと、当該チャックを昇降させるＺステージと、を有するプローバが用いられている。 In order to perform such stroke management, a prober having a chuck for sucking and holding a semiconductor wafer and a Z stage for raising and lowering the chuck is used in a semiconductor wafer test using the probe card.
国際公開第２００６／０６４５４６号International Publication No. 2006/064546
　上記の構造では、チャックを介して半導体ウェハをプローブカードに押し付けるため、当該チャックやプローブカードの剛性を高めておく必要があり、高コスト化を招来するという問題がある。半導体ウェハに形成された全てのＤＵＴにプローブカードを同時に接触させる一括コンタクト方式を採用する場合には、この問題は特に顕著である。 In the above structure, since the semiconductor wafer is pressed against the probe card via the chuck, it is necessary to increase the rigidity of the chuck or the probe card, resulting in an increase in cost. This problem is particularly noticeable when the collective contact method in which the probe card is simultaneously brought into contact with all the DUTs formed on the semiconductor wafer.
　本発明が解決しようとする課題は、低コスト化を図ることが可能な半導体ウェハの試験方法、半導体ウェハ搬送装置、及び半導体ウェハ試験装置を提供することである。 The problem to be solved by the present invention is to provide a semiconductor wafer test method, a semiconductor wafer transfer apparatus, and a semiconductor wafer test apparatus capable of reducing the cost.
　（１）本発明に係る半導体ウェハの試験方法は、プローブカードを用いて半導体ウェハを試験する方法であって、前記半導体ウェハを保持する保持部材と前記プローブカードとの間に密閉空間を形成する密閉工程と、前記密閉空間を減圧する減圧工程と、前記密閉空間を減圧した状態で、前記保持部材を前記プローブカードに向かって所定量移動させる移動工程と、を備えたことを特徴とする（請求項１参照）。 (1) A method for testing a semiconductor wafer according to the present invention is a method for testing a semiconductor wafer using a probe card, wherein a sealed space is formed between the holding member for holding the semiconductor wafer and the probe card. A sealing step; a decompression step of decompressing the sealed space; and a moving step of moving the holding member by a predetermined amount toward the probe card in a state where the sealed space is decompressed ( (See claim 1).
　上記発明において、前記プローブカードは、カンチレバー型プローブカード又はバーチカル型プローブカードを含んでもよい（請求項２参照）。 In the above invention, the probe card may include a cantilever type probe card or a vertical type probe card (see claim 2).
　上記発明において、前記半導体ウェハの試験方法は、前記半導体ウェハと前記プローブカードとの電気的接触を検出する検出工程を備え、前記移動工程は、前記検出工程での検出結果に基づいて、前記保持部材を前記プローブカードに向かって移動させることを含んでもよい（請求項３参照）。 In the above invention, the semiconductor wafer testing method includes a detection step of detecting electrical contact between the semiconductor wafer and the probe card, and the moving step is performed based on a detection result in the detection step. It may include moving a member toward the probe card (see claim 3).
　上記発明において、前記移動工程は、前記保持部材を移動させる移動手段によって、前記保持部材を前記プローブカードに向かって前進させることを含んでもよい（請求項４参照）。 In the above invention, the moving step may include advancing the holding member toward the probe card by moving means for moving the holding member (see claim 4).
　上記発明において、前記減圧工程は、前記密閉空間内の減圧に伴って生じる吸着力（ＦＰ）が、前記プローブカードの押圧に必要とされる必要押圧力（ＦＮ）以下となるように（ＦＰ≦ＦＮ）、前記密閉空間内を減圧することを含んでもよい（請求項５参照）。 In the above invention, the depressurization step is performed so that the adsorption force (F P ) generated along with the depressurization in the sealed space is equal to or less than a necessary pressing force (F N ) required for pressing the probe card ( F P ≦ F N ), and may include reducing the pressure in the sealed space (see claim 5).
　上記発明において、前記移動工程は、前記保持部材に当接している当接手段を後退させることを含んでもよい（請求項６参照）。 In the above invention, the moving step may include retreating the contact means that is in contact with the holding member (see claim 6).
　上記発明において、前記減圧工程は、前記密閉空間内の減圧に伴って生じる吸着力（ＦＰ）が、前記プローブカードの押圧に必要とされる必要押圧力（ＦＮ）よりも大きくなるように（ＦＰ＞ＦＮ）、前記密閉空間内を減圧することを含んでもよい（請求項７参照）。 In the above invention, in the pressure reducing step, the adsorption force (F P ) generated with the pressure reduction in the sealed space is larger than the necessary pressing force (F N ) required for pressing the probe card. (F P > F N ), which may include reducing the pressure in the sealed space (see claim 7).
　（２）本発明に係る半導体ウェハ搬送装置は、プローブカードを用いた半導体ウェハの試験に用いられる半導体ウェハ搬送装置であって、前記半導体ウェハを保持する保持部材と、前記プローブカードと前記保持部材との間に密閉空間を形成する密閉手段と、前記密閉空間を減圧する減圧手段と、前記減圧手段によって前記密閉空間を減圧した状態で、前記保持部材を前記プローブカードに対して相対移動させる移動手段と、を備えたことを特徴とする（請求項８参照）。 (2) A semiconductor wafer transfer device according to the present invention is a semiconductor wafer transfer device used for testing a semiconductor wafer using a probe card, the holding member holding the semiconductor wafer, the probe card, and the holding member A sealing means for forming a sealed space between them, a decompressing means for decompressing the sealed space, and a movement for moving the holding member relative to the probe card in a state where the sealed space is decompressed by the decompressing means. Means (refer to claim 8).
　上記発明において、前記プローブカードは、カンチレバー型プローブカード又はバーチカル型プローブカードを含んでもよい（請求項９参照）。 In the above invention, the probe card may include a cantilever type probe card or a vertical type probe card (see claim 9).
　上記発明において、前記保持部材は、前記半導体ウェハが載置される載置面を有し、前記密閉手段は、前記載置面に設けられた環状のシール部材を含んでもよい（請求項１０参照）。 In the above invention, the holding member may have a mounting surface on which the semiconductor wafer is mounted, and the sealing means may include an annular seal member provided on the mounting surface (see claim 10). ).
　（３）本発明に係る半導体ウェハ搬送装置は、プローブカードを用いた半導体ウェハの試験に用いられる半導体ウェハ搬送装置であって、前記半導体ウェハを保持する保持部材と、前記プローブカードと前記保持部材との間に密閉空間を形成する密閉手段と、前記密閉空間を減圧する減圧手段と、前記保持部材に当接する当接部と、前記当接部を移動させる駆動部と、を有する当接手段と、を備えたことを特徴とする（請求項１１参照）。 (3) A semiconductor wafer transfer apparatus according to the present invention is a semiconductor wafer transfer apparatus used for testing a semiconductor wafer using a probe card, the holding member holding the semiconductor wafer, the probe card, and the holding member. A contact means including: a sealing means for forming a sealed space between; a pressure reducing means for reducing the pressure of the sealed space; a contact part that contacts the holding member; and a drive part that moves the contact part. (Refer to claim 11).
　上記発明において、前記プローブカードは、カンチレバー型プローブカード又はバーチカル型プローブカードを含んでもよい（請求項１２参照）。 In the above invention, the probe card may include a cantilever type probe card or a vertical type probe card (see claim 12).
　上記発明において、前記保持部材は、前記半導体ウェハが載置される載置面を有し、前記密閉手段は、前記載置面に設けられた環状のシール部材を含んでもよい（請求項１３参照）。 In the above invention, the holding member may have a mounting surface on which the semiconductor wafer is mounted, and the sealing means may include an annular seal member provided on the mounting surface (see claim 13). ).
　上記発明において、前記駆動部は、ボールねじ機構が連結されたモータ、又は、圧電素子を含んでもよい（請求項１４参照）。 In the above invention, the driving unit may include a motor connected to a ball screw mechanism or a piezoelectric element (see claim 14).
　上記発明において、複数の前記当接手段が、前記保持部材の外周部に当接するように周方向に沿って実質的に等間隔に配置されてもよい（請求項１５参照）。 In the above invention, the plurality of contact means may be arranged at substantially equal intervals along the circumferential direction so as to contact the outer peripheral portion of the holding member (see claim 15).
　（４）本発明に係る半導体ウェハ試験装置は、プローブカードを用いて半導体ウェハを試験する半導体ウェハ試験装置であって、前記プローブカードが電気的に接続される試験装置本体と、上記の半導体ウェハ搬送装置と、を備えたことを特徴とする（請求項１６参照）。 (4) A semiconductor wafer test apparatus according to the present invention is a semiconductor wafer test apparatus for testing a semiconductor wafer using a probe card, the test apparatus main body to which the probe card is electrically connected, and the semiconductor wafer described above And a conveying device (see claim 16).
　本発明では、減圧によって半導体ウェハとプローブカードとを電気的に接触させるので、半導体ウェハを保持する保持部材やプローブカードの剛性を高める必要がなく、低コスト化を図ることができる。 In the present invention, since the semiconductor wafer and the probe card are brought into electrical contact under reduced pressure, it is not necessary to increase the rigidity of the holding member and the probe card for holding the semiconductor wafer, and the cost can be reduced.
　また、本発明では、減圧を維持した状態で保持部材をプローブカードに向かって移動させるので、ストローク管理を必要とするタイプのプローブカードにも対応することができる。 In the present invention, since the holding member is moved toward the probe card while maintaining the reduced pressure, it is possible to cope with a probe card of a type that requires stroke management.
図１は、本発明の第１実施形態における半導体ウェハ試験装置の全体構成を示す概略側面図である。FIG. 1 is a schematic side view showing an overall configuration of a semiconductor wafer test apparatus in a first embodiment of the present invention. 図２は、図１のII部の拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a portion II in FIG. 図３は、本発明の第１実施形態におけるウェハプローバを示す平面図である。FIG. 3 is a plan view showing the wafer prober in the first embodiment of the present invention. 図４は、図３のIV-IV線に沿った断面図である。4 is a cross-sectional view taken along line IV-IV in FIG. 図５は、本発明の第１実施形態における半導体ウェハの試験方法を示すフローチャートである。FIG. 5 is a flowchart showing a semiconductor wafer test method according to the first embodiment of the present invention. 図６は、図５のステップＳ１２を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing step S12 of FIG. 図７は、図５のステップＳ１４を示す拡大断面図である。FIG. 7 is an enlarged cross-sectional view showing step S14 of FIG. 図８は、本発明の第２実施形態における半導体ウェハ試験装置の全体構成を示す概略側面図である。FIG. 8 is a schematic side view showing the overall configuration of the semiconductor wafer testing apparatus in the second embodiment of the present invention. 図９は、本発明の第２実施形態におけるウェハトレイを示す断面図である。FIG. 9 is a cross-sectional view showing a wafer tray in the second embodiment of the present invention. 図１０は、本発明の第２実施形態におけるステージを示す平面図である。FIG. 10 is a plan view showing a stage in the second embodiment of the present invention. 図１１は、図１０のXI-XI線に沿った断面図である。11 is a cross-sectional view taken along line XI-XI in FIG. 図１２は、本発明の第２実施形態におけるメカニカルストッパの構成を示す断面図である。FIG. 12 is a cross-sectional view showing the configuration of the mechanical stopper in the second embodiment of the present invention. 図１３は、本発明の第２実施形態におけるメカニカルストッパのレイアウトを示す底面図である。FIG. 13 is a bottom view showing the layout of the mechanical stopper in the second embodiment of the present invention. 図１４は、本発明の第２実施形態における半導体ウェハの試験方法を示すフローチャートである。FIG. 14 is a flowchart showing a semiconductor wafer test method according to the second embodiment of the present invention. 図１５は、図１４のステップＳ２２～Ｓ２４を示す拡大断面図である。FIG. 15 is an enlarged sectional view showing steps S22 to S24 in FIG.
　以下、本発明の実施形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　＜第１実施形態＞
　図１及び図２は本実施形態における半導体ウェハ試験装置を示す図である。 <First Embodiment>
1 and 2 are diagrams showing a semiconductor wafer test apparatus in the present embodiment.
　本実施形態における半導体ウェハ試験装置１は、半導体ウェハ１００に造り込まれたＤＵＴの電気的特性を試験する装置であり、図１に示すように、テストヘッド１０と、インタフェース組立体２０と、ウェハプローバ３０と、を備えている。 The semiconductor wafer test apparatus 1 in this embodiment is an apparatus for testing the electrical characteristics of a DUT built in a semiconductor wafer 100. As shown in FIG. 1, a test head 10, an interface assembly 20, and a wafer And a prober 30.
　この半導体ウェハ試験装置１では、ＤＵＴの試験に際して、ウェハプローバ３０によって半導体ウェハ１００をインタフェース組立体２０のプローブカード２１に対向させ、この状態で、第２の真空ポンプ４２（図３参照）によって密閉空間３７（図６及び図７参照）内を減圧することで、半導体ウェハ１００をプローブカード２１に接触させる。さらに、この状態からウェハプローバ３０によって半導体ウェハ１００をプローブカード２１に向かって所定量押し込む。この押込みによって半導体ウェハ１００とプローブカード２１とが確実に接触したら、テストヘッド１０から半導体ウェハ１００のＤＵＴに対して試験信号を入出力することで、ＤＵＴのテストを実行する。 In this semiconductor wafer test apparatus 1, when testing the DUT, the semiconductor probe 100 is made to face the probe card 21 of the interface assembly 20 by the wafer prober 30, and in this state, the second vacuum pump 42 (see FIG. 3) The semiconductor wafer 100 is brought into contact with the probe card 21 by reducing the pressure in the space 37 (see FIGS. 6 and 7). Further, from this state, the wafer prober 30 pushes the semiconductor wafer 100 toward the probe card 21 by a predetermined amount. When the semiconductor wafer 100 and the probe card 21 are reliably brought into contact with each other by this pushing, a test signal is inputted / outputted from the test head 10 to the DUT of the semiconductor wafer 100 to execute a DUT test.
　すなわち、本実施形態の半導体ウェハ試験装置１では、半導体ウェハ１００とインタフェース組立体２０とを接触させる方式として減圧方式を採用しつつも、カンチレバー型やバーチカル型のプローブカードに必要とされるストローク管理の機能も備えている。 That is, in the semiconductor wafer test apparatus 1 of the present embodiment, the stroke management required for the cantilever type or vertical type probe card is adopted while adopting the decompression method as a method for bringing the semiconductor wafer 100 and the interface assembly 20 into contact with each other. It also has the function.
　インタフェース組立体２０は、図２に示すように、半導体ウェハ１００に電気的に接触するプローブカード２１と、テストヘッド１０に接続されるパフォーマンスボード２４と、プローブカード２１とパフォーマンスボード２４との間で伝送路のピッチ変換を行うインタポーザ２２と、を備えている。 As shown in FIG. 2, the interface assembly 20 includes a probe card 21 that is in electrical contact with the semiconductor wafer 100, a performance board 24 connected to the test head 10, and the probe card 21 and the performance board 24. And an interposer 22 that performs pitch conversion of the transmission path.
　プローブカード２１は、配線等が形成されたカード基板２１１と、当該基板２１に実装された多数のプローブ針２１２を有する、いわゆるカンチレバー型のプローブカードである。 The probe card 21 is a so-called cantilever type probe card having a card substrate 211 on which wiring or the like is formed and a large number of probe needles 212 mounted on the substrate 21.
　なお、本実施形態におけるプローブカード２１は、半導体ウェハ１００との接触後に所定量のオーバドライブを必要とするタイプのものであれば、上記のものに特に限定されない。例えば、プローブカード２１として、カード基板と、当該カード基板に立設された多数のポゴピンと、を有する、いわゆるバーチカル（垂直）型のプローブカードを用いてもよい。 Note that the probe card 21 in the present embodiment is not particularly limited to the above as long as it is of a type that requires a predetermined amount of overdrive after contact with the semiconductor wafer 100. For example, as the probe card 21, a so-called vertical (vertical) type probe card having a card substrate and a large number of pogo pins standing on the card substrate may be used.
　このプローブカード２１とパフォーマンスボード２４とを電気的に接続するインタポーザ２２は、例えば、シリコン基板、セラミック基板、ガラス基板等のピッチ変換基板や異方導電性ゴム等から構成されており、プローブカード２１側の狭いピッチを、パフォーマンスボード２４側の比較的広いピッチに変換する。なお、このインタポーザ２２は、プローブカード２１とパフォーマンスボード２４との間で伝送路のピッチ変換を行うものであれば、上記のものに特に限定されない。 The interposer 22 that electrically connects the probe card 21 and the performance board 24 is composed of, for example, a pitch conversion substrate such as a silicon substrate, a ceramic substrate, or a glass substrate, anisotropic conductive rubber, or the like. The narrow pitch on the side is converted into a relatively wide pitch on the performance board 24 side. The interposer 22 is not particularly limited to the above as long as the transmission path pitch conversion is performed between the probe card 21 and the performance board 24.
　パフォーマンスボード２４は、インタポーザ２２を介してプローブカード２１と電気的に接続されている一方で、特に図示しないコネクタやケーブル等を介して、テストヘッド１０内に収容されたピンエレクトロニクスに電気的に接続されている。さらに、テストヘッド１０は、例えば、ケーブルを介してテスタ（メインフレーム）に電気的に接続されている。本実施形態におけるテストヘッド１０やテスタが、本発明における試験装置本体の一例に相当する。 While the performance board 24 is electrically connected to the probe card 21 via the interposer 22, it is electrically connected to the pin electronics housed in the test head 10 via a connector, cable, or the like not shown. Has been. Furthermore, the test head 10 is electrically connected to a tester (main frame) via a cable, for example. The test head 10 and the tester in the present embodiment correspond to an example of a test apparatus main body in the present invention.
　プローブカード２１の上面とパフォーマンスボード２４の下面との間には、環状のシール部材２３が介装されており、プローブカード２１とパフォーマンスボード２４との間に内部空間２５が形成されている。インタポーザ２２は、この内部空間２５の中に収容されている。 An annular seal member 23 is interposed between the upper surface of the probe card 21 and the lower surface of the performance board 24, and an internal space 25 is formed between the probe card 21 and the performance board 24. The interposer 22 is accommodated in the internal space 25.
　図３及び図４は本実施形態におけるウェハプローバを示す図である。 3 and 4 are views showing a wafer prober in the present embodiment.
　ウェハプローバ３０は、図１に示すように、半導体ウェハ１００を吸着保持するチャック３３と、当該チャック３３をインタフェース組立体２０に対して相対移動させるステージ６０と、を備えている。本実施形態におけるウェハプローバ３０が、本発明における半導体ウェハ搬送装置の一例に相当する。 As shown in FIG. 1, the wafer prober 30 includes a chuck 33 that holds the semiconductor wafer 100 by suction and a stage 60 that moves the chuck 33 relative to the interface assembly 20. The wafer prober 30 in the present embodiment corresponds to an example of a semiconductor wafer transfer apparatus in the present invention.
　チャック３３は、図３及び図４に示すように、半導体ウェハ１００が載置される平坦な上面３３１を持つ略円板状の部材であり、チャック３３の上面３３１は半導体ウェハ１００よりも大きな直径を有している。なお、本実施形態におけるチャック３３が、本発明における保持部材の一例に相当する。 As shown in FIGS. 3 and 4, the chuck 33 is a substantially disk-shaped member having a flat upper surface 331 on which the semiconductor wafer 100 is placed, and the upper surface 331 of the chuck 33 has a larger diameter than the semiconductor wafer 100. have. The chuck 33 in the present embodiment corresponds to an example of the holding member in the present invention.
　このチャック３３の上面３３１には、半導体ウェハ１００よりも小径の３つの環状溝３３２が同心円状に形成されている。これらの環状溝３３２は、チャック３３内に形成された吸着用通路３３３に連通している。この吸着用通路３３３は、吸着ポート３３４を介して第１の真空ポンプ４１に接続されている。 On the upper surface 331 of the chuck 33, three annular grooves 332 having a smaller diameter than the semiconductor wafer 100 are formed concentrically. These annular grooves 332 communicate with a suction passage 333 formed in the chuck 33. The suction passage 333 is connected to the first vacuum pump 41 via the suction port 334.
　従って、チャック３３の上面３３１に半導体ウェハ１００を載置した状態で第１の真空ポンプ４１によって吸引を行うと、環状溝３３２内に発生した負圧によって半導体ウェハ１００がチャック３３に吸着保持される。なお、環状溝３３２の形状や数は特に限定されない。 Accordingly, when suction is performed by the first vacuum pump 41 with the semiconductor wafer 100 placed on the upper surface 331 of the chuck 33, the semiconductor wafer 100 is attracted and held by the chuck 33 due to the negative pressure generated in the annular groove 332. . The shape and number of the annular grooves 332 are not particularly limited.
　さらに、本実施形態では、チャック３３内に減圧用通路３３５が形成されている。この減圧用通路３３５は、上面３３１において最外側の環状溝３３２のさらに外側に位置する吸引孔３３６で開口している。この減圧用通路３３５は、減圧ポート３３７を介して、第２の真空ポンプ４２に接続されている。本実施形態における第２の真空ポンプ４２が、本発明における減圧手段の一例に相当する。 Furthermore, in this embodiment, a pressure reducing passage 335 is formed in the chuck 33. The decompression passage 335 is opened by a suction hole 336 positioned further outside the outermost annular groove 332 on the upper surface 331. The pressure reducing passage 335 is connected to the second vacuum pump 42 via a pressure reducing port 337. The second vacuum pump 42 in the present embodiment corresponds to an example of a decompression unit in the present invention.
　また、チャック３３の上面３３１の外周部近傍には、環状のシール部材３４が設けられている。このシール部材３４の具体例としては、例えばシリコーンゴムからなるパッキン等を例示することができる。チャック３３がプローブカード２１に押し付けられると、このシール部材３４によって、チャック３３の上面３３１とプローブカード２１との間に密閉空間３７（図６及び図７参照）が形成されるようになっている。特に、本実施形態のシール部材３４は、第２のポンプ４２の減圧後のチャック３３の移動を十分に許容し得る程度のＺ方向（図１）に沿った自由度（柔軟性）を有している。 Further, an annular seal member 34 is provided in the vicinity of the outer peripheral portion of the upper surface 331 of the chuck 33. As a specific example of the seal member 34, for example, a packing made of silicone rubber can be exemplified. When the chuck 33 is pressed against the probe card 21, a sealed space 37 (see FIGS. 6 and 7) is formed between the upper surface 331 of the chuck 33 and the probe card 21 by the seal member 34. . In particular, the seal member 34 of this embodiment has a degree of freedom (flexibility) along the Z direction (FIG. 1) that can sufficiently allow the movement of the chuck 33 after the pressure reduction of the second pump 42. ing.
　さらに、チャック３３内には、半導体ウェハ１００の温度調節を行うために、冷却用通路３３８が形成されていると共にヒータ３５と温度センサ３６が埋設されている。冷却用通路３３８は、一対の冷却ポート３３９を介してチラー４３に接続されている。温度センサ３５６の検出結果に基づいて、ヒータ３５やチラー４３を制御することで、半導体ウェハ１００の温度が目標温度に維持されるようになっている。 Furthermore, in order to adjust the temperature of the semiconductor wafer 100, a cooling passage 338 is formed in the chuck 33, and a heater 35 and a temperature sensor 36 are embedded. The cooling passage 338 is connected to the chiller 43 via a pair of cooling ports 339. By controlling the heater 35 and the chiller 43 based on the detection result of the temperature sensor 356, the temperature of the semiconductor wafer 100 is maintained at the target temperature.
　以上に説明したチャック３３は、ステージ３２の先端に固定されている。ステージ３２は、特に図示しないモータやボールねじ機構等から構成されており、図１に示すように、チャック３３を三次元的（Ｘ－Ｙ－Ｚ方向）に移動させると共にＺ軸を中心として回転させることが可能となっている。 The chuck 33 described above is fixed to the tip of the stage 32. The stage 32 is composed of a motor, a ball screw mechanism, and the like (not shown). As shown in FIG. 1, the stage 32 moves in a three-dimensional manner (XYZ direction) and rotates around the Z axis. It is possible to make it.
　このステージ３２は、チャック３３に吸着保持された半導体ウェハ１００を、インタフェース組立体２０に対向する位置に移動させてプローブカード２１に押し付けることが可能となっている。なお、本実施形態におけるステージ３２が、本発明における移動手段の一例に相当する。 The stage 32 can move the semiconductor wafer 100 sucked and held by the chuck 33 to a position facing the interface assembly 20 and press it against the probe card 21. The stage 32 in the present embodiment corresponds to an example of a moving unit in the present invention.
　次に、以上に説明した半導体ウェハ試験装置１による半導体ウェハ１００の試験方法について、図５～図７を参照しながら説明する。図５は本実施形態における半導体ウェハの試験方法を示すフローチャート、図６及び図７は図５のステップＳ１２及びＳ１４を示す図である。 Next, a method for testing the semiconductor wafer 100 using the semiconductor wafer test apparatus 1 described above will be described with reference to FIGS. FIG. 5 is a flowchart showing a semiconductor wafer testing method in the present embodiment, and FIGS. 6 and 7 are views showing steps S12 and S14 of FIG.
　先ず、図５のステップＳ１１において、ウェハプローバ３０のステージ３２が、半導体ウェハ１００を吸着保持しているチャック３３を、プローブカード２１に対向する位置に移動させる。次いで、チャック３３のシール部材３４がプローブカード２１のカード基板２１１に密着するまで、ステージ３２がチャック３３を上昇させる。シール部材３４がプローブカード２１に密着してプローブカード２１とチャック３３との間に密閉空間３７が形成されるまでチャック３３を上昇させたら、ステージ３２は停止する。 First, in step S <b> 11 of FIG. 5, the stage 32 of the wafer prober 30 moves the chuck 33 holding the semiconductor wafer 100 to a position facing the probe card 21. Next, the stage 32 raises the chuck 33 until the seal member 34 of the chuck 33 comes into close contact with the card substrate 211 of the probe card 21. When the chuck 33 is raised until the sealing member 34 comes into close contact with the probe card 21 and a sealed space 37 is formed between the probe card 21 and the chuck 33, the stage 32 stops.
　次いで、図５のステップＳ１２において、図６に示すように、第２の真空ポンプ４２を作動させて密閉空間３７内を減圧する。 Next, in step S12 of FIG. 5, as shown in FIG. 6, the second vacuum pump 42 is operated to depressurize the sealed space 37.
　この際、同図に示すように、密閉空間３７内の減圧に伴って生じる吸着力ＦＰが、プローブカード２１が有する全てのプローブ針２１２を押圧するのに必要な必要押圧力ＦＮ（例えば２００～３００[kgf]（１．９６×１０３[N]～２．９４×１０３[N]）程度）と実質的に同一（ＦＰ≒ＦＮ）となるように、第２の真空ポンプ４２を制御する。なお、吸着力ＦＰが必要押圧力ＦＮよりも若干弱く（ＦＰ＜ＦＮ）なるように、第２の真空ポンプ４２を制御してもよい。 At this time, as shown in the figure, the suction force F P that occurs with the vacuum in the closed space 37, required pressing force required to press all the probes 212 having the probe card 21 F N (e.g. The second vacuum so as to be substantially the same (F P ≈F N ) about 200 to 300 [kgf] (about 1.96 × 10 3 [N] to 2.94 × 10 3 [N])) The pump 42 is controlled. Incidentally, such that slightly weaker than the required pressing force F N is attraction force F P (F P <F N ), it may control the second vacuum pump 42.
　ここで、上記の必要押圧力ＦＮは、プローブ針２１２一本当たりに必要とされる押圧力（単位：[kgf/pin]）に対して、プローブカード２１が有するプローブ針２１２の総数を乗じることで算出される。 Here, it required pressing force F N described above, the pressing force required per one probe 212 (unit: [kgf / pin]) with respect to, multiplied by the total number of probe needles 212 with probe card 21 is It is calculated by.
　この減圧に伴って、半導体ウェハ１００とプローブカード２１とが接触すると、例えば、テストヘッド１０が半導体ウェハ１００の電極１１０とプローブカード２１のプローブ針２１２との電気的な接触を検出する（ステップＳ１３）。 When the semiconductor wafer 100 and the probe card 21 come into contact with the pressure reduction, for example, the test head 10 detects electrical contact between the electrode 110 of the semiconductor wafer 100 and the probe needle 212 of the probe card 21 (step S13). ).
　次いで、図５のステップＳ１４において、この検出をトリガとして、図７に示すように、例えばステージ３２のモータに取り付けられたエンコーダからの出力に基づいて、ステージ３２がチャック３３をさらに所定量（例えば１００μｍ）上昇させる。この上昇によって、プローブカード２１のプローブ針２１２が半導体ウェハ１００の電極１１０に喰い込むので、プローブ針２１２と電極１１０とが確実に接触する。 Next, in step S14 in FIG. 5, using this detection as a trigger, as shown in FIG. 100 μm). Due to this rise, the probe needle 212 of the probe card 21 bites into the electrode 110 of the semiconductor wafer 100, so that the probe needle 212 and the electrode 110 are reliably in contact with each other.
　次いで、図５のステップＳ１５において、テストヘッド１０がインタフェース組立体２０を介して半導体ウェハ１００のＤＵＴに対して試験信号を入出力することで、ＤＵＴの試験が実行される。 Next, in step S15 of FIG. 5, the test head 10 inputs / outputs a test signal to / from the DUT of the semiconductor wafer 100 via the interface assembly 20, whereby the DUT test is executed.
　半導体ウェハをプローブカードに下方から単に押し付ける従来の押圧方式のウェハプローバでは、チャックやステージ、プローブカードのスティフナの剛性を高めておく必要がある。これに対し、本実施形態では、減圧によって半導体ウェハ１００とプローブカード２１とを電気的に接触させるので、従来の押圧式のプローバのチャックと比較して、チャック３３、ステージ３２、或いはプローブカード２１のスティフナの剛性を低くすることができ、半導体ウェハ試験装置１の低コスト化を図ることができる。 In a conventional pressing type wafer prober that simply presses a semiconductor wafer against the probe card from below, it is necessary to increase the rigidity of the chuck, stage, and probe card stiffener. On the other hand, in the present embodiment, the semiconductor wafer 100 and the probe card 21 are brought into electrical contact with each other by decompression, so that the chuck 33, the stage 32, or the probe card 21 is compared with the chuck of a conventional pressing type prober. The rigidity of the stiffener can be reduced, and the cost of the semiconductor wafer test apparatus 1 can be reduced.
　また、本実施形態では、減圧を維持した状態でステージ３２によってチャック３３を上昇させるので、ストローク管理を必要とするタイプのプローブカードを使用する場合にも対応することができる。 Further, in this embodiment, the chuck 33 is raised by the stage 32 while maintaining the reduced pressure, so that it is possible to cope with a case where a probe card of a type that requires stroke management is used.
　因みに、ストローク管理を必要とするタイプのプローブカードを用いた試験において、単に減圧によってプローブカードと半導体ウェハとを接触させると、ストロークを厳密に管理することが難しく、十分なオーバドライブを確保し得なかったり、プローブ針２１２を塑性変形させてしまうおそれがある。 Incidentally, in a test using a probe card of a type that requires stroke management, if the probe card and the semiconductor wafer are simply brought into contact with each other by decompression, it is difficult to strictly manage the stroke, and sufficient overdrive can be secured. Or the probe needle 212 may be plastically deformed.
　＜第２実施形態＞
　図８は本実施形態における半導体ウェハ試験装置の全体構成を示す概略側面図、図９は本実施形態におけるウェハトレイを示す断面図、図１０及び図１１は本実施形態におけるステージを示す図、図１２は本実施形態におけるメカニカルストッパの構成を示す断面図、図１３は本実施形態におけるメカニカルストッパのレイアウトを示す底面図である。 Second Embodiment
8 is a schematic side view showing the overall configuration of the semiconductor wafer testing apparatus in the present embodiment, FIG. 9 is a cross-sectional view showing a wafer tray in the present embodiment, FIGS. 10 and 11 are views showing a stage in the present embodiment, and FIG. FIG. 13 is a sectional view showing the configuration of the mechanical stopper in the present embodiment, and FIG. 13 is a bottom view showing the layout of the mechanical stopper in the present embodiment.
　本実施形態における半導体ウェハ試験装置１Ｂは、図８に示すように、テストヘッド１０と、インタフェース組立体２０と、ウェハプローバ３０Ｂと、を備えている。テストヘッド１０及びインタフェース組立体２０の構成は、第１実施形態と同様であるので、同一の符号を付して説明を省略する。 The semiconductor wafer test apparatus 1B in this embodiment includes a test head 10, an interface assembly 20, and a wafer prober 30B as shown in FIG. Since the configuration of the test head 10 and the interface assembly 20 is the same as that of the first embodiment, the same reference numerals are given and description thereof is omitted.
　本実施形態におけるウェハプローバ３０Ｂは、（１）チャック３３に代えてウェハトレイ５０がステージ６０に取り付けられており、（２）ウェハトレイ５０を着脱可能に保持する先端保持部６１がステージ６０に設けられており、さらに（３）ウェハトレイ５０と当接するメカニカルストッパ７０を備えている点で、第１実施形態と相違する。 In the wafer prober 30B according to the present embodiment, (1) the wafer tray 50 is attached to the stage 60 instead of the chuck 33, and (2) a front end holding portion 61 that detachably holds the wafer tray 50 is provided on the stage 60. Furthermore, (3) it is different from the first embodiment in that it includes a mechanical stopper 70 that comes into contact with the wafer tray 50.
　本実施形態におけるウェハトレイ５０は、第１実施形態で説明したチャック３３と類似の構成を有しており、図９に示すように、半導体ウェハ１００が載置される平坦な上面５０１を持つ略円板状の部材であり、ウェハトレイ５０の上面５０１は半導体ウェハ１００よりも大きな直径を有している。なお、本実施形態におけるウェハトレイ５０が、本発明における保持部材の一例に相当する。 The wafer tray 50 in this embodiment has a configuration similar to that of the chuck 33 described in the first embodiment. As shown in FIG. 9, the wafer tray 50 has a substantially circular shape having a flat upper surface 501 on which the semiconductor wafer 100 is placed. It is a plate-like member, and the upper surface 501 of the wafer tray 50 has a larger diameter than the semiconductor wafer 100. The wafer tray 50 in the present embodiment corresponds to an example of a holding member in the present invention.
　このウェハトレイ５０の上面５０１には、半導体ウェハ１００よりも小径の３つの環状溝５０２が同心円状に形成されている。これらの環状溝５０２は、ウェハトレイ５０内に形成された吸着用通路５０３に連通している。この吸着用通路５０３は、吸着ポート５０４を介して第１の真空ポンプ（不図示）に接続されている。 On the upper surface 501 of the wafer tray 50, three annular grooves 502 having a smaller diameter than the semiconductor wafer 100 are formed concentrically. These annular grooves 502 communicate with a suction passage 503 formed in the wafer tray 50. The adsorption passage 503 is connected to a first vacuum pump (not shown) via an adsorption port 504.
　従って、ウェハトレイ５０の上面５０１に半導体ウェハ１００を載置した状態で第１の真空ポンプによって吸引を行うと、環状溝５０２内に発生した負圧によって半導体ウェハ１００がウェハトレイ５０に吸着保持される。なお、環状溝５０２の形状や数は特に限定されない。 Therefore, when suction is performed by the first vacuum pump while the semiconductor wafer 100 is placed on the upper surface 501 of the wafer tray 50, the semiconductor wafer 100 is attracted and held on the wafer tray 50 by the negative pressure generated in the annular groove 502. The shape and number of the annular grooves 502 are not particularly limited.
　さらに、本実施形態では、ウェハトレイ５０内に減圧用通路５０５が形成されている。この減圧用通路５０５は、上面５０１において最外側の環状溝５０２のさらに外側に位置する吸引孔５０６で開口している。この減圧用通路５０５は、減圧ポート５０７を介して、第２の真空ポンプ（不図示）に接続されている。本実施形態における第２の真空ポンプが、本発明における減圧手段の一例に相当する。 Furthermore, in this embodiment, a pressure reducing passage 505 is formed in the wafer tray 50. The decompression passage 505 is opened by a suction hole 506 positioned further outside the outermost annular groove 502 on the upper surface 501. The pressure reducing passage 505 is connected to a second vacuum pump (not shown) via a pressure reducing port 507. The 2nd vacuum pump in this embodiment is equivalent to an example of the decompression means in the present invention.
　また、ウェハトレイ５０の上面５０１の外周部近傍には、環状のシール部材５１が設けられている。このシール部材５１の具体例としては、例えばシリコーンゴムからなるパッキン等を例示することができる。ウェハトレイ５０がプローブカード２１に押し付けられると、このシール部材５１によって、ウェハトレイ５０の上面５０１とプローブカード２１との間に密閉空間５３（図１５参照）が形成されるようになっている。特に、本実施形態のシール部材５１は、第２のポンプの減圧後のウェハトレイ５０の移動を十分に許容し得る程度のＺ方向（図８）に沿った自由度（柔軟性）を有している。 Further, an annular seal member 51 is provided in the vicinity of the outer peripheral portion of the upper surface 501 of the wafer tray 50. As a specific example of the seal member 51, for example, packing made of silicone rubber can be exemplified. When the wafer tray 50 is pressed against the probe card 21, the sealing member 51 forms a sealed space 53 (see FIG. 15) between the upper surface 501 of the wafer tray 50 and the probe card 21. In particular, the seal member 51 of the present embodiment has a degree of freedom (flexibility) along the Z direction (FIG. 8) enough to allow the movement of the wafer tray 50 after the pressure reduction of the second pump. Yes.
　さらに、ウェハトレイ５０内には、上述のチャック３３と同様に、冷却用通路５０８が形成されていると共にヒータ５２及び温度センサ（不図示）が埋設されており、半導体ウェハ１００の温度調節を行うことが可能となっている。 Further, similarly to the chuck 33 described above, a cooling passage 508 is formed in the wafer tray 50 and a heater 52 and a temperature sensor (not shown) are embedded to adjust the temperature of the semiconductor wafer 100. Is possible.
　以上に説明したウェハトレイ５０は、ステージ６０によって着脱可能に保持されて移動することが可能となっている。こうしたウェハトレイ５０を採用することで、例えば、複数のテストヘッドで一つのステージ６０を共用して、テスト中の半導体ウェハ１００をウェハトレイ５０に保持させつつ、ステージ６０は他の作業（他のウェハトレイ５０の移動やアライメント等）を行うことができ、半導体ウェハ試験装置全体の稼働率向上を図ることができる。 The wafer tray 50 described above is detachably held by the stage 60 and can be moved. By adopting such a wafer tray 50, for example, a stage 60 is shared by a plurality of test heads and the semiconductor wafer 100 under test is held on the wafer tray 50, while the stage 60 performs other operations (other wafer trays 50). And the operation rate of the entire semiconductor wafer testing apparatus can be improved.
　ステージ６０は、特に図示しないモータやボールねじ機構等から構成されており、図１に示すように、ウェハトレイ５０を三次元的（Ｘ－Ｙ－Ｚ方向）に移動させると共にＺ軸を中心として回転させることが可能となっている。なお、本実施形態におけるステージ６０が、本発明における移動装置の一例に相当する。 The stage 60 includes a motor and a ball screw mechanism that are not particularly shown, and as shown in FIG. 1, the wafer tray 50 is moved three-dimensionally (XYZ direction) and rotated about the Z axis. It is possible to make it. The stage 60 in the present embodiment corresponds to an example of the moving device in the present invention.
　また、本実施形態におけるステージ６０は、図１０及び図１１に示すように、ウェハトレイ５０を着脱可能に保持する先端保持部６１を有している。この先端保持部６１は、ウェハトレイ５０が載置される平坦な上面６１１を持つ円板状の部材で構成されており、この上面６１１はウェハトレイ５０と同程度の大きさを有している。 Further, as shown in FIGS. 10 and 11, the stage 60 in the present embodiment has a tip holding portion 61 that holds the wafer tray 50 in a detachable manner. The tip holding portion 61 is formed of a disk-like member having a flat upper surface 611 on which the wafer tray 50 is placed. The upper surface 611 has a size that is approximately the same as the wafer tray 50.
　この先端保持部６１の上面６１１には、半導体ウェハ１００よりも小径の３つの環状溝６１２が同心円状に形成されている。これらの環状溝６１２は、先端保持部６１内に形成された吸着用通路６１３に連通している。この吸着用通路６１３は、吸着ポート６１４を介して第３の真空ポンプ６２に接続されている。 Three annular grooves 612 having a smaller diameter than the semiconductor wafer 100 are concentrically formed on the upper surface 611 of the tip holding portion 61. These annular grooves 612 communicate with a suction passage 613 formed in the tip holding portion 61. The suction passage 613 is connected to the third vacuum pump 62 via the suction port 614.
　従って、この先端保持部６１の上面６１１にウェハトレイ５０を載置した状態で第３の真空ポンプ６２によって吸引を行うと、環状溝６１２内に発生した負圧によってウェハトレイ５０がステージ６０の先端保持部６１に吸着保持される。 Accordingly, when suction is performed by the third vacuum pump 62 in a state where the wafer tray 50 is placed on the upper surface 611 of the tip holding portion 61, the wafer tray 50 is moved to the tip holding portion of the stage 60 by the negative pressure generated in the annular groove 612. 61 is held by suction.
　なお、環状溝６１２の形状や数は特に限定されない。また、先端保持部６１の上面６１１にガイドピンを立設すると共に、ウェハトレイ５０の下面にガイド孔を形成し、これらガイドピンとガイド孔によってウェハトレイ５０を先端保持部６１に案内してもよい。 Note that the shape and number of the annular grooves 612 are not particularly limited. Further, guide pins may be provided upright on the upper surface 611 of the tip holding portion 61, and guide holes may be formed on the lower surface of the wafer tray 50, and the wafer tray 50 may be guided to the tip holding portion 61 by these guide pins and guide holes.
　メカニカルストッパ７０は、図１２に示すように、モータ７１、ボールねじ機構７２、及び当接部材７３を備えている。なお、本実施形態におけるメカニカルストッパ７０が、本発明における当接手段の一例に相当する。 The mechanical stopper 70 includes a motor 71, a ball screw mechanism 72, and a contact member 73 as shown in FIG. The mechanical stopper 70 in the present embodiment corresponds to an example of the contact means in the present invention.
　モータ７１は、例えば、サーボモータ又はパルスモータから構成されており、ストロークを数値管理することが可能となっている。ボールねじ機構７２は、モータ７１の駆動軸に連結されており、モータ７１が発生した回転駆動力をＺ方向沿った直線駆動力に変換する。当接部材７３は、ボールねじ機構に取り付けられており、ボールねじ機構７２によって変換されたモータ７１の駆動力によって、Ｚ軸方向に移動することが可能となっている。 The motor 71 is composed of, for example, a servo motor or a pulse motor, and the stroke can be numerically managed. The ball screw mechanism 72 is connected to the drive shaft of the motor 71, and converts the rotational drive force generated by the motor 71 into a linear drive force along the Z direction. The contact member 73 is attached to a ball screw mechanism, and can be moved in the Z-axis direction by the driving force of the motor 71 converted by the ball screw mechanism 72.
　なお、モータ７１及びボールねじ機構７２に代えて、圧電素子（ピエゾ素子）を用いてもよい。 A piezoelectric element (piezo element) may be used instead of the motor 71 and the ball screw mechanism 72.
　このメカニカルストッパ７０は、ウェハプローバ３０のヘッドプレート３１において、プローブカード２１が挿入される開口３１ａに周囲に取り付けられており、通常はモータ７１が停止しており、当接部材７３がウェハトレイ５０の外周部に当接してストッパとして機能する。そして、後述するように、例えば半導体ウェハ１００の電極１１０とプローブカード２１のプローブ針２１２との電気的接触をトリガとして、モータ７１が駆動して当接部材７３が所定量（例えば１００μｍ程度）後退するようになっている。 The mechanical stopper 70 is attached to the periphery of the opening 31 a into which the probe card 21 is inserted in the head plate 31 of the wafer prober 30. Normally, the motor 71 is stopped and the contact member 73 is attached to the wafer tray 50. It abuts on the outer periphery and functions as a stopper. Then, as will be described later, for example, with the electrical contact between the electrode 110 of the semiconductor wafer 100 and the probe needle 212 of the probe card 21 as a trigger, the motor 71 is driven to retract the contact member 73 by a predetermined amount (eg, about 100 μm) It is supposed to be.
　本実施形態では、図１３に示すように、複数（本例では３つ）のメカニカルストッパ７０がヘッドプレート３１の開口３１ａの周囲に、周方向に沿って実質的に等間隔（１２０°毎）に配置されている。なお、図１３は、インタフェース組立体２０及びウェハプローバ３０を下方から見た図である。 In the present embodiment, as shown in FIG. 13, a plurality (three in this example) of mechanical stoppers 70 are substantially equidistant around the opening 31a of the head plate 31 along the circumferential direction (every 120 °). Are arranged. FIG. 13 is a view of the interface assembly 20 and the wafer prober 30 as viewed from below.
　複数のメカニカルストッパ７０を配置することで、メカニカルストッパ７０によってウェハトレイ５０の主面の方向も制御することが可能となる。なお、メカニカルストッパ７０の数は３つ以上であれば特に限定されず、また、メカニカルストッパ７０の配置も均等配置が好ましいが、特にこれに限定されない。 By arranging a plurality of mechanical stoppers 70, the direction of the main surface of the wafer tray 50 can also be controlled by the mechanical stoppers 70. The number of mechanical stoppers 70 is not particularly limited as long as it is three or more, and the mechanical stoppers 70 are preferably arranged evenly, but are not particularly limited thereto.
　なお、このメカニカルストッパ７０をウェハトレイ５０に設けて、当接部材７３をウェハプローバ３０Ｂのヘッドプレート３１に当接させてもよい。 The mechanical stopper 70 may be provided on the wafer tray 50, and the contact member 73 may be in contact with the head plate 31 of the wafer prober 30B.
　次に、以上に説明した半導体ウェハ試験装置１Ｂによる半導体ウェハ１００の試験方法について、図１４及び図１５を参照しながら説明する。図１４は本実施形態における半導体ウェハの試験方法を示すフローチャート、図１５は図１４のステップＳ２２～Ｓ２４を示す拡大断面図である。 Next, a method for testing the semiconductor wafer 100 using the semiconductor wafer test apparatus 1B described above will be described with reference to FIGS. FIG. 14 is a flowchart showing a method for testing a semiconductor wafer in the present embodiment, and FIG. 15 is an enlarged sectional view showing steps S22 to S24 in FIG.
　先ず、図１４のステップＳ２１において、ウェハプローバ３０Ｂのステージ６０が、半導体ウェハ１００を保持しているウェハトレイ５０を、プローブカード２１に対向する位置に移動させる。次いで、ウェハトレイ５０のシール部材５１がプローブカード２１のカード基板２１１に密着するまで、ステージ６０がウェハトレイ５０を上昇させる。シール部材５１がプローブカード２１に密着してプローブカード２１とウェハトレイ５０との間に密閉空間５３が形成されるまでウェハトレイ５０を上昇させたら、ステージ６０は停止する。 First, in step S21 of FIG. 14, the stage 60 of the wafer prober 30B moves the wafer tray 50 holding the semiconductor wafer 100 to a position facing the probe card 21. Next, the stage 60 raises the wafer tray 50 until the seal member 51 of the wafer tray 50 comes into close contact with the card substrate 211 of the probe card 21. When the wafer tray 50 is raised until the sealing member 51 is in close contact with the probe card 21 and the sealed space 53 is formed between the probe card 21 and the wafer tray 50, the stage 60 stops.
　次いで、図１４のステップＳ２２において、図１５に示すように、第２の真空ポンプを作動させて密閉空間５３内を減圧する。 Next, in step S22 of FIG. 14, as shown in FIG. 15, the second vacuum pump is operated to depressurize the sealed space 53.
　この際、同図に示すように、密閉空間５３内の減圧に伴って生じる吸着力ＦＰが、プローブカード２１が有する全てのプローブ針２１２に必要な押圧力ＦＮ（例えば２００～３００[kgf]（１．９６×１０３[N]～２．９４×１０３[N]）程度）よりも若干強く（ＦＰ＞ＦＮ）なるように、第２の真空ポンプを制御する。 At this time, as shown in the figure, the suction force F P that occurs with the vacuum in the closed space 53, the pressing force needed for all probes 212 having the probe card 21 F N (e.g. 200 ~ 300 [kgf ] (Approximately 1.96 × 10 3 [N] to 2.94 × 10 3 [N])), the second vacuum pump is controlled to be slightly stronger (F P > F N ).
　この減圧に伴って、半導体ウェハ１００とプローブカード２１とが接触すると、例えば、テストヘッド１０が半導体ウェハ１００の電極１１０とプローブカード２１のプローブ針２１２との電気的な接触を検出する（ステップＳ２３）。 When the semiconductor wafer 100 and the probe card 21 come into contact with the pressure reduction, for example, the test head 10 detects electrical contact between the electrode 110 of the semiconductor wafer 100 and the probe needle 212 of the probe card 21 (step S23). ).
　なお、本実施形態では、半導体ウェハ１００とプローブカード２１とが接触したら、ステージ６０は、他の作業（他のウェハトレイ５０の移動やアライメント等）を行うために、ウェハトレイ５０から離れて下降する。 In this embodiment, when the semiconductor wafer 100 and the probe card 21 come into contact with each other, the stage 60 moves down from the wafer tray 50 in order to perform other operations (such as movement and alignment of other wafer trays 50).
　次いで、図１４のステップＳ２４において、この検出をトリガとして、図１５に示すように、メカニカルストッパ７０のモータ７１を駆動させて、当接部材７３を所定量（例えば１００μｍ）後退させる。 Next, in step S24 of FIG. 14, using this detection as a trigger, as shown in FIG. 15, the motor 71 of the mechanical stopper 70 is driven to retract the contact member 73 by a predetermined amount (for example, 100 μm).
　この際、上述のように、減圧による吸着力ＦＰが、プローブ針２１２の必要押圧力ＦＮよりも若干強くなっているので（ＦＰ＞ＦＮ）、当接部材７３の後退に伴ってウェハトレイ５０がプローブカード２１にさらに接近する。この接近によって、プローブカード２１のプローブ針２１２が半導体ウェハ１００の電極１１０に食い込むので、プローブ針２１２と電極１１０とが確実に接触する。 At this time, as described above, the suction force F P by decompression, because the stronger a little than the required pressing force F N of the probe needle 212 (F P> F N) , along with the retraction of the contact member 73 The wafer tray 50 further approaches the probe card 21. By this approach, the probe needle 212 of the probe card 21 bites into the electrode 110 of the semiconductor wafer 100, so that the probe needle 212 and the electrode 110 come into contact with each other.
　次いで、図１４のステップＳ２５において、テストヘッド１０がインタフェース組立体２０を介して半導体ウェハ１００のＤＵＴに対して試験信号を入出力することで、ＤＵＴの試験が実行される。 Next, in step S25 of FIG. 14, the test head 10 inputs / outputs a test signal to / from the DUT of the semiconductor wafer 100 via the interface assembly 20, whereby the DUT test is executed.
　以上のように、本実施形態では、減圧によって半導体ウェハ１００とプローブカード２１とを電気的に接触させるので、ウェハトレイ５０、ステージ６０、或いはプローブカード２１のスティフナの剛性を低くすることができ、半導体ウェハ試験装置１Ｂの低コスト化を図ることができる。 As described above, in this embodiment, since the semiconductor wafer 100 and the probe card 21 are electrically contacted by decompression, the rigidity of the stiffener of the wafer tray 50, the stage 60, or the probe card 21 can be reduced, and the semiconductor The cost of the wafer test apparatus 1B can be reduced.
　また、本実施形態では、減圧を維持した状態でメカニカルストッパ７０の当接部材７３を後退させるので、ストローク管理を必要とするタイプのプローブカードを使用する場合にも対応することができる。 Further, in this embodiment, the contact member 73 of the mechanical stopper 70 is retracted while maintaining the reduced pressure, so that it is possible to cope with the case where a probe card of a type that requires stroke management is used.
　また、ストローク管理の不要なメンブレン型のプローブカードを対象とした減圧方式のプローバに、本実施形態におけるメカニカルストッパ７０を取り付けることで、ストローク管理の必要なカンチレバー型やバーチカル型のプローブカードにも対応することが可能となる。 In addition, by attaching the mechanical stopper 70 in this embodiment to a decompression type prober for membrane type probe cards that do not require stroke management, it is also compatible with cantilever type and vertical type probe cards that require stroke management. It becomes possible to do.
　また、こうしたメカニカルストッパ７０を複数設けることで、ウェハトレイ５０の平面方向の制御も可能となる。 Also, by providing a plurality of such mechanical stoppers 70, the planar direction of the wafer tray 50 can be controlled.
　なお、以上説明した実施形態は、本発明の理解を容易にするために記載されたものであって、本発明を限定するために記載されたものではない。したがって、上記の実施形態に開示された各要素は、本発明の技術的範囲に属する全ての設計変更や均等物をも含む趣旨である。 The embodiment described above is described for easy understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.
１，１Ｂ…半導体ウェハ試験装置
　１０…テストヘッド
　２０…インタフェース組立体
　　２１…プローブカード
　　　２１２…プローブ針
　　２２…インタポーザ
　　２４…パフォーマンスボード
　３０，３０Ｂ…ウェハプローバ
　　３１…ヘッドプレート
　　３２…ステージ
　　３３…チャック
　　　３４…シール部材
　　　３７…密閉空間
　　４２…第２の真空ポンプ
　５０…ウェハトレイ
　　５１…シール部材
　　５３…密閉空間
　６０…ステージ
　７０…メカニカルストッパ
　　７１…モータ
　　７２…ボールねじ機構
　　７３…当接部材
１００…半導体ウェハ
　１１０…電極 DESCRIPTION OF SYMBOLS 1,1B ... Semiconductor wafer test apparatus 10 ... Test head 20 ... Interface assembly 21 ... Probe card 212 ... Probe needle 22 ... Interposer 24 ... Performance board 30, 30B ... Wafer prober 31 ... Head plate 32 ... Stage 33 ... Chuck 34 ... Seal member 37 ... Sealed space 42 ... Second vacuum pump 50 ... Wafer tray 51 ... Seal member 53 ... Sealed space 60 ... Stage 70 ... Mechanical stopper 71 ... Motor 72 ... Ball screw mechanism 73 ... Contact member 100 ... Semiconductor wafer 110 ... electrode

Claims (16)

  1. 　プローブカードを用いて半導体ウェハを試験する方法であって、
    　前記半導体ウェハを保持する保持部材と前記プローブカードとの間に密閉空間を形成する密閉工程と、
    　前記密閉空間を減圧する減圧工程と、
    　前記密閉空間を減圧した状態で、前記保持部材を前記プローブカードに向かって所定量移動させる移動工程と、を備えたことを特徴とする半導体ウェハの試験方法。     A method of testing a semiconductor wafer using a probe card,
    A sealing step of forming a sealed space between the holding member that holds the semiconductor wafer and the probe card;
    A decompression step of decompressing the sealed space;
    And a moving step of moving the holding member by a predetermined amount toward the probe card in a state where the sealed space is decompressed.
  2. 　請求項１に記載の半導体ウェハの試験方法であって、
    　前記プローブカードは、カンチレバー型プローブカード又はバーチカル型プローブカードを含むことを特徴とする半導体ウェハの試験方法。     A test method for a semiconductor wafer according to claim 1,
    The method for testing a semiconductor wafer, wherein the probe card includes a cantilever type probe card or a vertical type probe card.
  3. 　請求項１又は２に記載の半導体ウェハの試験方法であって、
    　前記半導体ウェハと前記プローブカードとの電気的接触を検出する検出工程を備え、
    　前記移動工程は、前記検出工程での検出結果に基づいて、前記保持部材を前記プローブカードに向かって移動させることを含むことを特徴とする半導体ウェハの試験方法。     A method for testing a semiconductor wafer according to claim 1 or 2,
    A detection step of detecting electrical contact between the semiconductor wafer and the probe card;
    The method for testing a semiconductor wafer, wherein the moving step includes moving the holding member toward the probe card based on a detection result in the detecting step.
  4. 　請求項１～３の何れかに記載の半導体ウェハの試験方法であって、
    　前記移動工程は、前記保持部材を移動させる移動手段によって、前記保持部材を前記プローブカードに向かって前進させることを含むことを特徴とする半導体ウェハの試験方法。     A method for testing a semiconductor wafer according to any one of claims 1 to 3,
    The method for testing a semiconductor wafer, wherein the moving step includes advancing the holding member toward the probe card by moving means for moving the holding member.
  5. 　請求項４に記載の半導体ウェハの試験方法であって、
    　前記減圧工程は、前記密閉空間内の減圧に伴って生じる吸着力（ＦＰ）が、前記プローブカードの押圧に必要とされる必要押圧力（ＦＮ）以下となるように（ＦＰ≦ＦＮ）、前記密閉空間内を減圧することを含むことを特徴とする半導体ウェハの試験方法。     A method for testing a semiconductor wafer according to claim 4,
    The depressurization step is performed so that the adsorption force (F P ) generated with the depressurization in the sealed space is equal to or less than the necessary pressing force (F N ) required for pressing the probe card (F P ≦ F N ), a method for testing a semiconductor wafer, comprising depressurizing the sealed space.
  6. 　請求項１～３の何れかに記載の半導体ウェハの試験方法であって、
    　前記移動工程は、前記保持部材に当接している当接手段を後退させることを含むことを特徴とする半導体ウェハの試験方法。     A method for testing a semiconductor wafer according to any one of claims 1 to 3,
    The method for testing a semiconductor wafer, wherein the moving step includes retracting a contact means that is in contact with the holding member.
  7. 　請求項６に記載の半導体ウェハの試験方法であって、
    　前記減圧工程は、前記密閉空間内の減圧に伴って生じる吸着力（ＦＰ）が、前記プローブカードの押圧に必要とされる必要押圧力（ＦＮ）よりも大きくなるように（ＦＰ＞ＦＮ）、前記密閉空間内を減圧することを含むことを特徴とする半導体ウェハの試験方法。     A test method for a semiconductor wafer according to claim 6,
    The depressurization step is performed such that the adsorption force (F P ) generated with the depressurization in the sealed space is larger than the necessary pressing force (F N ) required for pressing the probe card (F P > F N ), depressurizing the inside of the sealed space, and a method for testing a semiconductor wafer.
  8. 　プローブカードを用いた半導体ウェハの試験に用いられる半導体ウェハ搬送装置であって、
    　前記半導体ウェハを保持する保持部材と、
    　前記プローブカードと前記保持部材との間に密閉空間を形成する密閉手段と、
    　前記密閉空間を減圧する減圧手段と、
    　前記減圧手段によって前記密閉空間を減圧した状態で、前記保持部材を前記プローブカードに対して相対移動させる移動手段と、を備えたことを特徴とする半導体ウェハ搬送装置。     A semiconductor wafer transfer device used for testing a semiconductor wafer using a probe card,
    A holding member for holding the semiconductor wafer;
    Sealing means for forming a sealed space between the probe card and the holding member;
    Decompression means for decompressing the sealed space;
    And a moving means for moving the holding member relative to the probe card in a state where the sealed space is decompressed by the decompressing means.
  9. 　請求項８に記載の半導体ウェハ搬送装置であって、
    　前記プローブカードは、カンチレバー型プローブカード又はバーチカル型プローブカードを含むことを特徴とする半導体ウェハ搬送装置。     The semiconductor wafer transfer device according to claim 8,
    The semiconductor wafer transfer apparatus, wherein the probe card includes a cantilever type probe card or a vertical type probe card.
  10. 　請求項８又は９に記載の半導体ウェハ搬送装置であって、
    　前記保持部材は、前記半導体ウェハが載置される載置面を有し、
    　前記密閉手段は、前記載置面に設けられた環状のシール部材を含むことを特徴とする半導体ウェハ搬送装置。     A semiconductor wafer transfer device according to claim 8 or 9,
    The holding member has a mounting surface on which the semiconductor wafer is mounted;
    The semiconductor wafer transfer apparatus, wherein the sealing means includes an annular seal member provided on the mounting surface.
  11. 　プローブカードを用いた半導体ウェハの試験に用いられる半導体ウェハ搬送装置であって、
    　前記半導体ウェハを保持する保持部材と、
    　前記プローブカードと前記保持部材との間に密閉空間を形成する密閉手段と、
    　前記密閉空間を減圧する減圧手段と、
    　前記保持部材に当接する当接部と、前記当接部を移動させる駆動部と、を有する当接手段と、を備えたことを特徴とする半導体ウェハ搬送装置。     A semiconductor wafer transfer device used for testing a semiconductor wafer using a probe card,
    A holding member for holding the semiconductor wafer;
    Sealing means for forming a sealed space between the probe card and the holding member;
    Decompression means for decompressing the sealed space;
    A semiconductor wafer transfer apparatus comprising: an abutting unit having an abutting part that abuts on the holding member; and a driving unit that moves the abutting part.
  12. 　請求項１１に記載の半導体ウェハ搬送装置であって、
    　前記プローブカードは、カンチレバー型プローブカード又はバーチカル型プローブカードを含むことを特徴とする半導体ウェハ搬送装置。     The semiconductor wafer transfer device according to claim 11,
    The semiconductor wafer transfer apparatus, wherein the probe card includes a cantilever type probe card or a vertical type probe card.
  13. 　請求項１１又は１２に記載の半導体ウェハ搬送装置であって、
    　前記保持部材は、前記半導体ウェハが載置される載置面を有し、
    　前記密閉手段は、前記載置面に設けられた環状のシール部材を含むことを特徴とする半導体ウェハ搬送装置。     It is a semiconductor wafer conveyance device according to claim 11 or 12,
    The holding member has a mounting surface on which the semiconductor wafer is mounted;
    The semiconductor wafer transfer apparatus, wherein the sealing means includes an annular seal member provided on the mounting surface.
  14. 　請求項１１～１３の何れかに記載の半導体ウェハ搬送装置であって、
    　前記駆動部は、ボールねじ機構が連結されたモータ、又は、圧電素子を含むことを特徴とする半導体ウェハ搬送装置。     A semiconductor wafer transfer device according to any one of claims 11 to 13,
    The semiconductor wafer transfer apparatus, wherein the driving unit includes a motor or a piezoelectric element connected to a ball screw mechanism.
  15. 　請求項１０～１４の何れかに記載の半導体ウェハ搬送装置であって、
    　複数の前記当接手段が、前記保持部材の外周部に当接するように周方向に沿って実質的に等間隔に配置されていることを特徴とする半導体ウェハ搬送装置。     The semiconductor wafer transfer device according to any one of claims 10 to 14,
    The semiconductor wafer transfer apparatus, wherein the plurality of contact means are arranged at substantially equal intervals along the circumferential direction so as to contact the outer peripheral portion of the holding member.
  16. 　プローブカードを用いて半導体ウェハを試験する半導体ウェハ試験装置であって、
    　前記プローブカードが電気的に接続される試験装置本体と、
    　請求項８～１５の何れかに記載の半導体ウェハ搬送装置と、を備えたことを特徴とする半導体ウェハ試験装置。     A semiconductor wafer testing apparatus for testing a semiconductor wafer using a probe card,
    A test apparatus body to which the probe card is electrically connected;
    A semiconductor wafer test apparatus comprising the semiconductor wafer transfer apparatus according to any one of claims 8 to 15.
PCT/JP2010/064608 2010-08-27 2010-08-27 Testing method for semiconductor wafer, semiconductor wafer transport device, and semiconductor wafer testing device WO2012026036A1 (en)

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