JP2016515321A5 - - Google Patents

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Publication number
JP2016515321A5
JP2016515321A5 JP2015558321A JP2015558321A JP2016515321A5 JP 2016515321 A5 JP2016515321 A5 JP 2016515321A5 JP 2015558321 A JP2015558321 A JP 2015558321A JP 2015558321 A JP2015558321 A JP 2015558321A JP 2016515321 A5 JP2016515321 A5 JP 2016515321A5
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JP
Japan
Prior art keywords
training sequence
sequence
received
clock signal
error
Prior art date
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Application number
JP2015558321A
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English (en)
Japanese (ja)
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JP2016515321A (ja
JP6165888B2 (ja
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Priority claimed from PCT/CN2013/071735 external-priority patent/WO2014127514A1/en
Publication of JP2016515321A publication Critical patent/JP2016515321A/ja
Publication of JP2016515321A5 publication Critical patent/JP2016515321A5/ja
Application granted granted Critical
Publication of JP6165888B2 publication Critical patent/JP6165888B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015558321A 2013-02-21 2013-02-21 １０ｇｂａｓｅ−ｔシステムにおけるデータ支援型タイミング回復のための方法および装置 Expired - Fee Related JP6165888B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/071735 WO2014127514A1 (en) 2013-02-21 2013-02-21 Method and apparatus for data aided timing recovery in 10gbase-t system

Publications (3)

Publication Number Publication Date
JP2016515321A JP2016515321A (ja) 2016-05-26
JP2016515321A5 true JP2016515321A5 (enExample) 2017-03-02
JP6165888B2 JP6165888B2 (ja) 2017-07-19

Family

ID=51390474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015558321A Expired - Fee Related JP6165888B2 (ja) 2013-02-21 2013-02-21 １０ｇｂａｓｅ−ｔシステムにおけるデータ支援型タイミング回復のための方法および装置

Country Status (6)

Country Link
US (1) US9544128B2 (enExample)
EP (1) EP2959629A4 (enExample)
JP (1) JP6165888B2 (enExample)
KR (1) KR101733660B1 (enExample)
CN (1) CN105122720B (enExample)
WO (1) WO2014127514A1 (enExample)

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US9647799B2 (en) * 2012-10-16 2017-05-09 Inphi Corporation FEC coding identification
US9921899B2 (en) * 2014-12-18 2018-03-20 Oracle International Corporation Monitoring serial link errors
US10050773B1 (en) * 2015-06-30 2018-08-14 Mosys, Inc. Bootstrapped autonegotiation clock from a referenceless clock chip
US10103837B2 (en) * 2016-06-23 2018-10-16 Advanced Micro Devices, Inc. Asynchronous feedback training
EP3297205A1 (en) * 2016-09-16 2018-03-21 Universiteit Gent Sequence aligner for synchronizing data
CN114268315A (zh) * 2020-09-16 2022-04-01 深圳市中兴微电子技术有限公司 环路滤波器、定时恢复方法和装置
CN119051826A (zh) * 2024-04-03 2024-11-29 上海交通大学 10GBase-T物理层同步与均衡方法及装置

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US5712873A (en) * 1996-06-04 1998-01-27 Thomson Consumer Electronics, Inc. Multi-mode equalizer in a digital video signal processing system
CN1061205C (zh) 1997-07-24 2001-01-24 北京信威通信技术有限公司 扩频通信系统中载波恢复和补偿的方法及其装置
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US8385470B2 (en) * 2000-12-05 2013-02-26 Google Inc. Coding a signal with a shuffled-Hadamard function
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US20030107986A1 (en) * 2001-12-11 2003-06-12 Sarnoff Corporation Method and apparatus for demodulating orthogonal frequency division multiplexed signals
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JP4456432B2 (ja) 2004-08-02 2010-04-28 富士通株式会社 基準信号を用いて同期伝送を行う装置および方法
JP2007004496A (ja) 2005-06-23 2007-01-11 Trusted Solutions Kk メール送付システムおよびメール送付方法
KR101206503B1 (ko) 2006-06-30 2012-11-29 삼성전자주식회사 스큐 제거 회로 및 그에 의한 스큐 제거 방법
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KR101375466B1 (ko) * 2009-01-12 2014-03-18 램버스 인코포레이티드 다중 전력 모드를 갖는 메조크로노스 시그널링 시스템
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US8406278B2 (en) * 2009-06-01 2013-03-26 At&T Intellectual Property I, L.P. Narrowband interference rejection for ultra-wideband systems
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