WO2022116901A1 - Iis总线译码方法、装置、示波器及计算机可读存储介质 - Google Patents

Iis总线译码方法、装置、示波器及计算机可读存储介质 Download PDF

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WO2022116901A1
WO2022116901A1 PCT/CN2021/133453 CN2021133453W WO2022116901A1 WO 2022116901 A1 WO2022116901 A1 WO 2022116901A1 CN 2021133453 W CN2021133453 W CN 2021133453W WO 2022116901 A1 WO2022116901 A1 WO 2022116901A1
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level
data
trigger
channel
time
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PCT/CN2021/133453
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French (fr)
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徐冬冬
刘福奇
周先冲
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深圳市道通科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • the present application relates to the technical field of serial buses, and in particular, to an IIS bus decoding method, device, oscilloscope, and computer-readable storage medium.
  • a serial bus is a type of bus used for data transfer.
  • IIS bus is a kind of serial bus, which is used to transmit data between audio devices and is widely used in multimedia devices.
  • the device receiving the data needs to decode the IIS data according to the encoding method of the IIS bus.
  • decoding the data transmitted by the IIS bus can be obtained, and system debugging and troubleshooting can be carried out according to the decoding data.
  • a decoding algorithm is generated according to the encoding method of the IIS bus to automatically decode the IIS bus.
  • the inventor found that when the IIS bus is decoded in the related art, if it is disturbed by noise, the decoding accuracy is not high.
  • embodiments of the present invention provide an IIS bus decoding method, device, oscilloscope, and computer-readable storage medium, which are used to solve the problem of inaccurate IIS bus decoding existing in the prior art.
  • a method for decoding an IIS bus comprising:
  • the sum of the trigger level threshold and trigger hysteresis of each data in the three-way data is determined as the rising edge trigger level of the data, and the difference between the trigger level threshold and the trigger hysteresis of the each data is determined. It is determined as the falling edge trigger level of the data of this channel;
  • the level change time of each channel of data wherein the start level is a high level or a low level, and the level change time includes a rising edge trigger time and a falling edge trigger time;
  • the IIS bus is decoded according to the start level and level change time of each channel of data.
  • the trigger hysteresis of any one of the three channels of data is determined in the following manner:
  • the product of the difference and a preset coefficient is determined as the trigger hysteresis.
  • the three-way data are respectively SCK, WS and SD, the SCK is a bit clock, the WS is a frame clock, and the SD is serial data;
  • the decoding of the IIS bus according to the start level and level change time of the data of each channel includes:
  • the level change time of the SCK is the rising edge trigger time
  • obtain the SD data corresponding to the level change time of the SCK save the SD data to the current frame, and the SD data is based on the SD data.
  • the starting level of the SD and the level change time of the SD are determined;
  • the level of the WS corresponding to the level change time of the SCK, and the level of the WS is determined according to the start level of the WS and the level jump time of the WS. If the level jumps within the time range of the current frame, the data of the current frame is output.
  • outputting the data of the current frame further includes:
  • an apparatus for decoding an IIS bus includes:
  • the first acquisition module is used to acquire the trigger level threshold and trigger hysteresis of each data in the three-way data of the IIS bus;
  • the determination module is used to determine the sum of the trigger level threshold and trigger hysteresis of each channel of data in the three channels of data as the rising edge trigger level of the channel data, and the trigger level threshold of each channel of data and the trigger level are determined.
  • the difference of the trigger lag is determined as the falling edge trigger level of the data of this channel;
  • the second acquisition module is used for acquiring the starting level of each channel of data, and according to the starting level, rising edge trigger level and falling edge trigger level of each channel of data, the power level of each channel of data is
  • the level signal is detected to obtain the level change time of each channel of data, wherein the start level is a high level or a low level, and the level change time includes a rising edge trigger time and a falling edge trigger time;
  • the decoding module is used for decoding the IIS bus according to the start level and the level change time of each channel of data.
  • the device further includes a setting module for:
  • the trigger lag amount is set as the product of the difference and a preset coefficient.
  • the three-way data are respectively SCK, WS and SD, the SCK is a bit clock, the WS is a frame clock, and the SD is serial data;
  • the decoding module is used for:
  • the level change time of the SCK is the rising edge trigger time
  • obtain the SD data corresponding to the level change time of the SCK save the SD data to the current frame, and the SD data is based on the SD data.
  • the starting level of the SD and the level change time of the SD are determined;
  • the level of the WS corresponding to the level change time of the SCK, and the level of the WS is determined according to the start level of the WS and the level jump time of the WS. If the level jumps within the time range of the current frame, the data of the current frame is output.
  • the decoding module is further used for:
  • an oscilloscope including: a processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface communicate with each other through the communication bus. Communication;
  • the memory is used for storing at least one executable instruction, and the executable instruction enables the processor to perform the operations of the above-mentioned IIS bus decoding method.
  • a computer-readable storage medium where at least one executable instruction is stored in the storage medium, and when the executable instruction is run on an oscilloscope, the oscilloscope executes the above-mentioned IIS Operation of the bus decoding method.
  • the trigger level threshold and trigger hysteresis of each of the three channels of data of the IIS bus by acquiring the trigger level threshold and trigger hysteresis of each of the three channels of data of the IIS bus, the sum of the trigger level threshold and trigger hysteresis of each of the three channels of data can be determined as the channel
  • the rising edge trigger level of the data, and the difference between the trigger level threshold and the trigger hysteresis of each channel of data is determined as the falling edge trigger level of the channel of data;
  • the starting level of each channel of data is obtained, according to the The starting level, rising edge trigger level and falling edge trigger level of each channel of data are detected by detecting the level signal of each channel of data, and the level change time of each channel of data can be obtained.
  • the starting level and level change time of the IIS bus can be decoded.
  • the sum of the trigger level threshold and trigger hysteresis of each channel of data in the three channels of data is determined as the rising edge trigger level of the channel of data, and the The difference between the trigger level threshold of the data and the trigger hysteresis is determined as the falling edge trigger level of this channel of data.
  • the level transition time can be delayed to prevent the level transition caused by excessive noise. Improve the accuracy of decoding.
  • FIG. 1 shows a schematic structural diagram of an oscilloscope provided by an embodiment of the present invention
  • FIG. 2 shows a schematic flowchart of an IIS bus decoding method provided by an embodiment of the present invention
  • FIG. 3 shows a schematic structural diagram of an IIS bus decoding apparatus provided by an embodiment of the present invention.
  • FIG. 1 shows a schematic structural diagram of an oscilloscope according to an embodiment of the present invention.
  • the specific embodiment of the present invention does not limit the specific implementation of the oscilloscope.
  • the oscilloscope may include: a processor (processor) 402 , a communication interface (Communications Interface) 404 , a memory (memory) 406 , and a communication bus 408 .
  • the processor 402 , the communication interface 404 , and the memory 406 communicate with each other through the communication bus 408 .
  • the communication interface 404 is used for communicating with network elements of other devices such as clients or other servers.
  • the processor 402 is used for executing the program 410 .
  • program 410 may include program code, which includes computer-executable instructions.
  • the processor 402 may be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
  • the one or more processors included in the oscilloscope may be the same type of processors, such as one or more CPUs; or may be different types of processors, such as one or more CPUs and one or more ASICs.
  • the memory 406 is used to store the program 410 .
  • Memory 406 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk memory.
  • the program 410 can be specifically called by the processor 402 to make the oscilloscope execute the operation of the IIS bus decoding method.
  • the oscilloscope of the embodiment of the present invention can make the oscilloscope execute the operation of the IIS bus decoding method by calling the program by the processor, so as to complete the decoding of the IIS bus. The following describes the process of the oscilloscope executing the IIS bus decoding method in detail.
  • FIG. 2 shows a flowchart of a method for decoding an IIS bus according to an embodiment of the present invention, and the method is executed by an oscilloscope. At least a program is stored in the memory of the oscilloscope, and the program causes the processor of the oscilloscope to execute the operation of the IIS bus decoding method. As shown in Figure 2, the method includes the following steps:
  • Step 110 Acquire the trigger level threshold and trigger hysteresis of each of the three channels of data of the IIS bus.
  • the three channels of data of the IIS bus are SCK, WS and SD respectively.
  • Each channel of data in the three channels of data is respectively set with a trigger level threshold and a trigger hysteresis, and the trigger level threshold and trigger hysteresis of each channel of data are carried out separately. set up.
  • the trigger level threshold of each of the three channels of data can be set according to the IIS bus protocol, and the trigger lag amount can be set according to the noise interference of the IIS bus. If the noise interference is large, the trigger lag amount is also set to be larger. If the noise interference is small, the trigger hysteresis is also set to be small.
  • the trigger hysteresis amount of any one of the three channels of data of the IIS bus can be determined in the following manner:
  • the level signal of the data at the preset frequency save the voltage value corresponding to the level signal in the preset array, obtain the maximum and minimum values of all data in the preset array, and calculate the maximum and minimum values
  • the product of the difference and the preset coefficient is determined as the trigger hysteresis amount.
  • the preset coefficient may be set to 1/10.
  • Step 120 Determine the sum of the trigger level threshold and trigger hysteresis amount of each channel of data in the three channels of data as the rising edge trigger level of the channel data, and determine the trigger level threshold and trigger hysteresis of each channel of data. The difference is determined as the falling edge trigger level of the data of this channel.
  • the rising edge trigger level and the falling edge trigger level of the channel of data can be determined.
  • the rising edge trigger level is the sum of the trigger level threshold and the trigger hysteresis
  • the falling edge trigger level is the difference between the trigger level threshold and the trigger hysteresis.
  • Step 130 Obtain the starting level of each channel of data, and detect the level signal of each channel of data according to the starting level, rising edge trigger level and falling edge trigger level of each channel of data , to obtain the level change time of each channel of data, wherein the start level is a high level or a low level, and the level change time includes a rising edge trigger time and a falling edge trigger time.
  • the level signal of each channel of data when the level signal of each channel of data is detected, if it is detected that before a certain time, the level value corresponding to the level signal is smaller than the rising edge trigger level, after the time, the level corresponding to the level signal is detected. If the level value of the level signal is greater than the rising edge trigger level, the time is determined as the rising edge trigger time; if it is detected that before a certain time, the level value corresponding to the level signal is greater than the falling edge trigger level, at this time After that, if the level value corresponding to the level signal is smaller than the falling edge trigger level, the time is determined as the falling edge trigger time.
  • the first level change time after the start level is the rising edge trigger time
  • the second level change time is the falling edge trigger time
  • the first level change time is the falling edge trigger time.
  • the time range between the change time and the second level change time is the duration of the high level. If the start level is high, the first level change time after the start level is the falling edge trigger time, the second level change time is the rising edge trigger time, and the first level change time
  • the time range between the second transition time is the duration of the low level.
  • Step 140 Decode the IIS bus according to the start level and level change time of each channel of data.
  • the three-way data of the IIS bus are SCK, WS and SD respectively, SCK is the bit clock, WS is the frame clock, SD is the serial data.
  • step 140 may further include:
  • Step 141 If it is determined that the level change time of the SCK is the rising edge trigger time, obtain the SD data corresponding to the level change time of the SCK, save the SD data to the current frame, and the SD data is based on The start level of the SD and the level change time of the SD are determined.
  • SCK receives data on the rising edge, so it is necessary to obtain the rising edge trigger time of SCK, and obtain the corresponding SD data according to the rising edge trigger time of SCK. Further, the level change time of SCK can be traversed. If it is judged that the level change time of SCK is the rising edge trigger time, the SD data corresponding to the rising edge trigger time is read, and the read SD data is saved to the current state. frame.
  • the current frame generally includes multi-bit SD data, and the current frame corresponds to the left channel or the right channel.
  • the level change time of the next SCK when traversing the level change time of the SCK, can be determined according to the level change time of the previous SCK. For example, if the level change time of the previous SCK is the rising edge trigger time, the level change time of the next SCK is the falling edge trigger time; if the level change time of the previous SCK is the falling edge trigger time, the next SCK level change time is the falling edge trigger time. The level change time of SCK is the rising edge trigger time.
  • Step 142 Obtain the level of WS corresponding to the level change time of the SCK.
  • the level of the WS is determined according to the start level of the WS and the level jump time of the WS. If the level of the WS jumps within the time range of the current frame, the data of the current frame is output.
  • the level of WS is determined according to the start level of WS and the level transition time of WS.
  • the data of the current frame is binary data, if it is judged that the level of WS jumps within the time range of the current frame, the data of the current frame is converted into hexadecimal, and the output is converted into The data of the current frame in hexadecimal, after outputting the data of the current frame, obtain and save the data of the next frame.
  • the data of the current frame when WS is at a high level, the data of the current frame corresponds to the left channel, and when WS is at a low level, the data of the current frame corresponds to the right channel. If it is determined that the level of WS jumps within the time range of the current frame, it means that the data of the current frame needs to be output to the corresponding channel. It can be understood that if it is determined that the jump level of WS is a falling edge trigger level, the data of the current frame is output to the left channel, and the data of the next frame is output to the right channel. If it is determined that the jump level of WS is the rising edge trigger level, the data of the current frame is output to the right channel, and the data of the next frame is output to the left channel.
  • the data of the current frame is the frame data saved in the time between the time when the WS level jump is detected last time and the time when the WS level jump is detected currently.
  • the trigger level threshold and trigger hysteresis of each of the three channels of data of the IIS bus by acquiring the trigger level threshold and trigger hysteresis of each of the three channels of data of the IIS bus, the sum of the trigger level threshold and trigger hysteresis of each of the three channels of data can be determined as the channel
  • the rising edge trigger level of the data, and the difference between the trigger level threshold and the trigger hysteresis of each channel of data is determined as the falling edge trigger level of the channel of data;
  • the starting level of each channel of data is obtained, according to the The start level, rising edge trigger level and falling edge trigger level of each channel of data are detected by detecting the level signal of each channel of data, and the level change time of each channel of data can be obtained.
  • the starting level and level change time of the IIS bus can be decoded.
  • the sum of the trigger level threshold and trigger hysteresis of each channel of data in the three channels of data is determined as the rising edge trigger level of the channel of data, and the The difference between the trigger level threshold of the data and the trigger hysteresis is determined as the falling edge trigger level of the data of this channel.
  • FIG. 3 shows a schematic structural diagram of an IIS bus decoding apparatus according to an embodiment of the present invention. As shown in Figure 3, the device includes:
  • the first acquisition module 310 is used to acquire the trigger level threshold and trigger hysteresis amount of each channel of data in the three channels of data of the IIS bus;
  • the determining module 320 is used to determine the sum of the trigger level threshold and the trigger hysteresis amount of each channel of data in the three channels of data as the rising edge trigger level of the channel data, and the trigger level threshold value of each channel of data is determined. And the difference between the trigger lag amount is determined as the falling edge trigger level of the data of this channel;
  • the second obtaining module 330 is configured to obtain the start level of each channel of data, and the data of each channel of data is determined according to the start level, rising edge trigger level and falling edge trigger level of each channel of data.
  • the level signal is detected to obtain the level change time of each channel of data, wherein the start level is a high level or a low level, and the level change time includes a rising edge trigger time and a falling edge. trigger time;
  • the decoding module 340 is used for decoding the IIS bus according to the start level and the level change time of each channel of data.
  • the apparatus further includes a setting module 350 for:
  • the trigger lag amount is set as the product of the difference and a preset coefficient.
  • the three-way data are respectively SCK, WS and SD, the SCK is a bit clock, the WS is a frame clock, and the SD is serial data;
  • the decoding module 340 is used to:
  • the level change time of the SCK is the rising edge trigger time
  • obtain the SD data corresponding to the level change time of the SCK save the SD data to the current frame, and the SD data is based on the SD data.
  • the starting level of the SD and the level change time of the SD are determined;
  • the level of the WS corresponding to the level change time of the SCK, and the level of the WS is determined according to the start level of the WS and the level jump time of the WS. If the level jumps within the time range of the current frame, the data of the current frame is output.
  • the decoding module 340 is further configured to:
  • the first acquisition module can acquire the trigger level threshold and trigger hysteresis of each of the three channels of data of the IIS bus, and the determination module can acquire the trigger level threshold and trigger hysteresis of each of the three channels of data.
  • the sum of the amount is determined as the rising edge trigger level of this road data, and the difference between the trigger level threshold and trigger hysteresis amount of each road data is determined as the falling edge trigger level of this road data;
  • the second acquisition module can obtain The starting level of each channel of data, according to the starting level, rising edge trigger level and falling edge trigger level of each channel of data, the level signal of each channel of data can be detected, and the level change of each channel of data can be obtained.
  • the decoding module can decode the IIS bus according to the starting level and level change time of each channel of data. It can be seen that the IIS bus decoding device according to the embodiment of the present invention determines the sum of the trigger level threshold and the trigger hysteresis amount of each channel of data in the three channels of data as the rising edge trigger level of the channel data, The difference between the trigger level threshold of the data and the trigger hysteresis is determined as the falling edge trigger level of the data of this channel. By adding the trigger hysteresis, the time of level change can be delayed to prevent the level change caused by excessive noise, so it can be Improve the accuracy of decoding.
  • An embodiment of the present invention provides a computer-readable storage medium, where the storage medium stores at least one executable instruction, and when the executable instruction runs on an IIS bus decoding apparatus, the IIS bus decoding apparatus executes the above-mentioned The IIS bus decoding method in any method embodiment.
  • An embodiment of the present invention provides an IIS bus decoding apparatus for executing the above-mentioned IIS bus decoding method.
  • An embodiment of the present invention provides a computer program, which can be invoked by a processor to cause an oscilloscope to execute the IIS bus decoding method in any of the foregoing method embodiments.
  • An embodiment of the present invention provides a computer program product.
  • the computer program product includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions.
  • the program instructions When the program instructions are run on a computer, the computer is made to execute any of the above.
  • modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment.
  • the modules or units or components in the embodiments may be combined into one module or unit or component, and they may be divided into multiple sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination unless at least some of such features and/or procedures or elements are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

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Abstract

本发明实施例涉及串行总线技术领域，公开了一种IIS总线译码方法、装置、示波器及计算机可读存储介质。该方法包括：获取IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量；将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；获取每一路数据的起始电平，根据每一路数据的起始电平、上升沿触发电平及下降沿触发电平对每一路数据的电平信号进行检测，以获取每一路数据的电平变化时间；根据每一路数据的起始电平及电平变化时间对IIS总线进行译码。通过上述方式，本发明实施例实现了对IIS总线的准确译码。

Description

IIS总线译码方法、装置、示波器及计算机可读存储介质
本申请要求于2020年12月3日提交中国专利局、申请号为202011395822.6、申请名称为“IIS总线译码方法、装置、示波器及计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及串行总线技术领域，具体涉及一种IIS总线译码方法、装置、示波器及计算机可读存储介质。
背景技术
串行总线是一种用于数据传输的总线。IIS总线是串行总线的一种，用于在音频设备之间传输数据，在多媒体设备中有着广泛的应用。
在利用IIS总线传输数据时，接收数据的设备需要根据IIS总线的编码方法对IIS数据进行译码。通过译码可以获取IIS总线传输的数据，并且可以根据译码数据进行系统调试和故障排除。相关技术中，根据IIS总线的编码方法生成译码算法，以自动对IIS总线进行译码。然而，发明人在实现本发明的过程中发现：相关技术中对于IIS总线进行译码时，若受到噪声的干扰，则译码的准确度不高。
发明内容
鉴于上述问题，本发明实施例提供了一种IIS总线译码方法、装置、示波器及计算机可读存储介质，用于解决现有技术中存在的IIS总线译码不准确的问题。
根据本发明实施例的一个方面，提供了一种IIS总线译码方法，所述方法包括：
获取所述IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量；
将所述三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；
获取所述每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，以获取所述每一路数据的电平变化时间，其中，所述起始电平为高电平或低电平，所述电平变化时间包括上升沿触发时间和下降沿触发时间；
根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码。
在一种可选的方式中，所述三路数据中任意一路数据的触发滞后量通过如下方式进行确定：
按照预设频率采集所述任意一路数据的电平信号；
将所述电平信号所对应的电压值保存至预设数组中；
获取所述预设数组中所有数据的最大值和最小值，并计算所述最大值和所述最小值的差值；
将所述差值与预设系数的乘积确定为所述触发滞后量。
在一种可选的方式中，所述三路数据分别为SCK、WS和SD，所述SCK为位时钟，所述WS为帧时钟，所述SD为串行数据；
所述根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码包括：
若判断所述SCK的电平变化时间为上升沿触发时间，则获取所述SCK的电平变化时间所对应的SD数据，将所述SD数据保存至当前帧，所述SD数据根据所述SD的起始电平及所述SD的电平变化时间确定；
获取所述SCK的电平变化时间所对应的WS的电平，所述WS的电平根据所述WS的起始电平及所述WS的电平跳转时间确定，若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据。
在一种可选的方式中，所述若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据进一步包括：
若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则将所述当前帧的数据转换为十六进制；
输出所述转换为十六进制的所述当前帧的数据。
根据本发明实施例的另一方面，提供了一种IIS总线译码装置，所述装置包括：
第一获取模块，用于获取所述IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量；
确定模块，用于将所述三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；
第二获取模块，用于获取所述每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，以获取所述每一路数据的电平变化时间，其中，所述起始电平为高电平或低电平，所述电平变化时间包括上升沿触发时间和下降沿触发时间；
译码模块，用于根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码。
在一种可选的方式中，所述装置还包括设置模块，用于：
按照预设频率采集所述任意一路数据的电平信号；
将所述电平信号所对应的电压值保存至预设数组中；
获取所述预设数组中所有数据的最大值和最小值，并计算所述最大值和所述最小值的差值；
将所述触发滞后量设置为所述差值与预设系数的乘积。
在一种可选的方式中，所述三路数据分别为SCK、WS和SD，所述SCK为位时钟，所述WS为帧时钟，所述SD为串行数据；
所述译码模块用于：
若判断所述SCK的电平变化时间为上升沿触发时间，则获取所述SCK的电平变化时间所对应的SD数据，将所述SD数据保存至当前帧，所述SD数据根据所述SD的起始电平及所述SD的电平变化时间确定；
获取所述SCK的电平变化时间所对应的WS的电平，所述WS的电平根据所述WS的起始电平及所述WS的电平跳转时间确定，若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据。
在一种可选的方式中，所述译码模块进一步用于：
若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则将所述当前帧的数据转换为十六进制；
输出所述转换为十六进制的所述当前帧的数据。
根据本发明实施例的另一方面，提供了一种示波器，包括：处理器、存储器、通信接口和通信总线，所述处理器、所述存储器和所述通信接口通过所述通信总线完成相互间的通信；
所述存储器用于存放至少一可执行指令，所述可执行指令使所述处理器执行上述的IIS总线译码方法的操作。
根据本发明实施例的又一方面，提供了一种计算机可读存储介质，所述存储介质中存储有至少一可执行指令，所述可执行指令在示波器上运行时，使得示波器执行上述的IIS总线译码方法的操作。
本发明实施例通过获取IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量，可以将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；获取每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，可以获取所述每一路数据的电平变化时间，根据每一路数据的起始电平及电平变化时间可以对IIS总线进行译码。可以看出，本发明实施例的IIS总线译码方法将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平，通过加入触发滞后量可以延迟电平变换的时间，防止由于噪声过大引起的电平变换，因而可以提高译码的准确度。
上述说明仅是本发明实施例技术方案的概述，为了能够更清楚了解本发明实施例的技术手段，而可依照说明书的内容予以实施，并且为了让本发明实施 例的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
附图仅用于示出实施方式，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1示出了本发明实施例提供的示波器的结构示意图；
图2示出了本发明实施例提供的IIS总线译码方法的流程示意图；
图3示出了本发明实施例提供的IIS总线译码装置的结构示意图。
具体实施方式
下面将参照附图更详细地描述本发明的示例性实施例。虽然附图中显示了本发明的示例性实施例，然而应当理解，可以以各种形式实现本发明而不应被这里阐述的实施例所限制。
图1示出了本发明实施例示波器的结构示意图，本发明具体实施例并不对示波器的具体实现做限定。
如图1所示，该示波器可以包括：处理器(processor)402、通信接口(Communications Interface)404、存储器(memory)406、以及通信总线408。
其中：处理器402、通信接口404、以及存储器406通过通信总线408完成相互间的通信。通信接口404，用于与其它设备比如客户端或其它服务器等的网元通信。处理器402，用于执行程序410。
具体地，程序410可以包括程序代码，该程序代码包括计算机可执行指令。
处理器402可能是中央处理器CPU，或者是特定集成电路ASIC(Application Specific Integrated Circuit)，或者是被配置成实施本发明实施例的一个或多个集成电路。示波器包括的一个或多个处理器，可以是同一类型的处理器，如一个或多个CPU；也可以是不同类型的处理器，如一个或多个CPU以及一个或多个ASIC。
存储器406，用于存放程序410。存储器406可能包含高速RAM存储器，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
程序410具体可以被处理器402调用使示波器执行IIS总线译码方法的操作。本发明实施例的示波器通过处理器调用程序可以使示波器执行IIS总线译码方法的操作，从而完成对IIS总线的译码。下面对示波器执行IIS总线译码方法的过程进行详细说明。
图2示出了本发明实施例IIS总线译码方法的流程图，该方法由示波器执行。示波器的存储器中存放至少程序，该程序使示波器的处理器执行IIS总线译码方法的操作。如图2所示，该方法包括以下步骤：
步骤110：获取所述IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量。
其中，IIS总线的三路数据分别为SCK、WS和SD，三路数据中每一路数据分别设置有触发电平阈值和触发滞后量，且每一路数据的触发电平阈值和触发滞后量单独进行设置。可以根据IIS总线协议对三路数据中每一路数据的触发电平阈值进行设置，根据IIS总线所受到噪声干扰的大小对触发滞后量进行设置，若噪声干扰较大，则触发滞后量也设置较大，若噪声干扰较小，则触发滞后量也设置较小。
在一种优选的实施方式中，可以对IIS总线的三路数据中任意一路数据的触发滞后量通过如下方式进行确定：
按照预设频率采集该路数据的电平信号，将电平信号所对应的电压值保存至预设数组中，获取预设数组中所有数据的最大值和最小值，并计算最大值和最小值的差值，将差值与预设系数的乘积确定为触发滞后量。优选的，预设系数可以设置为1/10。
步骤120：将所述三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平。
其中，根据三路数据中每一路数据的触发电平阈值及触发滞后量可以确定该路数据的上升沿触发电平和下降沿触发电平。上升沿触发电平为触发电平阈值及触发滞后量的和，下降沿触发电平为触发电平阈值及触发滞后量的差。
步骤130：获取所述每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，以获取所述每一路数据的电平变化时间，其中，所述起始电平为高电平或低电平，所述电平变化时间包括上升沿触发时间和下降沿触发时间。
其中，在对每一路数据的电平信号进行检测时，若检测到在某一时间之前，电平信号所对应的电平值小于上升沿触发电平，在该时间之后，电平信号所对应的电平值大于上升沿触发电平，则将该时间确定为上升沿触发时间；若检测到在某一时间之前，电平信号所对应的电平值大于下降沿触发电平，在该时间之后，电平信号所对应的电平值小于下降沿触发电平，则将该时间确定为下降沿触发时间。
其中，若起始电平为低电平，则起始电平之后的第一个电平变化时间为上升沿触发时间，第二个电平变化时间为下降沿触发时间，第一个电平变化时间与第二个电平变化时间之间的时间范围为高电平的持续时间。若起始电平为高电平，则起始电平之后的第一个电平变化时间为下降沿触发时间，第二个电平变化时间为上升沿触发时间，第一个电平变化时间与第二个电平变化时间之间的时间范围为低电平的持续时间。
步骤140：根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码。
其中，IIS总线的三路数据分别为SCK、WS和SD，SCK为位时钟，WS为帧时钟，SD为串行数据。
在一种优选的实施方式中，步骤140可以进一步包括：
步骤141：若判断所述SCK的电平变化时间为上升沿触发时间，则获取所述SCK的电平变化时间所对应的SD数据，将所述SD数据保存至当前帧，所述SD数据根据所述SD的起始电平及所述SD的电平变化时间确定。
其中，根据IIS总线协议，SCK在上升沿接收数据，因此需要获取SCK的上升沿触发时间，根据SCK的上升沿触发时间获取对应的SD数据。进一步的，可以遍历SCK的电平变化时间，若判断SCK的电平变化时间为上升沿触发时间，则读取对应于该上升沿触发时间的SD数据，并将读取的SD数据保存至当前帧。当前帧一般包括多位SD数据，并且当前帧对应左声道或者右声道。
其中，在遍历SCK的电平变化时间时，可以根据上一SCK的电平变化时间判断下一SCK的电平变化时间。例如，若上一SCK的电平变化时间为上升沿触发时间，则下一SCK的电平变化时间为下降沿触发时间；若上一SCK的电平变化时间为下降沿触发时间，则下一SCK的电平变化时间为上升沿触发时间。
步骤142：获取所述SCK的电平变化时间所对应的WS的电平，所述WS的电平根据所述WS的起始电平及所述WS的电平跳转时间确定，若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据。
其中，获取SCK的电平变化时间所对应的WS的电平后，若判断WS的电平在当前帧的时间范围内发生跳转，则说明当前帧的数据源已经采集完毕，需要输出当前帧的数据。WS的电平根据WS的起始电平及WS的电平跳转时间确定。
在一种优选的实施方式中，当前帧的数据为二进制数据，若判断WS的电平在当前帧的时间范围内发生跳转，则将当前帧的数据转换为十六进制，输出转换为十六进制的当前帧的数据，输出当前帧的数据之后，获取并保存下一帧的数据。
其中，WS为高电平时，当前帧的数据对应于左声道，WS为低电平时，当前帧的数据对应于右声道。若判断WS的电平在当前帧的时间范围内发生跳转，则说明需要将当前帧的数据输出至对应声道。可以理解的，若判断WS的跳转电平为下降沿触发电平，则将当前帧的数据输出至左声道，并将下一帧的数据输出至右声道。若判断WS的跳转电平为上升沿触发电平，则将当前帧的数据输出至右声道，并将下一帧的数据输出至左声道。当前帧的数据为上一次检测到WS电平发生跳转的时刻与当前检测到WS电平发生跳转的时刻之间的时间所保存的帧数据。
本发明实施例通过获取IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量，可以将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；获取每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所 述每一路数据的电平信号进行检测，可以获取所述每一路数据的电平变化时间，根据每一路数据的起始电平及电平变化时间可以对IIS总线进行译码。可以看出，本发明实施例的IIS总线译码方法将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平，通过加入触发滞后量可以延迟电平变换的时间，防止由于噪声过大引起的电平变换，因而可以提高译码的准确度。
图3示出了本发明实施例IIS总线译码装置的结构示意图。如图3所示，该装置包括：
第一获取模块310，用于获取所述IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量；
确定模块320，用于将所述三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；
第二获取模块330，用于获取所述每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，以获取所述每一路数据的电平变化时间，其中，所述起始电平为高电平或低电平，所述电平变化时间包括上升沿触发时间和下降沿触发时间；
译码模块340，用于根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码。
在一种可选的方式中，该装置还包括设置模块350，用于：
按照预设频率采集所述任意一路数据的电平信号；
将所述电平信号所对应的电压值保存至预设数组中；
获取所述预设数组中所有数据的最大值和最小值，并计算所述最大值和所述最小值的差值；
将所述触发滞后量设置为所述差值与预设系数的乘积。
在一种可选的方式中，所述三路数据分别为SCK、WS和SD，所述SCK为位时钟，所述WS为帧时钟，所述SD为串行数据；
译码模块340用于：
若判断所述SCK的电平变化时间为上升沿触发时间，则获取所述SCK的电平变化时间所对应的SD数据，将所述SD数据保存至当前帧，所述SD数据根据所述SD的起始电平及所述SD的电平变化时间确定；
获取所述SCK的电平变化时间所对应的WS的电平，所述WS的电平根据所述WS的起始电平及所述WS的电平跳转时间确定，若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据。
在一种可选的方式中，译码模块340进一步用于：
若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则将所述当 前帧的数据转换为十六进制；
输出所述转换为十六进制的所述当前帧的数据。
本发明实施例通过第一获取模块可以获取IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量，确定模块可以将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；第二获取模块可以获取每一路数据的起始电平，根据每一路数据的起始电平、上升沿触发电平及下降沿触发电平对每一路数据的电平信号进行检测，可以获取每一路数据的电平变化时间，译码模块可以根据每一路数据的起始电平及电平变化时间对IIS总线进行译码。可以看出，本发明实施例的IIS总线译码装置将三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平，通过加入触发滞后量可以延迟电平变换的时间，防止由于噪声过大引起的电平变换，因而可以提高译码的准确度。
本发明实施例提供了一种计算机可读存储介质，所述存储介质存储有至少一可执行指令，该可执行指令在IIS总线译码装置上运行时，使得所述IIS总线译码装置执行上述任意方法实施例中的IIS总线译码方法。
本发明实施例提供一种IIS总线译码装置，用于执行上述IIS总线译码方法。
本发明实施例提供了一种计算机程序，所述计算机程序可被处理器调用使示波器执行上述任意方法实施例中的IIS总线译码方法。
本发明实施例提供了一种计算机程序产品，计算机程序产品包括存储在计算机可读存储介质上的计算机程序，计算机程序包括程序指令，当程序指令在计算机上运行时，使得所述计算机执行上述任意方法实施例中的IIS总线译码方法。
在此提供的算法或显示不与任何特定计算机、虚拟系统或者其它设备固有相关。各种通用系统也可以与基于在此的示教一起使用。根据上面的描述，构造这类系统所要求的结构是显而易见的。此外，本发明实施例也不针对任何特定编程语言。应当明白，可以利用各种编程语言实现在此描述的本发明的内容，并且上面对特定语言所做的描述是为了披露本发明的最佳实施方式。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本发明并帮助理解各个发明方面中的一个或多个，在上面对本发明的示例性实施例的描述中，本发明实施例的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。
本领域技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。上述实施例中的步骤，除有特殊说明外，不应理解为对执行顺序的限定。

Claims (10)

  1. 一种IIS总线译码方法，其特征在于，所述方法包括：
    获取所述IIS总线的三路数据中每一路数据的触发电平阈值及触发滞后量；
    将所述三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；
    获取所述每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，以获取所述每一路数据的电平变化时间，其中，所述起始电平为高电平或低电平，所述电平变化时间包括上升沿触发时间和下降沿触发时间；
    根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码。
  2. 根据权利要求1所述的方法，其特征在于，所述三路数据中任意一路数据的触发滞后量通过如下方式进行确定：
    按照预设频率采集所述任意一路数据的电平信号；
    将所述电平信号所对应的电压值保存至预设数组中；
    获取所述预设数组中所有数据的最大值和最小值，并计算所述最大值和所述最小值的差值；
    将所述差值与预设系数的乘积确定为所述触发滞后量。
  3. 根据权利要求1或2所述的方法，其特征在于，所述三路数据分别为SCK、WS和SD，所述SCK为位时钟，所述WS为帧时钟，所述SD为串行数据；
    所述根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码包括：
    若判断所述SCK的电平变化时间为上升沿触发时间，则获取所述SCK的电平变化时间所对应的SD数据，将所述SD数据保存至当前帧，所述SD数据根据所述SD的起始电平及所述SD的电平变化时间确定；
    获取所述SCK的电平变化时间所对应的WS的电平，所述WS的电平根据所述WS的起始电平及所述WS的电平跳转时间确定，若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据。
  4. 根据权利要求3所述的方法，其特征在于，所述若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据进一步包括：
    若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则将所述当前帧的数据转换为十六进制；
    输出所述转换为十六进制的所述当前帧的数据。
  5. 一种IIS总线译码装置，其特征在于，所述装置包括：
    第一获取模块，用于获取所述IIS总线的三路数据中每一路数据的触发电 平阈值及触发滞后量；
    确定模块，用于将所述三路数据中每一路数据的触发电平阈值及触发滞后量的和确定为该路数据的上升沿触发电平，将所述每一路数据的触发电平阈值及触发滞后量的差确定为该路数据的下降沿触发电平；
    第二获取模块，用于获取所述每一路数据的起始电平，根据所述每一路数据的起始电平、上升沿触发电平及下降沿触发电平对所述每一路数据的电平信号进行检测，以获取所述每一路数据的电平变化时间，其中，所述起始电平为高电平或低电平，所述电平变化时间包括上升沿触发时间和下降沿触发时间；
    译码模块，用于根据所述每一路数据的起始电平及电平变化时间对所述IIS总线进行译码。
  6. 根据权利要求5所述的装置，其特征在于，所述装置还包括设置模块，用于：
    按照预设频率采集所述任意一路数据的电平信号；
    将所述电平信号所对应的电压值保存至预设数组中；
    获取所述预设数组中所有数据的最大值和最小值，并计算所述最大值和所述最小值的差值；
    将所述触发滞后量设置为所述差值与预设系数的乘积。
  7. 根据权利要求5或6所述的装置，其特征在于，所述三路数据分别为SCK、WS和SD，所述SCK为位时钟，所述WS为帧时钟，所述SD为串行数据；
    所述译码模块用于：
    若判断所述SCK的电平变化时间为上升沿触发时间，则获取所述SCK的电平变化时间所对应的SD数据，将所述SD数据保存至当前帧，所述SD数据根据所述SD的起始电平及所述SD的电平变化时间确定；
    获取所述SCK的电平变化时间所对应的WS的电平，所述WS的电平根据所述WS的起始电平及所述WS的电平跳转时间确定，若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则输出所述当前帧的数据。
  8. 根据权利要求7所述的方法，其特征在于，所述译码模块进一步用于：
    若判断所述WS的电平在所述当前帧的时间范围内发生跳转，则将所述当前帧的数据转换为十六进制；
    输出所述转换为十六进制的所述当前帧的数据。
  9. 一种示波器，其特征在于，包括：处理器、存储器、通信接口和通信总线，所述处理器、所述存储器和所述通信接口通过所述通信总线完成相互间的通信；
    所述存储器用于存放至少一可执行指令，所述可执行指令使所述处理器执行如权利要求1-4任意一项所述的IIS总线译码方法的操作。
  10. 一种计算机可读存储介质，其特征在于，所述存储介质中存储有至少一可执行指令，所述可执行指令在示波器上运行时，使得示波器执行如权利要求1-4任意一项所述的IIS总线译码方法的操作。
PCT/CN2021/133453 2020-12-03 2021-11-26 Iis总线译码方法、装置、示波器及计算机可读存储介质 WO2022116901A1 (zh)

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