JP2015526883A - シリコンオンインシュレータ基板上に導波路の光分離を提供する方法および構造 - Google Patents
シリコンオンインシュレータ基板上に導波路の光分離を提供する方法および構造 Download PDFInfo
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12035—Materials
- G02B2006/12061—Silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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Abstract
Description
Claims (34)
- 集積構造を形成する方法であって、
第1の基板中に分離領域を形成する行為と、
第2の基板上にフォトニクス区域を形成する行為と、
前記分離領域が前記フォトニクス区域と整列するように、前記第1および第2の基板を一緒に接合する行為と、
を含む、方法。 - 前記第1および第2の基板が各々、シリコン基板を備え、前記フォトニクス区域が、シリコンフォトニクス区域である、請求項1に記載の方法。
- 導波路コアが前記分離領域と整列するように、前記導波路を前記シリコンフォトニクス区域内に形成することをさらに含む、請求項2に記載の方法。
- 前記第1および第2の基板が一緒に接合された後に前記導波路が形成される、請求項3に記載の方法。
- 浅いトレンチ分離領域として前記分離領域を形成することをさらに含む、請求項2に記載の方法。
- 前記シリコンフォトニクス区域の下位に前記第2の基板の一部としてBOXを形成することをさらに含み、前記BOXと浅いトレンチ分離領域を合わせた厚さが少なくとも1umである、請求項5に記載の方法。
- 前記BOXの厚さが、200nm以下である、請求項6に記載の方法。
- 前記浅いトレンチ分離領域の厚さが、約800nm〜約1200nmの範囲である、請求項6に記載の方法。
- 前記導波路コアを包囲するようにクラッディング領域を形成することをさらに含み、前記クラッディング領域が、前記導波路の下に位置付けられる前記第2の基板上の第1の誘電体によって少なくとも部分的に形成される、請求項3に記載の方法。
- 前記導波路コアがシリコンで形成され、前記第1の誘電体が酸化物を含む、請求項9に記載の方法。
- 前記第1の誘電体が二酸化シリコンを含む、請求項10に記載の方法。
- 前記クラッディング領域が、前記導波路の側面上に第2の誘電体をさらに備える、請求項9に記載の方法。
- 前記第1および第2の誘電体が、二酸化シリコンを含む、請求項10に記載の方法。
- 前記接合が、非晶質シリコンを前記第1および第2の基板のうちの少なくとも一方の上に形成することと、前記非晶質シリコンが接合材料として機能して前記第1の基板を前記第2の基板に接合するように、前記基板を一緒に押圧することと、をさらに含む、請求項2に記載の方法。
- 前記第2の基板が絶縁体をさらに備え、前記第1および第2の基板の前記接合が、埋め込み絶縁体を有するシリコンオンインシュレータ構造を形成する、請求項2に記載の方法。
- 前記第2の基板が、前記シリコンに隣接して誘電体材料をさらに備え、前記方法が、前記導波路が形成される前に、前記第2の基板シリコンを薄層化することをさらに含む、請求項2に記載の方法。
- 前記第2の基板シリコンが、切断線を形成するようにドーパントをインプラントして、次に、前記切断線に沿って切断して、前記シリコンの一部分を除去することによって薄層化される、請求項16に記載の方法。
- 前記第2の基板シリコンの前記除去された部分を、別の集積構造中の基板として用いられるように再利用することをさらに含む、請求項17に記載の方法。
- 前記トレンチ分離領域を含む側面の反対側の側面から前記第1の基板を薄層化することを含む、請求項2に記載の方法。
- 前記第1の基板の前記薄層化が、ドーパントを前記第1の基板の前記シリコンにインプラントして切断線を形成し、次に、前記第1の基板の前記シリコンを前記切断線に沿って切断して前記シリコンの一部分を除去することを含む、請求項19に記載の方法。
- 前記第1の基板の前記シリコンの前記除去された部分を、別の集積構造中の基板として用いられるように再利用することをさらに含む、請求項20に記載の方法。
- 前記第1および第2の基板が半導体材料を備え、前記フォトニクス区域が、前記第2の基板の前記半導体材料から形成され、前記方法が、前記第2の基板の前記半導体材料を用いて導波路コアを形成することをさらに含む、請求項1に記載の方法。
- 前記半導体材料がシリコンを含む、請求項22に記載の方法。
- 前記第2の基板上に回路素子区域を形成することをさらに含む、請求項1に記載の方法。
- 集積構造であって、
内部に形成された浅いトレンチ分離領域を有する第1の半導体基板であって、前記分離領域の前記トレンチが、第1の屈折率を有する誘電体材料によって充填される、第1の半導体基板と、
前記第1の基板に取り付けられ、かつ前記第1の基板に対面する誘電体材料および前記誘電体材料上の半導体材料から形成された導波路を含む第2の基板であって、前記導波路が、前記第1の屈折率よりも大きい第2の屈折率を有する材料で形成され、かつ前記浅いトレンチ分離領域上に位置付けられる、第2の基板と、
を備える集積構造。 - 前記浅いトレンチ分離領域が、前記トレンチ内の二酸化シリコンを含む、請求項25に記載の構造。
- 前記第2の基板に対面する前記誘電体材料と、前記浅いトレンチ分離領域との前記合成厚さが、少なくとも1000nmである、請求項25に記載の構造。
- 前記第1および第2の基板がシリコンを含む、請求項25に記載の構造。
- 前記導波路が、クラッディング領域に包囲されたコア領域を含み、前記クラッディング領域が、少なくとも部分的に、前記第2の基板上の前記誘電体材料によって形成される、請求項25に記載の構造。
- 前記コア領域がシリコンを含み、前記クラッディング領域が二酸化シリコンを含む、請求項25に記載の構造。
- 電子回路素子が上に形成される前記第2の基板の前記半導体材料の区域をさらに含む、請求項25に記載の構造。
- 前記取り付けられた第1および第2の基板が、シリコンオンインシュレータ構造を形成する、請求項25に記載の構造。
- 前記第2の基板の前記半導体材料の上の誘電体材料をさらに備える、請求項23に記載の構造。
- 前記第2の基板の前記半導体材料上の前記誘電体材料が、中間層誘電体構造の一部である、請求項33に記載の構造。
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US13/487,573 | 2012-06-04 | ||
US13/487,573 US9709740B2 (en) | 2012-06-04 | 2012-06-04 | Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate |
PCT/US2013/043347 WO2014042716A1 (en) | 2012-06-04 | 2013-05-30 | Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate |
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KR (1) | KR101770886B1 (ja) |
CN (1) | CN104412375B (ja) |
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JP6353440B2 (ja) | 2018-07-04 |
KR20150013900A (ko) | 2015-02-05 |
US9709740B2 (en) | 2017-07-18 |
EP2856499B1 (en) | 2024-02-07 |
CN104412375B (zh) | 2018-03-09 |
KR101770886B1 (ko) | 2017-08-23 |
US20190377133A1 (en) | 2019-12-12 |
SG11201408258TA (en) | 2015-02-27 |
US20130322811A1 (en) | 2013-12-05 |
WO2014042716A1 (en) | 2014-03-20 |
US20170315295A1 (en) | 2017-11-02 |
US20190162903A1 (en) | 2019-05-30 |
US10502896B2 (en) | 2019-12-10 |
US11237327B2 (en) | 2022-02-01 |
EP2856499A1 (en) | 2015-04-08 |
CN104412375A (zh) | 2015-03-11 |
TW201405184A (zh) | 2014-02-01 |
US10215921B2 (en) | 2019-02-26 |
TWI503585B (zh) | 2015-10-11 |
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