JP2015201779A - 受信装置 - Google Patents
受信装置 Download PDFInfo
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- JP2015201779A JP2015201779A JP2014079955A JP2014079955A JP2015201779A JP 2015201779 A JP2015201779 A JP 2015201779A JP 2014079955 A JP2014079955 A JP 2014079955A JP 2014079955 A JP2014079955 A JP 2014079955A JP 2015201779 A JP2015201779 A JP 2015201779A
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- voltage
- controlled oscillator
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
【解決手段】受信装置20は、電圧制御発振器22、サンプラ部23、制御電圧生成部24、異常検出部25および制御電圧保持部26を備える。制御電圧保持部26は、制御電圧生成部24から出力される制御電圧Vcの値を保持し、異常検出部25がデジタル信号の異常を検出すると、その異常検出前に保持した制御電圧を電圧制御発振器22に与える。
【選択図】図1
Description
Claims (6)
- 送信装置から送出されて伝送路を介して到達したデジタル信号を受信する受信装置であって、
制御電圧を入力し、前記制御電圧の値に応じた周波数のクロックを出力する電圧制御発振器と、
前記デジタル信号を入力するとともに、前記電圧制御発振器から出力されたクロックを入力し、前記クロックが指示するタイミングにおける前記デジタル信号のデータをサンプリングしホールドして出力するサンプラ部と、
前記デジタル信号または前記データと前記クロックとの間における位相または周波数の差を求め、その差が小さくなるような値を有する前記制御電圧を生成して前記電圧制御発振器へ出力する制御電圧生成部と、
前記デジタル信号の異常を検出する異常検出部と、
前記制御電圧生成部から出力される制御電圧の値を保持し、前記異常検出部が前記デジタル信号の異常を検出すると、その異常検出前に保持した制御電圧を前記電圧制御発振器に与える制御電圧保持部と、
を備えることを特徴とする受信装置。 - 前記異常検出部が前記デジタル信号の異常を検出すると、前記制御電圧生成部から前記電圧制御発振器への制御電圧の印加を禁止する、ことを特徴とする請求項1に記載の受信装置。
- 前記制御電圧保持部は、第1入力端子,第2入力端子および出力端子を有するアンプを含み、前記第1入力端子に制御電圧を保持し、前記第2入力端子と前記出力端子とが互いに接続され、前記出力端子の電圧値を前記電圧制御発振器に与える、ことを特徴とする請求項1に記載の受信装置。
- 前記異常検出部は、前記サンプラ部から出力されたデータのパターンに基づいて前記デジタル信号の異常を検出する、ことを特徴とする請求項1〜3の何れか1項に記載の受信装置。
- 前記異常検出部は、受信した前記デジタル信号の電圧値に基づいて前記デジタル信号の異常を検出する、ことを特徴とする請求項1〜3の何れか1項に記載の受信装置。
- デジタル信号を送出する送信装置と、前記送信装置から送出されて伝送路を介して到達した前記デジタル信号を受信する請求項1〜5の何れか1項に記載の受信装置と、を備えることを特徴とする送受信システム。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014079955A JP6371096B2 (ja) | 2014-04-09 | 2014-04-09 | 受信装置 |
US15/302,068 US10148418B2 (en) | 2014-04-09 | 2015-03-11 | Receiving device |
CN201580016757.2A CN106165299B (zh) | 2014-04-09 | 2015-03-11 | 接收装置 |
PCT/JP2015/057152 WO2015156077A1 (ja) | 2014-04-09 | 2015-03-11 | 受信装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014079955A JP6371096B2 (ja) | 2014-04-09 | 2014-04-09 | 受信装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015201779A true JP2015201779A (ja) | 2015-11-12 |
JP6371096B2 JP6371096B2 (ja) | 2018-08-08 |
Family
ID=54287657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014079955A Active JP6371096B2 (ja) | 2014-04-09 | 2014-04-09 | 受信装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10148418B2 (ja) |
JP (1) | JP6371096B2 (ja) |
CN (1) | CN106165299B (ja) |
WO (1) | WO2015156077A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6703364B2 (ja) * | 2014-04-10 | 2020-06-03 | ザインエレクトロニクス株式会社 | 受信装置 |
JP7317332B2 (ja) * | 2017-10-19 | 2023-07-31 | ザインエレクトロニクス株式会社 | 送信装置および送受信システム |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62256521A (ja) * | 1986-04-29 | 1987-11-09 | Victor Co Of Japan Ltd | 位相比較回路 |
JPS63276921A (ja) * | 1987-02-02 | 1988-11-15 | Matsushita Electric Ind Co Ltd | Pll回路 |
US5648964A (en) * | 1994-09-09 | 1997-07-15 | Kabushiki Kaisha Toshiba | Master-slave multiplex communication system and PLL circuit applied to the system |
JPH10154973A (ja) * | 1996-11-22 | 1998-06-09 | Yokogawa Electric Corp | 通信装置 |
US6775344B1 (en) * | 1999-04-02 | 2004-08-10 | Storage Technology Corporation | Dropout resistant phase-locked loop |
WO2008069555A1 (en) * | 2006-12-05 | 2008-06-12 | Electronics And Telecommunications Research Institute | Apparatus and method for channel estimation and synchronization in ofdm/ofdma relay system |
US20110025913A1 (en) * | 2009-07-28 | 2011-02-03 | Nec Electronics Corporation | Clock data recovery circuit and display device |
JP4754159B2 (ja) * | 2001-02-16 | 2011-08-24 | 富士通株式会社 | データ伝送速度の1/2周波数クロックを用いる光受信機のタイミング抽出回路及び光送受信機のデューティずれ対応回路 |
JP2012205204A (ja) * | 2011-03-28 | 2012-10-22 | Mitsubishi Electric Corp | 通信装置及び通信方法 |
US20130191679A1 (en) * | 2012-01-24 | 2013-07-25 | Qualcomm Incorporated | Dual mode clock/data recovery circuit |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69406477T2 (de) * | 1993-03-01 | 1998-03-19 | Nippon Telegraph & Telephone | Phasenregelkreis mit Abtast- und Halteschaltung |
JP4558028B2 (ja) | 2007-11-06 | 2010-10-06 | ザインエレクトロニクス株式会社 | クロックデータ復元装置 |
JP5314143B2 (ja) | 2009-07-24 | 2013-10-16 | ザインエレクトロニクス株式会社 | クロックデータ復元装置 |
JP2013197836A (ja) * | 2012-03-19 | 2013-09-30 | Seiko Epson Corp | 発振器及び電子機器 |
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2014
- 2014-04-09 JP JP2014079955A patent/JP6371096B2/ja active Active
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2015
- 2015-03-11 US US15/302,068 patent/US10148418B2/en active Active
- 2015-03-11 WO PCT/JP2015/057152 patent/WO2015156077A1/ja active Application Filing
- 2015-03-11 CN CN201580016757.2A patent/CN106165299B/zh active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62256521A (ja) * | 1986-04-29 | 1987-11-09 | Victor Co Of Japan Ltd | 位相比較回路 |
JPS63276921A (ja) * | 1987-02-02 | 1988-11-15 | Matsushita Electric Ind Co Ltd | Pll回路 |
US5648964A (en) * | 1994-09-09 | 1997-07-15 | Kabushiki Kaisha Toshiba | Master-slave multiplex communication system and PLL circuit applied to the system |
JPH10154973A (ja) * | 1996-11-22 | 1998-06-09 | Yokogawa Electric Corp | 通信装置 |
US6775344B1 (en) * | 1999-04-02 | 2004-08-10 | Storage Technology Corporation | Dropout resistant phase-locked loop |
JP4754159B2 (ja) * | 2001-02-16 | 2011-08-24 | 富士通株式会社 | データ伝送速度の1/2周波数クロックを用いる光受信機のタイミング抽出回路及び光送受信機のデューティずれ対応回路 |
WO2008069555A1 (en) * | 2006-12-05 | 2008-06-12 | Electronics And Telecommunications Research Institute | Apparatus and method for channel estimation and synchronization in ofdm/ofdma relay system |
US20110025913A1 (en) * | 2009-07-28 | 2011-02-03 | Nec Electronics Corporation | Clock data recovery circuit and display device |
JP2012205204A (ja) * | 2011-03-28 | 2012-10-22 | Mitsubishi Electric Corp | 通信装置及び通信方法 |
US20130191679A1 (en) * | 2012-01-24 | 2013-07-25 | Qualcomm Incorporated | Dual mode clock/data recovery circuit |
Also Published As
Publication number | Publication date |
---|---|
US20170118010A1 (en) | 2017-04-27 |
JP6371096B2 (ja) | 2018-08-08 |
WO2015156077A1 (ja) | 2015-10-15 |
CN106165299A (zh) | 2016-11-23 |
CN106165299B (zh) | 2020-03-24 |
US10148418B2 (en) | 2018-12-04 |
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