JP2015198219A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP2015198219A JP2015198219A JP2014076974A JP2014076974A JP2015198219A JP 2015198219 A JP2015198219 A JP 2015198219A JP 2014076974 A JP2014076974 A JP 2014076974A JP 2014076974 A JP2014076974 A JP 2014076974A JP 2015198219 A JP2015198219 A JP 2015198219A
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Abstract
【解決手段】ステップF2では、SOI基板に分離領域と素子形成領域が形成される。ステップF3では、SOI領域とバルク領域とが形成される。このとき、SOI領域とバルク領域との段差の側壁には、全周にわたって分離領域の分離絶縁膜が露出する。ステップF4では、ゲート電極が形成される。ステップF5では、バルク用トランジスタのエクステンション注入が行われる。このとき、エクステンション注入の不純物がSOI領域へ注入されるのを阻止する処理が行われる。ステップF6では、SOI領域にせり上げエピタキシャル層が形成される。
【選択図】図1
Description
他の実施の形態によれば、エピタキシャル層の異常成長を抑制することができる。
ここでは、SOI領域とバルク領域との段差の側壁に、全周にわたって分離領域の分離絶縁膜を露出させ、そして、バルク領域へのエクステンション注入の際にSOI領域を覆うようにレジストパターンを形成する手法について説明する。
ここでは、SOI領域とバルク領域との段差の側壁に、全周にわたって分離領域の分離絶縁膜を露出させ、そして、SOI領域に配置されるダミー素子形成領域の全体をダミー電極によって覆う手法について説明する。なお、実施の形態1と同一部材については同一符号を付し、必要である場合を除きその説明を繰り返さないこととする。
ここでは、SOI領域とバルク領域との段差の側壁に、全周にわたって分離領域の分離絶縁膜を露出させ、そして、SOI領域に配置されるダミー素子形成領域をダミーゲート電極と側壁保護膜とによって覆う手法について説明する。なお、実施の形態1と同一部材については同一符号を付し、必要である場合を除きその説明を繰り返さないこととする。
第1例
第1例では、SOI領域とバルク領域との境界にダミー素子形成領域およびダミーゲート電極を配置させないように、素子形成領域およびゲート電極等のパターン(マスクパターン)を作成する手法について説明する。
まず、ダミー素子形成領域のパターンの処理について説明する。図80に、SOI領域のパターンSOIPを示し、図81に、ダミー素子形成領域のパターンODDUMを示す。図81に示すように、SOI領域のパターンSOIPの境界を跨ぐように位置するダミー素子形成領域のパターンODDUMが境界に沿って存在する。
ODDUM not SOIP
によって表される。
ODDUM and SOIP
によって表される。
(ODDUM not SOIP) or (ODDUM and SOIP)
によって表される。
次に、ダミーゲート電極のパターンの処理について説明する。図85に、ダミーゲート電極のパターンPODUMを示す。図85に示すように、SOI領域のパターンSOIPの境界を跨ぐように位置するダミーゲート電極のパターンPODUMが存在する。
PODUM not SOIP
によって表される。
PODUM and SOIP
によって表される。
(PODUM not SOIP) or (PODUM and SOIP)
によって表される。
((ODDUM or PODUM) not SOIP) or ((ODDUM or PODUM) and SOIP)
によって表される。
第2例では、バルク領域へのエクステンション注入の際にSOI領域へ不純物が注入されないように、不純物の注入を阻止するフォトレジストのパターンを作成する手法について説明する。
IMPLADUM not SOIP
によって表される。
Claims (12)
- 半導体基板の表面上に絶縁層を介在させて半導体層が形成された基板部を用意する工程と、
前記基板部に分離領域を形成する工程と、
前記基板部に対して互いに隣接する第1領域および第2領域を規定し、前記第1領域に位置する前記半導体層および前記絶縁層を残すとともに、前記第2領域に位置する前記半導体層および前記絶縁層を除去して前記半導体基板と前記分離領域を露出することにより、前記第1領域には、第1素子形成領域および第1ダミー素子形成領域を形成し、前記第2領域には、第2素子形成領域および第2ダミー素子形成領域を形成する工程と、
前記第1領域に第1ゲート電極および第1ダミーゲート電極を形成し、前記第2領域に第2ゲート電極および第2ダミーゲート電極を形成する工程と、
前記第1素子形成領域および前記第1ダミー素子形成領域を被覆する被覆部を形成する工程と、
前記被覆部が形成された後、少なくとも前記被覆部をマスクとして、前記第2領域における前記第2素子形成領域に一導電型の不純物を導入する工程と、
前記第1素子形成領域に、エピタキシャル成長法によってせり上げエピタキシャル層を形成する工程と
を備え、
前記分離領域を形成する工程では、前記第2領域に位置する前記半導体層および前記絶縁層を除去することにより、前記第1領域と前記第2領域との境界に形成される段差の全体にわたり、前記分離領域が露出するように形成される、半導体装置の製造方法。 - 前記被覆部を形成する工程では、前記被覆部として、前記第1素子形成領域および前記第1ダミー素子形成領域を含む前記第1領域の全体を覆うようにフォトレジストが形成される、請求項1記載の半導体装置の製造方法。
- 前記被覆部を形成する工程では、前記被覆部として、前記第1ダミー素子形成領域の全体を覆う前記第1ダミーゲート電極と、前記第1素子形成領域の全体を覆うフォトレジストとが形成され、
前記せり上げエピタキシャル層を形成する工程では、前記第1ダミー素子形成領域の全体が前記第1ダミーゲート電極によって覆われた状態で、前記せり上げエピタキシャル層が形成される、請求項1記載の半導体装置の製造方法。 - 前記せり上げエピタキシャル層を形成する工程の前に、前記第1ゲート電極および前記第1ダミーゲート電極のそれぞれの側壁に側壁保護膜を形成する工程を有し、
前記被覆部を形成する工程では、前記被覆部として、前記第1ダミー素子形成領域を覆う前記第1ダミーゲート電極と、前記第1素子形成領域の全体を覆うフォトレジストとが形成され、
前記せり上げエピタキシャル層を形成する工程では、前記第1ダミー素子形成領域の全体が前記第1ダミーゲート電極および前記側壁保護膜によって覆われた状態で、前記せり上げエピタキシャル層が形成される、請求項1記載の半導体装置の製造方法。 - 前記分離領域を形成する工程は、
素子形成領域としてあらかじめ登録されているパターンを第1パターンとして設定するステップと、
前記第1領域に対応するパターンとして第2パターンを設定するステップと、
前記第1パターンのうち、前記第2パターンの領域内に位置する前記第1パターンの部分を第3パターンとして設定するステップと、
前記第1パターンから、前記第3パターンと、前記第2パターンの境界に位置する前記第1パターンの部分とを除いたパターンを第4パターンとして設定するステップと、
前記第3パターンと前記第4パターンとを合わせたパターンを第5パターンとして設定するステップと
を含み、
前記第5パターンに基づいて前記分離領域が形成される、請求項1〜4のいずれかに記載の半導体装置の製造方法。 - 前記第1ゲート電極、前記第1ダミーゲート電極、前記第2ゲート電極および前記第2ダミーゲート電極を形成する工程は、
前記第1領域に対応するパターンとして第2パターンを設定するステップと、
ゲート電極としてあらかじめ登録されているパターンを第6パターンとして設定するステップと、
前記第6パターンのうち、前記第2領域の領域内に位置する前記第6パターンの部分を第7パターンとして設定するステップと、
前記第6パターンから、前記第7パターンと、前記第2パターンの境界に位置する前記第6パターンの部分とを除いたパターンを第8パターンとして設定するステップと、
前記第7パターンおよび前記第8パターンとを合わせたパターンを第9パターンとして設定するステップと
を含み、
前記第9パターンに基づいて、前記第1ゲート電極、前記第1ダミーゲート電極、前記第2ゲート電極および前記第2ダミーゲート電極が形成される、請求項1〜4のいずれかに記載の半導体装置の製造方法。 - 前記被覆部を形成する工程は、
不純物を導入する領域としてあらかじめ登録されているパターンを第10パターンとして設定するステップと、
前記第1領域に対応するパターンを第2パターンとして設定するステップと、
前記第10パターンから前記第2パターンを除いたパターンを第11パターンとして設定するステップと
を含み、
前記第11パターンに基づいて、前記第1領域を覆う前記フォトレジストが形成される、請求項2記載の半導体装置の製造方法。 - 半導体基板および前記半導体基板の上に絶縁層を介在させて形成された半導体層を含む基板部と、
前記基板部に形成された分離領域と、
互いに隣接するように前記基板部に形成された第1領域および第2領域と、
前記分離領域によって前記第1領域に規定された第1素子形成領域および第1ダミー素子形成領域と、
前記分離領域によって前記第2領域に規定された第2素子形成領域および第2ダミー素子形成領域と、
前記第1領域および前記第2領域に形成されたゲート電極を含み、
前記第1素子形成領域に形成されたせり上げエピタキシャル層と、
を備え、
前記第1領域では、前記第1素子形成領域および前記第1ダミー素子形成領域は前記半導体層に形成され、
前記第2領域では、前記第2素子形成領域および前記第2ダミー素子形成領域は前記半導体基板に形成され、
前記第1領域と前記第2領域との境界には、前記絶縁層および前記半導体層の厚さに相当する段差が形成され、
前記分離領域は、前記段差の全周にわたり前記第1領域を囲むように位置する、半導体装置。 - 前記第2素子形成領域に一導電型の不純物が導入され、前記不純物は窒素(N)を含む、請求項8記載の半導体装置。
- 前記ゲート電極は、前記第1領域と前記第2領域との前記境界を跨がないように配置された、請求項8または9に記載の半導体装置。
- 前記ゲート電極は、
前記第1素子形成領域に形成された第1ゲート電極と、
前記第1ダミー素子形成領域に形成された第1ダミーゲート電極と
を含み、
前記第1ダミー素子形成領域の全体が、前記第1ダミーゲート電極によって覆われた、請求項8〜10のいずれかに記載の半導体装置。 - 前記ゲート電極は、
前記第1素子形成領域に形成された第1ゲート電極と、
前記第1ダミー素子形成領域に形成された第1ダミーゲート電極と
を含み、
前記第1ゲート電極および前記第1ダミーゲート電極のそれぞれの側壁には側壁絶縁膜が形成され、
前記第1ダミー素子形成領域の全体が、前記第1ダミーゲート電極および前記側壁絶縁膜によって覆われた、請求項8〜10のいずれかに記載の半導体装置。
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KR20210086931A (ko) * | 2019-12-31 | 2021-07-09 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 집적 회로에 대한 경계 스킴 및 집적 회로를 형성하기 위한 방법 |
US11069714B1 (en) | 2019-12-31 | 2021-07-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Boundary scheme for semiconductor integrated circuit and method for forming an integrated circuit |
KR102349066B1 (ko) * | 2019-12-31 | 2022-01-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 집적 회로에 대한 경계 스킴 및 집적 회로를 형성하기 위한 방법 |
US20220352178A1 (en) * | 2021-04-30 | 2022-11-03 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US11903187B2 (en) * | 2021-04-30 | 2024-02-13 | Samsung Electronics Co., Ltd. | Semiconductor devices |
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US20150287746A1 (en) | 2015-10-08 |
JP6262060B2 (ja) | 2018-01-17 |
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