JP2015115353A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS with a highly integrated SOI structure composed of vertical MISFETs.SOLUTION: A CMOS with an SOI structure composed of layered structure vertical (vertical direction operation) N-channel and P-channel MISFETs comprises: semiconductor layers (5, 6) with protrusion structures, which are provided on a semiconductor substrate 1 via an insulation film 2; ptype source-drain regions (7. 8) which are provided on and under the semiconductor layers (5, 6) in an opposed manner; a barrier metal layer 12 provided in contact with an upper part of the semiconductor layer 6; semiconductor layers (14, 15) with protrusion structures, which are provided on the barrier metal layer 12; and n type and ntype source-drain regions (16-19) provided on and under the semiconductor layers (14, 15) in an opposed manner, in which the ptype drain region 8 and the ntype drain region are connected by the barrier metal layer 12 and simplified surrounding gates on insulation 10 are provided on lateral faces of the semiconductor layers (6, 15) via gate insulation films (9, 20).

Description

  The present invention relates to a semiconductor integrated circuit having an SOI (Silicon On Insulator) structure. In particular, a low-cost SOI substrate made of single crystal silicon is formed on a semiconductor substrate (bulk wafer) by an easy manufacturing process. In particular, the present invention relates to forming a CMOS type semiconductor integrated circuit including short channel N-channel and P-channel MIS field effect transistors with high integration, high speed, low power, high performance and high reliability.

FIG. 36 is a schematic cross-sectional side view of a conventional semiconductor device, showing a part of a CMOS type semiconductor integrated circuit including N-channel and P-channel MIS field effect transistors having an SOI structure formed using a bonded SOI wafer. , 71 is a p-type silicon (Si) substrate, 72 is a bonding oxide film, 73 is an element isolation region forming trench and a buried oxide film, 74 is a p-type semiconductor layer (SOI substrate), and 75 is an n-type semiconductor film. Semiconductor layer (SOI substrate), 76 is an n ⁺ type source region, 77 is an n type source region, 78 is an n type drain region, 79 is an n ⁺ type drain region, 80 is a p ⁺ type source region, and 81 is a p ⁺ type Drain region, 82 is gate insulating film, 83 is gate electrode, 84 is side wall, 85 is PSG film, 86 is insulating film, 87 is barrier metal, 88 is conductive plug, 89 is interlayer insulation , 90 barrier metal, 91 Cu wiring 92 denotes the barrier insulating film.
In the figure, a thin p-type semiconductor layer (insulated in an island shape by an element isolation region forming trench and a buried oxide film 73, which is bonded onto a p-type silicon substrate 71 via an oxide film 72 ( SOI substrate 74 and n-type semiconductor layer (SOI substrate) 75 are formed. The p-type SOI substrate 74 has n-type source / drain regions (77, 78) self-aligned with the gate electrode 83, sidewalls. An n-channel LDD (Lightly Doped Drain) structure MIS field effect transistor composed of n ⁺ -type source / drain regions (76, 79) self-aligned to 84 is formed, and a gate electrode 83 is formed on the n-type SOI substrate 75. P ⁺ -type source / drain region self-aligned on sidewall 84 self-aligned A P-channel MIS field effect transistor made of (80, 81) is formed. Further, the n ⁺ type source / drain regions (76, 79) and the p ⁺ type source / drain regions (80, 81) are connected to the Cu wiring 91 having the barrier metal 90 via the conductive plug 88 having the barrier metal 87. A desired voltage is applied.
Therefore, the junction capacitance can be reduced by forming the source / drain region surrounded by the insulating film, the depletion layer capacitance can be reduced by completely depleting the SOI substrate, the breakdown voltage of the source / drain region can be improved, and the subthreshold characteristics can be improved. Compared with a CMOS comprising a MIS field effect transistor formed on a normal bulk wafer by reducing the threshold voltage or the like, higher speed, lower power, and higher integration are possible.
However, since the ground voltage is applied to the conductor (p-type silicon substrate) under the SOI substrate, the back channel of the N-channel MIS field effect transistor formed on the p-type SOI substrate is maintained in the off state. Since the back channel of the P-channel MIS field effect transistor formed on the type SOI substrate is always turned on, in the N-channel MIS field effect transistor, even if the voltage applied to the gate electrode is the ground voltage or the power supply voltage However, although the P-channel MIS field effect transistor operates normally, current flows through the front channel and the back channel at the ground voltage, and the front channel is off (no current flows) at the power supply voltage. There is a drawback that the channel has a small current leak and it is inevitable that it malfunctions. It was.
Further, when forming a CMOS, since N-channel and P-channel MIS field effect transistors had to be formed side by side on a silicon substrate bonded on an oxide film, high integration was not achieved.
When a CMOS integrated circuit is formed, the gate electrodes of a pair of N-channel and P-channel MIS field effect transistors are generally connected to the same voltage, and are inherent to the N-channel and P-channel MIS field effect transistors. Therefore, it was difficult to achieve high integration because each gate electrode had to be connected by a wiring body.
In order to create such an SOI structure, a so-called bonded SOI wafer in which a semiconductor substrate having a uniform single crystal is bonded to another semiconductor substrate through an oxide film must be purchased. Even if it relies on low-cost technology, there was a drawback that it was extremely expensive, about 2 to 3 times the bulk wafer in the mass production stage.
As another means for creating an SOI structure, a bulk wafer is used, an oxygen ion is implanted, and a silicon oxide film is formed inside the bulk wafer by high-temperature heat treatment. Even with forming, the costly problem of having to purchase a very expensive high-dose ion implantation machine and requiring a long manufacturing process to implant high doses of oxygen, silicon Disadvantages such as difficult control of oxide film thickness, formation of fully depleted SOI substrate, or instability of characteristics related to damage repair of crystal defects due to oxygen ion implantation in use of large-diameter wafers of 10 to 12 inches was there.
In addition, even if a bonded SOI substrate or a SOI substrate based on the SIMOX method is used, high-temperature heat treatment is necessary, and it is impossible to make an SOI substrate made of single crystal silicon multi-layered. A three-dimensional semiconductor integrated circuit could not be formed.
Attempts to recrystallize a polycrystalline silicon layer grown by chemical vapor deposition by laser annealing and convert it into a single crystal silicon layer have been tried before. A crystalline silicon layer could not be obtained, and the leakage current was so large that it could not be put into practical use, and no realization possibility was found for a multilayer SOI substrate.

JP2009-260099 JP2012-142492

The problem to be solved by the present invention is that, as shown in the prior art, even if an SOI substrate is formed by the SIMOX method or a bonded SOI wafer is used to form an SOI structure,
(1) The cost is considerably high, it can be used only for special purpose products with high added value, and the technology applicable to inexpensive general-purpose products is lacking.
(2) Since it is difficult to control the thinning of the SOI substrate in a large-diameter wafer, it is difficult to form a fully depleted SOI substrate, and it is difficult to obtain stability of characteristics of a large number of built-in MIS field effect transistors. .
(3) When forming a CMOS, the back channel leakage of any one of the MIS field effect transistors could not be prevented.
(4) When forming a CMOS, both N-channel and P-channel MIS field-effect transistors must be formed with an occupied area on the surface, which hinders high integration.
(5) When forming a CMOS, gate electrode connection wirings are formed on the individual gate electrodes of a pair of N-channel and P-channel MIS field effect transistors, and the elements are miniaturized to connect them. However, it was difficult to miniaturize the wiring and it was difficult to achieve high integration.
(6) When an SOI substrate is formed by bonding or SIMOX, high-temperature treatment is required. Therefore, it is impossible to form a multilayer SOI substrate and to form a MIS field effect transistor on each SOI substrate. 3D SOI could not be realized.
Such problems are becoming more prominent, and it is difficult to achieve higher integration, higher speed, higher performance, and higher reliability simply by forming a MIS field effect transistor having a fine SOI structure with the current technology. That is.

The above-described problems include a semiconductor substrate, an insulating film provided on the semiconductor substrate, a first barrier metal layer selectively provided on the insulating film, and the first barrier metal layer on the first barrier metal layer. A first-conductivity-type first semiconductor layer having a flat-plate structure provided in the same size as the first barrier metal layer, and a one-conductivity-type columnar structure provided selectively on the first semiconductor layer A second semiconductor layer; a second barrier metal layer selectively provided on and in contact with the second semiconductor layer; on the second semiconductor layer; and on the second barrier metal layer In addition, a third semiconductor layer having a conductivity type opposite to that of the flat plate structure provided in the same size as the second barrier metal layer and a columnar structure selectively provided on the third semiconductor layer are opposite to each other. A conductive type fourth semiconductor layer, and the entire first semiconductor layer and a lower portion of the second semiconductor layer; An opposite conductivity type source region, an opposite conductivity type drain region provided above the second semiconductor layer relative to the opposite conductivity type source region, the entire third semiconductor layer, and A drain region of one conductivity type provided below the fourth semiconductor layer, and a source region of one conductivity type provided above the fourth semiconductor layer relative to the drain region of one conductivity type; A gate electrode (integrated surrounding gate electrode) provided in a structure that is integrated and surrounded by at least the side surfaces of the second and fourth semiconductor layers via a gate insulating film, and has an opposite conductivity type Complementary drains of one-type and opposite-conductivity type MIS field-effect transistors having a stacked structure, in which a drain region of one conductivity type and a drain region of one conductivity type are connected by the second barrier metal layer. Type M It is solved by a semiconductor device of the present invention constituting the S field effect transistor.
Here, the integrated surrounding gate electrode is formed in a structure in which the side surface of the columnar structure semiconductor layer is surrounded by a gate insulating film in an N-channel MIS field-effect transistor and a P-channel MIS field-effect transistor stacked one above the other. The enclosed gate electrode of the N channel MIS field effect transistor and the enclosed gate electrode of the P channel MIS field effect transistor are integrated as a single enclosed gate electrode.
The barrier metal layer of the present invention is
[1] An auxiliary film for growing a single crystal semiconductor layer by preventing partial amorphization due to the influence of a base insulating film when growing an epitaxial semiconductor layer [2] Impurity of opposite conductivity type formed in each semiconductor layer Separation film [3] for preventing mutual impurity diffusion between the region and the one-conductivity type impurity region [1] to [1] to the conductive film connecting the opposite-conductivity type impurity region and the one-conductivity type impurity region respectively formed in the semiconductor layer 3], or a conductive film (single metal, metal compound, etc.) that plays all the roles.

As described above, according to the present invention, the first barrier metal layer (underlying insulation) is formed on the insulating film by using an ordinary inexpensive semiconductor substrate and utilizing the epitaxial growth technique (the manufacturing method will be described in detail separately). A film barrier layer), a first lateral (horizontal) semiconductor layer is grown directly on the first barrier metal layer, and a first vertical (vertical) is selectively formed on the first lateral (horizontal) semiconductor layer. ) Direction semiconductor layer is grown to form a lower SOI substrate having a convex structure, and a drain region of one conductivity type is provided on the upper portion of the first vertical (vertical) direction semiconductor layer, and one conductive layer is provided on the lower side while being spaced apart from each other. A source region of a type is provided, and a source region of one conductivity type is also provided in the entire first lateral (horizontal) direction semiconductor layer, and a part of the source region is further formed on the first longitudinal (vertical) direction semiconductor layer. In contact with the second barrier metal layer (underlying insulating film barrier layer and conductive layer for connecting a different conductivity type drain region) And a second lateral (horizontal) direction semiconductor layer is grown directly on the second barrier metal layer, and a second longitudinal (vertical) is selectively formed on the second lateral (horizontal) direction semiconductor layer. ) Direction semiconductor layer is grown to form an upper SOI substrate, and a source region of opposite conductivity type is provided above the second vertical (vertical) direction semiconductor layer, and spaced apart and oppositely, a drain region of opposite conductivity type at the bottom. And extending the second lateral (horizontal) direction semiconductor layer by providing a drain region of the opposite conductivity type, and a first longitudinal (vertical) direction semiconductor layer and a second longitudinal (vertical) direction semiconductor layer. An SOI structure CMOS composed of vertical (vertical operation) N-channel and P-channel MIS field effect transistors, each of which is provided with a surrounding gate electrode integrated via a gate insulating film on each side surface Since it can be configured, the junction capacitance of the source drain region Reduction (substantially zero), reduction of depletion layer capacitance, improvement of the breakdown voltage of the source / drain region, and reduction of threshold voltage due to improvement of subthreshold characteristics, reduction of power consumption, and the like are possible.
In addition, a barrier metal layer (underlying insulating film barrier layer) is provided on the upper surface of the insulating film so that the epitaxially growing semiconductor layer does not come into contact with the underlying insulating film during the growth of the semiconductor layer by epitaxial growth, thereby forming the epitaxially grown semiconductor layer. In addition, it is possible to form an SOI substrate including a fully depleted single crystal semiconductor layer in which partial amorphization due to the influence of the base insulating film is prevented.
Moreover, since the channel region can be formed by surrounding the gate electrode provided through the gate oxide film, the current path other than the channel can be cut off, and not only the complete channel control by the surrounding gate electrode is possible. Since a channel can be formed on all side surfaces, the channel width can be increased without increasing the occupied area of the surface (upper surface), and thus the drive current can be increased.
Also, through an easy manufacturing process (details will be described later), the enclosed gate electrode of the P-channel MIS field effect transistor and the enclosed gate electrode of the N-channel MIS field effect transistor are integrated as a single enclosed gate electrode (shared) By being formed in this manner, it is possible to achieve high integration by eliminating the wiring body.
Further, it is possible to achieve high integration by forming a stacked structure CMOS with almost one MIS field effect transistor occupied area without increasing the occupied area on the surface.
In addition, a second lateral (horizontal) direction semiconductor in which one conductive type (or opposite conductive type) drain region is formed without separately providing a wiring body to the one conductive type drain region and a wiring body to the opposite conductive type drain region. One conductivity type drain region and the opposite conductivity type drain region can be directly connected by the second barrier metal layer (underlying insulating film barrier layer and conductive film for connecting different conductivity type drain region) provided immediately below the layer. High integration can be achieved by eliminating the wiring body.
Further, the channel length for determining various characteristics of the MIS field effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer having good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. In addition, a MIS field effect transistor having stable characteristics can be obtained even in a large-diameter wafer.
Further, since a complete SOI structure CMOS circuit (inverter or the like) can be formed, it is possible to completely prevent malfunction due to high voltage noise generated in a semiconductor substrate due to static electricity or the like or latch-up characteristics peculiar to CMOS.
Also, a buried part that forms a part of the element isolation region by self-aligning the longitudinal (vertical) direction epitaxial semiconductor layer (see the manufacturing method) necessary for forming the first and second lateral (horizontal) direction semiconductor layers. High reliability and high integration can be achieved by being able to convert to an insulating film.
In addition, the first and second vertical (vertical) direction semiconductor layers (columnar structure semiconductor layers) having extremely good crystallinity are self-aligned to form components of the MIS field effect transistor (low concentration and high concentration). It is also possible to finely form a source / drain region, a gate oxide film, and an integrated surrounding gate electrode.
It is also possible to provide a wiring body under the barrier metal layer immediately below the first lateral (horizontal) semiconductor layer in which the one-conductivity type source region is provided. Since the wiring body can be omitted, the first lateral (horizontal) direction semiconductor layer can be finely formed.
Also, the direct connection between the one conductivity type drain region and the opposite conductivity type drain region by the second barrier metal layer (the conductive film for connecting the base insulating film barrier layer and the different conductivity type drain region) is stopped, and the connection to the one conductivity type drain region is stopped. In the integrated circuit including a 2-input NAND circuit or a 2-input NOR circuit, it is possible to separately provide a wiring body for the drain region opposite to the wiring body. In this case, both drain regions can be freely wired. A highly integrated circuit that is easy to use can be formed.
It is also possible to form a lower vertical (vertical operation) MIS field effect transistor in a semiconductor substrate and a vertical (vertical) direction semiconductor layer grown on the semiconductor substrate. In this case, between the semiconductor substrate and the source region, Although the junction capacity increases, the manufacturing method can be simplified.
In other words, high-speed, high-reliability, high-performance, and high-speed, capable of manufacturing large-scale semiconductor integrated circuits that can be used for high-speed, large-capacity communication devices, personal digital assistants, in-vehicle devices, various electronic mechanical devices, and space-related devices A CMOS semiconductor device having an extremely low power SOI structure having integration can be obtained.
The present inventors have in this technology (heterogeneous conductive region) on the insulating film connecting type barrier laminate vertical with metal layer and integrated surrounding gate electrode (vertical operation) CMOS (A ccumulated Ve rtical C MOS with C onnecting named Ba rrier M etal and S implified Su rrounding G ate on Insulator) structure, abbreviated as AVECCBAMSSUG (Eibe' click Bam sag).

Schematic side cross-sectional view of the first embodiment of the semiconductor device of the present invention (direction showing the connecting portion to the integrally enclosed gate electrode) Schematic side cross-sectional view of the first embodiment of the semiconductor device of the present invention (direction showing a connecting portion to a different conductivity type drain region) Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Schematic side cross-sectional view of the second embodiment of the semiconductor device of the present invention (direction showing the connecting portion to the integrally enclosed gate electrode) Schematic side cross-sectional view of a third embodiment of the semiconductor device of the present invention (direction showing a connecting portion to an integral enclosed gate electrode) Schematic side cross-sectional view of the third embodiment of the semiconductor device of the present invention (direction showing the connecting portion to the individual drain region) Schematic side cross-sectional view of a fourth embodiment of the semiconductor device of the present invention (direction showing a connecting portion to an integral enclosed gate electrode) Schematic side sectional view of a fourth embodiment in a semiconductor device of the present invention (direction showing a connection portion to a different conductivity type drain region) Schematic side sectional view of a conventional semiconductor device

In particular, the present invention
(1) Formation of a longitudinal (vertical) direction or lateral (horizontal) direction epitaxial Si layer with a Si substrate made of a complete single crystal as a nucleus.
(2) Growth of a complete single crystal Si layer by epitaxial growth using a barrier metal layer.
(3) Formation of upper and lower surrounding gate electrodes self-aligned with the Si layer having a columnar structure and integration by an easy process.
(4) Formation of n-type and n ⁺ -type source / drain regions or p ⁺ -type source / drain regions in a columnar Si layer and a flat Si layer self-aligned with the columnar Si layer.
(5) Direct connection of the p ⁺ type drain region formed in the columnar Si layer and the n ⁺ type drain region formed in the flat plate Si layer by the barrier metal layer.
(6) Lowering the temperature of the epitaxially grown Si layer after ion implantation of impurities for forming the source / drain regions.
(7) Simultaneous activation and depth control of the n-type and n ⁺ -type source / drain regions and the p ⁺ -type source / drain region by the RTP (Rapid Thermal Processing) method.
Using technology such as
A first barrier metal layer is provided on an Si substrate via an insulating film, and a first lateral (horizontal) epitaxial Si layer (first semiconductor layer) and a first barrier layer are formed on the first barrier metal layer. An n-type SOI substrate composed of a longitudinal (vertical) direction epitaxial Si layer (second semiconductor layer) is provided, and the entire first lateral (horizontal) direction epitaxial Si layer and the first longitudinal (vertical) direction epitaxial Si layer are provided. A p ⁺ -type source region is provided in the lower portion, and a p ⁺ -type drain region is provided in the upper portion of the first vertical (vertical) epitaxial Si layer, and the upper surface of the first vertical (vertical) epitaxial Si layer. A second barrier metal layer is provided in contact with the second barrier metal layer, and a second lateral (horizontal) epitaxial Si layer (third semiconductor layer) and a second longitudinal (vertical) epitaxial are formed on the second barrier metal layer. Si layer (4th Semiconductor layer) p-type SOI substrate is provided comprising a second lateral (horizontal) direction epitaxial Si layer as a whole and a second longitudinal (vertical) direction the epitaxial Si layer n-type lower and n ⁺ -type drain region is provided In contrast, n-type and n ⁺ -type source regions are provided above the second vertical (vertical) epitaxial Si layer, and gates are provided on the side surfaces of the first and second vertical (Si) vertical epitaxial Si layers. This is an SOI-structured CMOS comprising vertical (vertical operation) N-channel and P-channel MIS field effect transistors, in which an integral surrounding gate electrode is provided via an insulating film.

Hereinafter, the present invention will be specifically described with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side sectional view are shown only on the main insulating film, and the wiring is drawn with a slight back-and-forth displacement, and the horizontal and vertical sizes are accurate to show the main part of the invention. The dimensions are not shown.
1 to 30 show a first embodiment of a semiconductor device according to the present invention. FIG. 1 is a schematic side sectional view in a direction showing a connecting portion to an integrated surrounding gate electrode, and FIG. 2 shows a drain region of a different conductivity type. FIG. 3 to FIG. 30 are process cross-sectional views of the manufacturing method.

1 and 2 show a part of a CMOS type semiconductor integrated circuit using a silicon (Si) substrate and formed of vertical (vertical operation) N-channel and P-channel MIS field effect transistors formed in an AVECCBAMSSUG structure. 1 is a p-type silicon (Si) substrate of about 10 ¹⁵ cm ⁻³ , 2 is a silicon oxide film (SiO ₂ ) of about 150 nm, and 3 is a first barrier metal layer (underlying insulating film barrier layer of about 30 nm) , TiN), 4 is a silicon nitride film (Si ₃ N ₄ ) in an element isolation region of about 80 nm, and 5 is an n-type Si layer of about 10 ¹⁷ cm ⁻³ (first lateral (horizontal) epitaxial semiconductor layer) , 6 is an n-type Si layer (first vertical (vertical) epitaxial semiconductor layer) of about 10 ¹⁷ cm ⁻³ , and 7 is a p ⁺ type source region of about 10 ²⁰ cm ^−3. , 8 is a p ⁺ type drain region of about 10 ²⁰ cm ⁻³ , 9 is a gate oxide film (SiO ₂ ) of about 5 nm, 10 is an integrated surrounding gate electrode (WSi), and 11 is a phosphosilicate glass (about 150 nm) ( PSG) film, 12 is a second barrier metal layer of about 50 nm (underlying insulating film barrier layer and conductive film for connecting different types of drain regions, TiN), and 13 is a silicon nitride film (SiN) of an element isolation region of about 100 nm. ₃ N ₄ ), 14 is a p-type Si layer of about 10 ¹⁷ cm ⁻³ (second lateral (horizontal) epitaxial semiconductor layer), and 15 is a p-type Si layer of about 10 ¹⁷ cm ⁻³ (second longitudinal (vertical) direction epitaxial semiconductor layer) of, 16 ¹⁰ 20 ^{cm -3} of about ^{n +} -type drain region 17 is about 5 × ¹⁰ 17 ^{cm -3} of n-type drain region 18 is 5 × ¹⁰ 17 cm ³ about the n-type source region, the ¹⁰ 20 ^{cm -3} of about ^{n +} -type source regions 19, 20 are 5nm approximately the gate oxide film _(SiO 2), 21 is 300nm approximately phosphosilicate glass (PSG) film, 22 Is a silicon nitride film (Si ₃ N ₄ ) of about 20 nm, 23 is a barrier metal (TiN) of about 10 nm, 24 is a conductive plug (W), 25 is an insulating film (SiOC) of about 500 nm, and 26 is a barrier of about 10 nm. Metal (TaN), 27 is a Cu wiring (including a Cu seed layer) of about 500 nm, and 28 is a barrier insulating film (Si ₃ N ₄ ) of about 20 nm.

In FIG. 1 (the direction indicated connections to integrated surround gate electrode), a silicon oxide film (SiO 2) ₂ is provided on the silicon substrate 1 of p-type, on the silicon oxide film (SiO 2) ₂ Is selectively provided with a first barrier metal layer (underlying insulating film barrier layer, TiN) 3, and an n-type Si layer immediately above the first barrier metal layer (underlying insulating film barrier layer, TiN) 3. 5 (first lateral (horizontal) direction epitaxial semiconductor layer) is provided, and an n-type Si layer 6 (first longitudinal (vertical) direction epitaxial semiconductor layer) is selectively provided on the Si layer 5. In addition, an n-type SOI substrate composed of the Si layer 5 and the Si layer 6 is provided so as to be insulated and isolated in an island shape by a silicon nitride film (Si ₃ N ₄ ) 4. The side surface of the Si layer 6 is surrounded by gate electrodes (WSi, integrally surrounded gate electrodes) 10 having different film thicknesses via a gate oxide film (SiO ₂ ) 9. On top of the Si layer 6, ^{p +} -type drain region 8 is provided, in the lower portion of the Si layer 6, ^{p +} -type source region 7 is provided relative to the ^{p +} -type drain region 8, ^{p +} -type source A vertical (vertical operation) P-channel MIS field effect transistor having a structure in which the region 7 extends and is also provided in the entire Si layer 5 is formed. A second barrier metal layer (underlying insulating film barrier layer / conductive film for connecting different conductivity type drain regions, TiN) 12 is selectively provided on the Si layer 6 so as to partially contact the Si layer 6. The p-type Si layer 14 (second lateral (horizontal) direction epitaxial semiconductor layer) is directly above the second barrier metal layer (underlying insulating film barrier layer and conductive film for connecting different conductivity type drain region, TiN) 12. ) And a p-type Si layer 15 (second longitudinal (vertical) epitaxial semiconductor layer) is selectively provided on the Si layer 14, and a p-type layer composed of the Si layer 14 and the Si layer 15 is provided. An SOI substrate is provided by being insulated and isolated in an island shape by a silicon nitride film (Si ₃ N ₄ ) 13. The side surface of the Si layer 15 is surrounded by a gate electrode (WSi, integrally surrounded gate electrode) 10 having a different film thickness via a gate oxide film (SiO ₂ ) 20, and is part of the upper gate electrode 10. An integral surrounding gate electrode 10 is formed by being directly connected to the lower gate electrode 10. On top of the Si layer 15, n-type and ^{n +} -type source region (18, 19) are mounted on the lower portion of the Si layer 15, relative to n-type and the ^{n +} -type source region (18, 19) N-type and n ⁺ -type drain regions (16, 17) are provided, and the n ⁺ -type drain region 16 extends and is provided in the entire Si layer 14 as well. A channel MIS field effect transistor is formed. Here, the p ⁺ -type drain region and the n ⁺ -type drain region are directly connected by a second barrier metal layer (underlying insulating film barrier layer / conductive film for connecting different conductivity type drain regions, TiN) 12. The p ⁺ -type source region 7, the n ⁺ -type source region 19, and the integrated surrounding gate electrode 10 each have a Cu having a barrier metal (TaN) 26 via a conductive plug (W) 24 having a barrier metal (TiN) 23. The wiring 27 is connected. Note that the integrated surrounding gate electrode is formed to have a thick gate electrode thickness at the connection portion with the wiring body and at the integration portion, and thin at the other portions.

In FIG. 2 (direction indicated connections to different conductivity type drain region), a silicon oxide film (SiO 2) ₂ is provided on the silicon substrate 1 of p-type, on the silicon oxide film (SiO 2) ₂ is A first barrier metal layer (underlying insulating film barrier layer, TiN) 3 is selectively provided, and an n-type Si layer 5 is disposed immediately above the first barrier metal layer (underlying insulating film barrier layer, TiN) 3. (First lateral (horizontal) direction epitaxial semiconductor layer) is provided, and an n-type Si layer 6 (first longitudinal (vertical) direction epitaxial semiconductor layer) is selectively provided on the Si layer 5, An n-type SOI substrate composed of the Si layer 5 and the Si layer 6 is provided by being insulated and isolated in an island shape by a silicon nitride film (Si ₃ N ₄ ) 4. A side surface of the Si layer 6 is surrounded by a gate electrode (WSi, an integral surrounding gate electrode) 10 via a gate oxide film (SiO ₂ ) 9. On top of the Si layer 6, ^{p +} -type drain region 8 is provided, in the lower portion of the Si layer 6, ^{p +} -type source region 7 is provided relative to the ^{p +} -type drain region 8, ^{p +} -type source A vertical (vertical operation) P-channel MIS field effect transistor having a structure in which the region 7 extends and is also provided in the entire Si layer 5 is formed. A second barrier metal layer (underlying insulating film barrier layer / conductive film for connecting different conductivity type drain regions, TiN) 12 is selectively provided on the Si layer 6 so as to partially contact the Si layer 6. The p-type Si layer 14 (second lateral (horizontal) direction epitaxial semiconductor layer) is directly above the second barrier metal layer (underlying insulating film barrier layer and conductive film for connecting different conductivity type drain region, TiN) 12. ) And a p-type Si layer 15 (second longitudinal (vertical) epitaxial semiconductor layer) is selectively provided on the Si layer 14, and a p-type layer composed of the Si layer 14 and the Si layer 15 is provided. An SOI substrate is provided by being insulated and isolated in an island shape by a silicon nitride film (Si ₃ N ₄ ) 13. The side surface of the Si layer 15 is surrounded by a gate electrode (WSi, integrated surrounding gate electrode) 10 via a gate oxide film (SiO ₂ ) 20. On top of the Si layer 15, n-type and ^{n +} -type source region (18, 19) are mounted on the lower portion of the Si layer 15, relative to n-type and the ^{n +} -type source region (18, 19) N-type and n ⁺ -type drain regions (16, 17) are provided, and the n ⁺ -type drain region 16 extends and is provided in the entire Si layer 14 as well. A channel MIS field effect transistor is formed. Here, the p ⁺ -type drain region 8 and the n ⁺ -type drain region 16 are directly connected by a second barrier metal layer (underlying insulating film barrier layer / conductive film for connecting a different conductivity type drain region, TiN) 12. n ⁺ -type source region 19 and the second barrier metal layer (underlying insulating film barrier layer and different conductivity type drain region for connection of the conductive film, TiN) 12 by direct the attached n ⁺ -type and p ⁺ -type drain region 8 The drain region 16 is connected to a Cu wiring 27 having a barrier metal (TaN) 26 via a conductive plug (W) 24 having a barrier metal (TiN) 23.

Further, if FIGS. 1 and 2 are regarded as a CMOS type inverter, a ground voltage (Vss) is applied to the Cu wiring 27 to which the n ⁺ type source region 19 is connected, and the Cu wiring 27 to which the p ⁺ type source region 7 is connected. When a power supply voltage (Vdd) is applied and an input voltage (Vin) is applied to the Cu wiring 27 to which the integrated surrounding gate electrode 10 is connected, a second barrier metal layer (underlying insulating film barrier layer / different conductivity type drain region) The output voltage (Vout) can be taken out from the Cu wiring 27 connected to the n ⁺ type drain region 16 directly connected to the p ⁺ type drain region 8 by the conductive film for connection, TiN) 12.

Therefore, the first barrier metal layer (underlying insulating film barrier layer) is provided on the insulating film by using an ordinary inexpensive semiconductor substrate and utilizing the epitaxial growth technology (the manufacturing method will be described in detail separately). A first lateral (horizontal) semiconductor layer is grown directly on the barrier metal layer, and a second vertical (vertical) semiconductor layer is selectively grown on the first lateral (horizontal) semiconductor layer, And forming a p ⁺ type drain region on the upper part of the first vertical (vertical) semiconductor layer and providing a p ⁺ type source region on the lower side and extending away from the first vertical (vertical) semiconductor layer. A p ⁺ -type source region is also provided in the entire first lateral (horizontal) direction semiconductor layer, and a second barrier metal layer (underlying insulating layer) is partially in contact with the first longitudinal (vertical) direction semiconductor layer. A film barrier layer and a conductive film for connecting a different conductivity type drain region) and a second barrier film. A second lateral (horizontal) direction semiconductor layer is grown directly on the tall layer, and a second longitudinal (vertical) direction semiconductor layer is selectively grown on the second lateral (horizontal) direction semiconductor layer, As an SOI substrate, n-type and n ⁺ -type source regions are provided above the second vertical (vertical) direction semiconductor layer, and n-type and n ⁺ -type drain regions are provided below and spaced apart from each other. An n ⁺ -type drain region is also provided in the entire second lateral (horizontal) direction semiconductor layer, and gate insulation is provided on the side surfaces of the first vertical (vertical) direction semiconductor layer and the second vertical (vertical) direction semiconductor layer, respectively. Since an SOI-structure CMOS comprising vertical (vertical operation) N-channel and P-channel MIS field effect transistors having a surrounding gate electrode integrated through a film can be formed, a source / drain region can be formed. Reduction of junction capacitance (substantially zero), depletion layer capacitance It is possible to reduce the threshold voltage, lower power, etc. by reducing the amount, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics.
Also, by providing a barrier layer (underlying insulating film barrier layer) on the upper surface of the insulating film so that the epitaxially growing semiconductor layer and the underlying insulating film do not come into contact with each other during the growth of the semiconductor layer by epitaxial growth, It is possible to form an SOI substrate including a fully depleted single crystal semiconductor layer in which partial amorphization due to the influence of the base insulating film is prevented.
Moreover, since the channel region can be formed by surrounding the gate electrode provided through the gate oxide film, the current path other than the channel can be cut off, and not only the complete channel control by the surrounding gate electrode is possible. Since a channel can be formed on all side surfaces, the channel width can be increased without increasing the occupied area of the surface (upper surface), and thus the drive current can be increased.
Further, by an easy manufacturing process (details will be described later), the surrounding gate electrode of the P-channel MIS field effect transistor and the surrounding gate electrode of the N-channel MIS field effect transistor can be integrally formed as a single surrounding gate electrode. High integration can be made possible by eliminating the wiring body.
Further, it is possible to achieve high integration by forming a stacked structure CMOS with almost one MIS field effect transistor occupied area without increasing the occupied area on the surface.
Further, the wiring body to the n ⁺ -type drain region and the wiring body to the p ⁺ -type drain region are not provided separately, but are provided immediately below the second lateral (horizontal) direction semiconductor layer in which the n ⁺ -type drain region is formed. The n ⁺ -type drain region and the p ⁺ -type drain region can be directly connected by the second barrier metal layer (conductive film for connecting the underlying insulating film barrier layer and the different conductivity type drain region), so that one wiring body can be eliminated. High integration can be achieved. (Especially effective for inverter circuits.)
Further, the channel length for determining various characteristics of the MIS field effect transistor can be determined by the growth thickness of the epitaxial semiconductor layer having good controllability and the diffusion of impurities by heat treatment without depending on the control of the gate length by the photolithography technique. In addition, a MIS field effect transistor having stable characteristics can be obtained even in a large-diameter wafer.
Further, since a complete SOI structure CMOS circuit can be formed, it is possible to completely prevent malfunction due to high voltage noise generated in a semiconductor substrate due to static electricity or the like or latch-up characteristics peculiar to CMOS.
Also, a buried part that forms a part of the element isolation region by self-aligning the longitudinal (vertical) direction epitaxial semiconductor layer (see the manufacturing method) necessary for forming the first and second lateral (horizontal) direction semiconductor layers. High reliability and high integration can be achieved by being able to convert to an insulating film.
In addition, it is self-aligned with a fine columnar semiconductor layer (first and second vertical (vertical) semiconductor layers) having very good crystallinity, and the components of the MIS field effect transistor (low and high concentration). It is also possible to finely form a source / drain region, a gate oxide film, and an integrated surrounding gate electrode.
In other words, high-speed, high-reliability, high-performance, and high-speed, capable of manufacturing large-scale semiconductor integrated circuits that can be used for high-speed, large-capacity communication devices, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. A CMOS semiconductor device having an extremely low power SOI structure having integration can be obtained.

  Next, referring to FIGS. 3 to 30, FIG. 1 and FIG. 2 for the manufacturing method of the first embodiment in the semiconductor device according to the present invention, the schematic side sectional view in the direction showing the connecting portion to the integrally enclosed gate electrode. Will be described. However, here, only the manufacturing method relating to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.

FIG.
A silicon oxide film (SiO ₂ ) 2 of about 150 nm is grown on the p-type silicon substrate 1 by chemical vapor deposition. Next, a first barrier metal layer (underlying insulating film barrier layer, TiN) 3 of about 30 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 29 serving as an insulating film for defining the epitaxial semiconductor layer thickness is grown by about 60 nm by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 29, a first barrier metal layer (underlying insulating film barrier layer, TiN) 3 and the silicon oxide film (SiO ₂ ) 2 are sequentially subjected to anisotropic dry etching to form an opening. Next, the resist (not shown) is removed.

FIG.
Next, an n-type vertical (vertical) epitaxial Si layer 30 is grown on the exposed p-type silicon substrate 1. Then, chemical mechanical polishing (hereinafter abbreviated as CMP) is performed to planarize the vertical (vertical) epitaxial Si layer 30 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 29. Next, a tungsten film 31 of about 30 nm is grown by selective chemical vapor deposition.

FIG.
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 29 is anisotropically dry-etched using a resist (not shown) as a mask layer, and a longitudinal (vertical) direction epitaxial Si layer An opening is formed to expose a partial side surface of 30 and a partial upper surface of the first barrier metal layer (underlying insulating film barrier layer, TiN) 3. Next, the resist (not shown) is removed.

FIG.
Next, an n-type first lateral (horizontal) epitaxial Si layer 5 is grown on the first barrier metal layer (underlying insulating film barrier layer, TiN) 3 from the exposed side surface of the longitudinal (vertical) epitaxial Si layer 30. Then, the opening portion of the silicon nitride film (Si ₃ N ₄ ) 29 is embedded. The grown Si layer 5 becomes a complete single crystal semiconductor layer that is not affected by the underlying silicon oxide film (SiO ₂ ) 2 by the first barrier metal layer (underlying insulating film barrier layer, TiN) 3. (Without this first barrier metal layer (underlying insulating film barrier layer, TiN) 3, a part of the semiconductor layer becomes amorphous due to the influence of the underlying silicon oxide film (SiO ₂ ) 2. (This may cause minute current leakage.)

FIG.
Next, the surface of the Si layer 5 is oxidized at about 900 ° C. to grow a silicon oxide film (SiO ₂ ) 32 of about 20 nm. Next, using the silicon oxide film (SiO ₂ ) 32 as a mask layer, a tungsten film 31, a Si layer 30, a silicon nitride film (Si ₃ N ₄ ) 29, and a first barrier metal layer (underlying insulating film barrier layer, TiN) 3 are formed. Sequential anisotropic dry etching is performed to form two-stage apertures.

FIG.
Next, a silicon nitride film (Si ₃ N ₄ ) of about 80 nm is grown by chemical vapor deposition. Next, the silicon nitride film (Si ₃ N ₄ ) and the silicon oxide film (SiO ₂ ) 32 on the flat surface of the Si layer 5 are subjected to chemical mechanical polishing (CMP) to open the silicon nitride film (Si ₃ N ₄ ) 4. A buried element isolation region is formed flat in the part.

FIG.
Next, a silicon oxide film (SiO ₂ ) 33 of about 150 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, the silicon oxide film (SiO ₂ ) 33 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. (The opening width is about 80 nm) Next, the resist (not shown) is removed.

FIG.
Next, an n-type first longitudinal (vertical) epitaxial Si layer 6 is grown on the exposed Si layer 5. Next, chemical mechanical polishing (CMP) is performed to flatten the first vertical (vertical) epitaxial Si layer 6 protruding from the flat surface of the silicon oxide film (SiO ₂ ) 33.

FIG.
Next, the silicon oxide film (SiO ₂ ) 33 is removed by etching. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, boron ions for controlling the threshold voltage are implanted into the Si layer 6. Next, it is run at about 700 ° C. and controlled to a desired threshold voltage. Next, boron ions are implanted into the Si layer 5 and the Si layer 6 to form p ⁺ -type source / drain regions (7, 8). Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. (Here it does not perform the heat treatment step for activating and controlling the depth of the p ⁺ -type source and drain regions, p ⁺ -type source and drain regions previously shown.)

FIG.
Next, the exposed surfaces of the Si layer 5 and the Si layer 6 are oxidized to grow a gate oxide film (SiO ₂ ) 9 of about 5 nm. Next, a tungsten silicide film (WSi) 10a of about 150 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove and planarize the gate oxide film (SiO ₂ ) 9 and tungsten silicide film (WSi) 10a grown above the flat surface of the Si layer 6.

FIG.
Next, the tungsten silicide film (WSi) 10a is anisotropically dry-etched using a resist (not shown) as a mask layer using a normal lithography technique using an exposure drawing apparatus. Next, the resist (not shown) is removed. Next, the tungsten silicide film (WSi) 10a and the gate oxide film (SiO ₂ ) 9 are sequentially subjected to anisotropic dry etching (overetching) of about 50 nm to form a lower-layer surrounding gate electrode 10a.

FIG.
Next, a PSG film 11 of about 150 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and the PSG film 11 grown above the flat surface of the Si layer 6 is removed and flattened.

FIG.
Next, a second barrier metal layer (underlying insulating film barrier layer / conductive film for connecting a different conductivity type drain region, TiN) 12 of about 50 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 34 to be an epitaxial semiconductor layer thickness regulating insulating film is grown by about 50 nm by chemical vapor deposition.

FIG.
Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 34, a second barrier metal layer (underlying insulating film barrier layer and heterogeneous conductivity) The conductive film for connecting the drain region, TiN) 12 and the PSG film 11 are sequentially subjected to anisotropic dry etching to form an opening that exposes a part of the surface of the Si layer 5. Next, the resist (not shown) is removed.

FIG.
Next, a p-type vertical (vertical) epitaxial Si layer 35 is grown on the exposed Si layer 5 by an ECR plasma CVD enhanced chemical vapor deposition deposition system capable of low-temperature growth (500 ° C. or lower). . Next, chemical mechanical polishing (CMP) is performed to flatten the vertical (vertical) epitaxial Si layer 35 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 34. Next, a tungsten film 36 of about 30 nm is grown by selective chemical vapor deposition.

FIG.
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 34 is anisotropically dry etched using a resist (not shown) as a mask layer, and a longitudinal (vertical) direction epitaxial Si layer An opening is formed that exposes a part of the side surface 35 and a part of the upper surface of the second barrier metal layer (underlying insulating film barrier layer and conductive film for connecting different conductivity type drain region, TiN) 12. Next, the resist (not shown) is removed.

FIG.
Next, by using an ECR plasma CVD apparatus capable of low-temperature growth (500 ° C. or less), the second barrier metal layer (underlying insulating film barrier layer also serving as a different conductivity type drain region connection is formed from the side surface of the exposed vertical (vertical) epitaxial Si layer 35. A p-type second lateral (horizontal) epitaxial Si layer 14 is grown on the conductive film TiN) 12 and a hole in the silicon nitride film (Si ₃ N ₄ ) 34 is buried. The Si layer 14 grown here is a complete single crystal that is not affected by the underlying PSG film 11 by the second barrier metal layer (underlying insulating film barrier layer / conductive film for connecting different conductivity type drain regions, TiN) 12. It becomes a semiconductor layer. (Semiconductor partially amorphized under the influence of the underlying PSG film 11 without the second barrier metal layer (underlying insulating film barrier layer and conductive film for connecting a different conductivity type drain region, TiN) 12 It becomes a layer and causes a minute current leak.)

FIG.
Next, using a normal lithography technique by an exposure drawing apparatus, a resist (not shown) is used as a mask layer, a tungsten film 36, a Si layer (14, 35, 5), a silicon nitride film (Si ₃ N ₄ ) 34, and a second layer. Two barrier metal layers (underlying insulating film barrier layer and conductive film for connecting different conductivity type drain regions, TiN) 12 are sequentially subjected to anisotropic dry etching to form two-stage openings. (At this time, a part of the lower first barrier metal layer 3 is also removed.) Next, the resist (not shown) is removed.

FIG.
Next, a silicon nitride film (Si ₃ N ₄ ) of about 100 nm is grown by chemical vapor deposition. Next, the silicon nitride film (Si ₃ N ₄ ) on the flat surface of the Si layer 14 is subjected to chemical mechanical polishing (CMP), and the silicon nitride film (Si ₃ N ₄ ) 13 is flatly embedded in the opening to form an element isolation region. Form.

FIG.
Next, a silicon oxide film (SiO ₂ ) 37 having a thickness of about 150 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, the silicon oxide film (SiO ₂ ) 37 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. (The opening width is about 80 nm) Next, the resist (not shown) is removed.

FIG.
Next, a p-type second longitudinal (vertical) epitaxial Si layer 15 is grown on the exposed Si layer 14 by an ECR plasma CVD apparatus capable of low-temperature growth (500 ° C. or less). Next, chemical mechanical polishing (CMP) is performed to planarize the second vertical (vertical) epitaxial Si layer 15 protruding from the flat surface of the silicon oxide film (SiO ₂ ) 37.

FIG.
Next, the silicon oxide film (SiO ₂ ) 37 is removed by etching. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, boron ions for controlling the threshold voltage are implanted into the Si layer 15. Next, phosphorus ions are implanted into the Si layer 14 and Si layer 15 for forming the n-type source / drain regions (17, 18), and arsenic ions are implanted successively to form the n ⁺ -type source / drain regions (16, 19). Do it. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. (Although not performed here n-type and the n ⁺ -type source and drain region a heat treatment step of the activation and depth control of, the n-type and n ⁺ -type source and drain regions previously shown.)

FIG.
Next, the exposed surfaces of the Si layer 14 and the Si layer 15 are oxidized to grow a gate oxide film (SiO ₂ ) 20 of about 5 nm. Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 13 and the PSG film 11 are sequentially subjected to anisotropic dry etching using a resist (not shown) as a mask layer to surround the lower layer An opening that exposes a portion of the mold gate electrode 10a is formed. (The opening width is about 80 nm) Next, the resist (not shown) is removed.

FIG.
Next, a tungsten silicide film (WSi) 10b of about 150 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove and planarize the gate oxide film (SiO ₂ ) 9 and tungsten silicide film (WSi) 10b grown above the flat surface of the Si layer 15.

FIG.
Next, the tungsten silicide film (WSi) 10b is anisotropically dry-etched using a resist (not shown) as a mask layer using a normal lithography technique using an exposure drawing apparatus. Next, the resist (not shown) is removed. Next, the tungsten silicide film (WSi) 10b and the gate oxide film (SiO ₂ ) 20 are successively subjected to anisotropic dry etching (overetching) by about 50 nm to form an upper-layer surrounding gate electrode 10b. Thus, the integrated surrounding gate electrode 10 in which the lower surrounding gate electrode 10a and the upper surrounding gate electrode 10b are integrated is formed. Next, annealing for activation and depth control is performed by an RTP (Rapid Thermal Processing) method, p ⁺ -type source / drain regions (7, 8) are formed in the Si layer 5 and the Si layer 6, and the Si layer 14 and the Si layer 15 are formed. An n-type source / drain region (17, 18) and an n ⁺ -type source / drain region (16, 19) are formed.

FIG.
Next, a PSG film 21 of about 300 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, a silicon nitride film (Si ₃ N ₄ ) 22 of about 20 nm is grown by chemical vapor deposition.

FIG.
Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 22, a PSG film 21, a silicon nitride film (Si ₃ N ₄ ) 13, and The PSG film 11 is sequentially subjected to anisotropic dry etching to form vias. Next, the resist (not shown) is removed.

FIG.
Next, TiN 23 serving as a barrier metal is grown by chemical vapor deposition. Next, tungsten (W) 24 is grown by chemical vapor deposition. Next, a conductive plug (W) 24 having a barrier metal (TiN) 23 is formed by chemical mechanical polishing (CMP).

FIG. 1 (direction showing the connecting portion to the integrated surrounding gate electrode) and FIG. 2 (direction showing the connecting portion to the different conductivity type drain region)
Next, an insulating film (SiOC) 25 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique using an exposure drawing apparatus, the SiOC film 25 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 24 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 26 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, and Cu is flatly embedded in the opening portion to form a Cu wiring 27 having a barrier metal (TaN) 26. Next, a silicon nitride film (Si ₃ N ₄ ) 28 serving as a Cu barrier insulating film is grown by chemical vapor deposition to complete the semiconductor device having the AVECC BAMS SUG structure of the present invention.

FIG. 31 is a schematic sectional side view of the second embodiment of the semiconductor device of the present invention. Vertical (vertical operation) N-channel and P-channel MIS electric fields formed in an AVECCBAMSSUG structure using a silicon (Si) substrate. 1 shows a part of a CMOS type semiconductor integrated circuit composed of effect transistors, in which 1 to 28 are the same as in FIG. 1, and 38 is a lower connection wiring body (WSi).
In the figure, there is no Cu wiring 27 directly connected to the p ⁺ type source region of the P channel MIS field effect transistor, but instead a first barrier metal layer (underlying insulating film barrier layer immediately below the p ⁺ type source region). , TiN) 3, a semiconductor device having substantially the same structure as that of FIG. 1 is formed except that a lower connection wiring body (WSi) 38 connected from below is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and a step of forming a lower connection wiring body (WSi) is required before forming the SOI substrate of the P-channel MIS field effect transistor. However, it is possible to achieve high integration by forming the first lateral (horizontal) epitaxial Si layer finely.

FIG. 32 (direction showing the connection portion to the integrated surrounding gate electrode) and FIG. 33 (direction showing the connection portion to the individual drain region) are schematic side sectional views of the third embodiment of the semiconductor device of the present invention. 1 shows a part of a CMOS type semiconductor integrated circuit composed of vertical (vertical operation) N-channel and P-channel MIS field effect transistors formed on an AVECCBAMSSUG structure using a silicon (Si) substrate. 1 is the same as FIG. 1, 39 is an upper connection wiring body (WSi), and 40 is a silicon oxide film (SiO ₂ ).
In the figure, the drain region of the different conductivity type is separated and formed by the silicon oxide film (SiO ₂ ) 40, and the wiring body (WSi) 39 is provided on the drain region of the P-channel MIS field effect transistor. A semiconductor device having substantially the same structure as that of FIGS. 1 and 2 is formed except that the Cu wiring 27 connected to the wiring body (WSi) 39 is provided.
In this embodiment, the same effect as that of the first embodiment can be obtained, and both drain regions can be freely wired. Therefore, in an integrated circuit including a 2-input NAND circuit or a 2-input NOR circuit, By combining with the first embodiment or the second embodiment, it is possible to form a highly integrated circuit that is easy to use.

FIG. 34 (direction showing the connecting portion to the integrated surrounding gate electrode) and FIG. 35 (direction showing the connecting portion to the different conductivity type drain region) are schematic side cross sections of the fourth embodiment of the semiconductor device of the present invention. In the figure, a part of a CMOS type semiconductor integrated circuit composed of vertical (vertical operation) N-channel and P-channel MIS field effect transistors formed on an AVECCBAMSSUG structure using a silicon (Si) substrate is shown. 1 to 28 are the same as in FIG. 1, 41 is an n-type silicon (Si) substrate, 42 is an n ⁺ type substrate contact region, 43 is a trench element isolation region (Si ₃ N ₄ ), 44 is an n ⁺ type channel stopper Indicates the area.
In the figure, a P-channel MIS field effect transistor is formed on an n-type silicon (Si) substrate 41 and an n-type Si layer (first vertical (vertical) epitaxial semiconductor layer) 6, and n-type. The p ⁺ type source region 7 formed on the silicon (Si) substrate 41 is separated and defined by a trench element isolation region (Si ₃ N ₄ ) 43 provided with an n ⁺ type channel stopper region 44 at the bottom. A semiconductor device having substantially the same structure as that of FIG. 1 is formed except that an n ⁺ -type substrate contact region is formed on an n-type silicon (Si) substrate 41.
In this embodiment, substantially the same effect as in the first embodiment can be obtained, and a junction capacitance exists between the p ⁺ type source region and the n type silicon (Si) substrate. It can be somewhat simpler.

In the above embodiment, chemical vapor deposition is used when growing the semiconductor layer. However, the present invention is not limited to this, and molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) is also used. Alternatively, atomic layer crystal growth (ALE) or any other crystal growth method may be used.
In the above embodiment, a CMOS type semiconductor integrated circuit is formed in which a P-channel MIS field effect transistor is formed in the lower semiconductor layer and an N-channel MIS field effect transistor is formed in the upper semiconductor layer. May be formed.
The gate electrode, gate oxide film, barrier metal, conductive plug, wiring, insulating film, barrier metal layer (base insulating film barrier layer or base insulating film barrier layer and conductive film for connecting different conductivity type drain regions), etc. are implemented as described above. The material is not limited to an example, and any material having similar characteristics may be used.
In addition, although all of the above embodiments describe the case where an enhancement type MIS field effect transistor is formed, a depletion type MIS field effect transistor may be formed. In this case, an epitaxial semiconductor layer having the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing an epitaxial semiconductor layer and then ion-implanting an impurity of the opposite conductivity type to convert the conductivity type. A MIS field effect transistor may be formed.
Further, in the above embodiment, the CMOS type semiconductor integrated circuit is formed in which the MIS field effect transistors of different conductivity types are formed in the upper and lower convex structure semiconductor layers, respectively, but the MIS field effect transistor of the same conductivity type is formed. It is also possible to use it when doing so.

The present invention is particularly aimed at a semiconductor device with extremely high integration, high speed, and high reliability. However, the present invention is not limited to high speed and can be used for all CMOS type semiconductor integrated circuits.
In addition to the MIS field effect transistor, there is a possibility that it can be used for a semiconductor integrated circuit including other transistors.

1 p-type silicon (Si) substrate 2 silicon oxide film (SiO ₂ )
3 First barrier metal layer (underlying insulating film barrier layer, TiN)
4 Silicon nitride film in element isolation region (Si ₃ N ₄ )
5 n-type Si layer (first lateral (horizontal) direction epitaxial semiconductor layer)
6 n-type Si layer (first longitudinal (vertical) direction epitaxial semiconductor layer)
7 p ⁺ type source region 8 p ⁺ type drain region 9 Gate oxide film (SiO ₂ )
10 Integrated enclosed gate electrode (WSi)
10a Surrounding gate electrode (WSi) of lower MIS field effect transistor
10b Surround MIS field effect transistor surrounding gate electrode (WSi)
11 Phosphorsilicate glass (PSG) film 12 Second barrier metal layer (underlying insulating film barrier layer and conductive film for connecting different conductivity type drain region, TiN)
13 Silicon nitride film (Si ₃ N ₄ ) in element isolation region
14 p-type Si layer (second lateral (horizontal) direction epitaxial semiconductor layer)
15 p-type Si layer (second longitudinal (vertical) direction epitaxial semiconductor layer)
16 n ⁺ type drain region 17 n type drain region 18 n type source region 19 n ⁺ type source region 20 Gate oxide film (SiO ₂ )
21 Phosphorsilicate glass (PSG) film 22 Silicon nitride film (Si ₃ N ₄ )
23 Barrier metal (TiN)
24 Conductive plug (W)
25 SiOC film 26 Barrier metal (TaN)
27 Cu wiring (including Cu seed layer)
28 Barrier insulating film (Si ₃ N ₄ )
29 Silicon nitride film (Si ₃ N ₄ )
30 n-type vertical (vertical) epitaxial Si layer 31 selective chemical vapor deposition conductive film (W)
32 Silicon oxide film (SiO ₂ )
33 Silicon oxide film (SiO ₂ )
34 Silicon nitride film (Si ₃ N ₄ )
35 p-type vertical (vertical) epitaxial Si layer 36 selective chemical vapor deposition conductive film (W)
37 Silicon oxide film (SiO ₂ )
38 Lower connection wiring (WSi)
39 Upper connection wiring body (WSi)
40 Silicon oxide film (SiO ₂ )
41 n-type silicon (Si) substrate 42 n ⁺ -type substrate contact region 43 trench element isolation region (Si ₃ N ₄ )
44 n ⁺ type channel stopper region

Claims (3)

  A semiconductor substrate; an insulating film provided on the semiconductor substrate; a first barrier metal layer selectively provided on the insulating film; and the first barrier on the first barrier metal layer. A first semiconductor layer having a flat plate structure having the same size as the metal layer, a second semiconductor layer having a columnar structure selectively provided on the first semiconductor layer, and the second semiconductor layer A second barrier metal layer selectively provided in contact with a part of the second semiconductor layer, and a size of the second barrier metal layer on the second barrier metal layer; A third semiconductor layer having a flat plate structure provided in correspondence, a fourth semiconductor layer having a columnar structure selectively provided on the third semiconductor layer, the entire first semiconductor layer, and the first semiconductor layer; And a first impurity region provided in a lower portion of the semiconductor layer, relative to the first impurity region. A second impurity region provided above the second semiconductor layer, a third impurity region provided below the entire third semiconductor layer and the fourth semiconductor layer, and the third impurity region. And a fourth impurity region provided on the fourth semiconductor layer relative to the impurity region, wherein the second impurity region and the third impurity region are the second barrier metal layer. A semiconductor device characterized by being connected by   The first and second semiconductor layers constitute a semiconductor layer of one conductivity type, the third and fourth semiconductor layers constitute a semiconductor layer of opposite conductivity type, and the first and second impurity regions are oppositely conductive. A source / drain region of a type, and the third and fourth impurity regions form a source / drain region of one conductivity type, and are integrated with at least a side surface of the second and fourth semiconductor layers via a gate insulating film. A complementary MIS electric field provided with a gate electrode (integrated enclosure type gate electrode) having a surrounding structure and composed of a MIS field effect transistor of one conductivity type and an opposite conductivity type of a vertical structure (vertical operation) having a laminated structure. The semiconductor device according to claim 1, comprising an effect transistor.   A step of sequentially forming a first insulating film, a first barrier metal layer, and a second insulating film on a semiconductor substrate; and, selectively, the second insulating film, the first barrier metal layer, and the first And sequentially etching away the insulating film to form a first opening, exposing a part of the upper surface of the semiconductor substrate, and a first vertical epitaxial semiconductor layer in the first opening. Forming and planarizing, a step of forming a first mask layer on the upper surface of the first vertical epitaxial semiconductor layer, a portion of the second insulating film is selectively etched away, Forming a second opening exposing a part of the side surface of the first vertical epitaxial semiconductor layer; and first lateral epitaxial semiconductor from the exposed side surface of the first vertical epitaxial semiconductor layer. Forming a layer and flattening the second aperture. Burying in, a step of forming a second mask layer on the top surface of the first lateral epitaxial semiconductor layer, and using the second mask layer as an etching mask, the first mask layer, the first mask layer, A step of sequentially removing the vertical epitaxial semiconductor layer, the second insulating film, and the first barrier metal layer by etching to form a third hole portion; and a third insulation in the third hole portion. Embedding a film, removing the second mask layer, planarizing, forming a fourth insulating film, and selectively forming a fourth opening in the fourth insulating film; Exposing a part of the upper surface of the first lateral epitaxial semiconductor layer; forming a second vertical epitaxial semiconductor layer in the fourth hole portion; and planarizing the second vertical epitaxial semiconductor layer; Removing the insulating film by etching, and exposing the exposed Ion implantation of one conductivity type impurity into the upper surfaces of the two longitudinal epitaxial semiconductor layers and the first lateral epitaxial semiconductor layer; the second longitudinal epitaxial semiconductor layer and the first lateral epitaxial semiconductor; Forming a first gate insulating film on the exposed surface of the layer; growing a first gate electrode formation film; and planarizing to a height of the second longitudinal epitaxial semiconductor layer; The gate electrode forming film is selectively etched away to form a lower-layer surrounding gate electrode, and a fifth insulating film is grown and planarized to the height of the second vertical epitaxial semiconductor layer. A step of sequentially forming a second barrier metal layer and a sixth insulating film, and selectively etching the sixth insulating film, the second barrier metal layer, and the fifth insulating film sequentially Forming a fifth opening, exposing a part of the upper surface of the first lateral epitaxial semiconductor layer, and a third vertical epitaxial semiconductor in the fifth opening. Forming and planarizing a layer; forming a third mask layer on an upper surface of the third longitudinal epitaxial semiconductor layer; and selectively etching away a part of the sixth insulating film. A step of forming a sixth opening exposing a part of the side surface of the third vertical epitaxial semiconductor layer, and a second lateral epitaxial layer from the exposed side surface of the third vertical epitaxial semiconductor layer. Forming a semiconductor layer and filling the sixth opening portion flatly, selectively the third mask layer, the third longitudinal epitaxial semiconductor layer, the sixth insulating film, and the second Etch the barrier metal layers sequentially A step of forming a seventh opening, a step of flatly embedding a seventh insulating film in the seventh opening, a step of forming an eighth insulating film, and the eighth Forming an eighth opening selectively in the insulating film and exposing a part of the upper surface of the second lateral epitaxial semiconductor layer; and a fourth vertical direction in the eighth opening. Forming and planarizing an epitaxial semiconductor layer; etching removing the eighth insulating film; and exposing the upper surfaces of the fourth vertical epitaxial semiconductor layer and the second lateral epitaxial semiconductor layer. Selectively implanting impurities of opposite conductivity type, forming a second gate insulating film on the exposed surfaces of the fourth longitudinal epitaxial semiconductor layer and the second lateral epitaxial semiconductor layer, and selectively The seventh insulating film and the fifth insulating film; The insulating film is removed by etching in order to form a ninth opening exposing a part of the upper surface of the lower-layer surrounding gate electrode, and a second gate electrode forming film is grown. A step of filling the opening and flattening to the height of the fourth vertical epitaxial semiconductor layer, and selectively etching away the second gate electrode formation film to form an integral enclosed gate electrode And a step of forming a one-conductivity-type source / drain region and an opposite-conductivity-type source / drain region by performing heat treatment.