JP2018107231A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated CMOS having the same channel length around an entire circumference and an integrated surrounding gate electrode.SOLUTION: A CMOS comprises: lower semiconductor layers (11, 12) provided on a semiconductor substrate 1 via interlayer insulation films (2-4); upper semiconductor layers (15-17) provided via laminated interlayer insulation films 6; and an integrated surrounding gate electrode 23 provided around an entire circumference of part (12, 17) of the lower and upper semiconductor layers with a structure to surround the entire circumference via a gate insulation film 22, in which P channel and N channel MIS field effect transistors has a laminated structure composed of one conductivity type source/drain regions (13, 14) with one end being opposite to the part 11 of the lower semiconductor layers and forming a plane perpendicular to a principal surface of the semiconductor substrate in a self-aligned manner with the integrated surrounding gate electrode 23, and opposite conductivity type source/drain regions (18-21) with an end being opposite to the part (15, 16) of the upper semiconductor layers and forming a plane perpendicular to the principal surface of the semiconductor substrate in a self-aligned manner with the integrated surrounding gate electrode 23.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit having an SOI (Silicon On Insulator) structure. In particular, a low-cost multilayer SOI substrate made of single crystal silicon is formed on a semiconductor substrate (bulk wafer) by an easy manufacturing process. The present invention relates to forming a CMOS type semiconductor integrated circuit including short-channel N-channel and P-channel MIS field effect transistors on a substrate with high integration, high speed, low power, high performance, and high reliability.

FIG. 52 is a schematic cross-sectional side view of a conventional semiconductor device, and shows a part of a CMOS type semiconductor integrated circuit composed of N-channel and P-channel MIS field effect transistors formed by utilizing a selective epitaxial growth method of a semiconductor layer. In the figure, 61 is a p-type silicon substrate, 62 is a silicon nitride film, 63 is a silicon oxide film, 64 is a silicon nitride film in an element isolation region, 65 is an n-type Si layer (a part of the lower semiconductor layer), 66 is an n-type Si layer (a part of the lower semiconductor layer), 67 is a conductive film (a part of the source / drain region), 68 is a buried insulating film, 69 is a p ⁺ type source region, and 70 is a p ⁺ type drain region. , 71 is a silicon oxide film, 72 is a silicon nitride film in the element isolation region, 73 is a p-type Si layer (a part of the upper semiconductor layer), 74 is a p-type Si layer (a part of the upper semiconductor layer), 75 Is buried Inclusive insulating film, the lower semiconductor layer a gate oxide film 76, the upper semiconductor layer a gate oxide film 77, the integrated surround gate electrode 78, 79 is a silicon oxide film, 80 holes, the n ⁺ -type source 81 Region, 82 is an n-type source region, 83 is an n-type drain region, 84 is an n ⁺ -type drain region, 85 is a sidewall, 86 is a phosphosilicate glass (PSG) film, 87 is a silicon nitride film, 88 is a barrier metal, Reference numeral 89 denotes a conductive plug, 90 denotes an interlayer insulating film, 91 denotes a barrier metal, 92 denotes a Cu wiring, and 93 denotes a barrier insulating film.
In the figure, a silicon nitride film 62 is provided on a p-type silicon substrate 61, a silicon oxide film 63 is selectively provided on the silicon nitride film 62, and a pair of n-type is provided on the silicon oxide film 63. The Si layer 65 is provided, the n-type Si layer 66 is sandwiched between the opposing side surfaces of the pair of Si layers 65, and the conductive film 67 is provided on the opposite side surface of the pair of Si layers 65, respectively. The lower semiconductor layer (65, 66) having the above structure is provided, and the silicon oxide film 71 and the silicon oxide film 79 are selectively provided on the lower semiconductor layer (65, 66) having the conductive film 67, and silicon A structure in which a pair of p-type Si layers 73 are provided on the oxide film 79 through fine holes 80, and the p-type Si layer 74 is sandwiched between opposing side surfaces of the pair of Si layers 73. An upper semiconductor layer (73, 4), the lower semiconductor layer (65, 66) and the upper semiconductor layer (73, 74) having the conductive film 67 are the silicon nitride film (64, 72) and the buried insulating film (68, 75) in the element isolation region. Insulated and separated by islands. Surrounding the Si layer 66 and the Si layer 74 that coincide with each other in the vertical direction, a surrounding gate electrode 78 that is integrated (commonized) via a lower gate oxide film 76 or an upper gate oxide film 77 is provided. provided in the upper, the side wall of the upper surface portion of the integrated encircling the gate electrode 78 side wall 85 is provided, the Si layer 65, schematically ^{p +} -type source and drain regions (69, 70) is provided, the Si layer 66 is provided with a rough channel region (actually, the p ⁺ -type source / drain regions (69, 70) are slightly diffused in the lateral direction, the channel length is shorter at the top, and the channel length is longer toward the bottom. P-channel MIS field effect transistors (which form the channel region) are formed in the lower semiconductor layers (65, 66), while the Si layer 73 has a substantially n-type source. Provided a rain region (82, 83) and ^{n +} -type source and drain regions (81, 84), the Si layer 74, schematically channel region is provided (in fact the n-type source drain region (82, 83 ) Is slightly laterally diffused, and a channel region having a structure in which the channel length is shorter at the upper part and the channel length is longer at the lower part is formed.) An N-channel MIS field effect transistor having an LDD structure is formed in the upper semiconductor layer (73). 74). In addition, the conductive film 67, the n ⁺ -type source / drain regions (81, 84), and the integrated surrounding gate electrode 78 that are side-connected to the p ⁺ -type source / drain regions (69, 70) have barrier metals 88, respectively. A Cu wiring 92 having a barrier metal 91 is connected via a conductive plug 89.
Therefore, using a normal inexpensive semiconductor substrate, a lower semiconductor layer and an upper semiconductor layer (SOI substrate) made of single crystal silicon each laminated on an insulating film are provided using an epitaxial growth technique, and each SOI substrate is provided. In the SOI structure, a surrounding gate electrode integrated (commonized) through a gate oxide film is provided around a part of the SOI substrate, a channel region is formed, and a source / drain region is provided on the remaining SOI substrate. N-channel and P-channel MIS field-effect transistors can be formed, so that the junction capacitance of the source / drain region is reduced (substantially zero), the depletion layer capacitance is reduced, and the subthreshold characteristics can be improved. Is possible.
In addition, since the channel region can be completely surrounded by the integrated surrounding gate electrode provided through the gate oxide film, the current path other than the channel can be cut off, complete channel control is possible, and back channel leakage Since the channel can be formed on four surfaces (upper and lower surfaces and two side surfaces in the channel width direction), the channel width can be increased without increasing the occupied area of the surface (upper surface), and the drive current is increased. It is also possible.
The upper and lower single crystal semiconductor layers can be formed, and the surface (upper surface) occupied area can be formed by forming the N-channel MIS field-effect transistor in the upper-layer semiconductor layer immediately above the P-channel MIS field-effect transistor formed in the lower-layer semiconductor layer. Can be formed as an enclosed gate electrode in which the gate electrode of the P-channel MIS field effect transistor and the gate electrode of the N-channel MIS field effect transistor are integrated in a self-aligned manner, thereby achieving high integration of the gate electrode wiring. It is possible.
However, since the connection to the source / drain region of the P-channel MIS field-effect transistor formed in the lower semiconductor layer is formed from the upper wiring, it is necessary to provide a lower semiconductor layer longer than the upper semiconductor layer (actually the upper layer) A pair of conductive films are provided at both ends of a lower semiconductor layer that is almost the same as the semiconductor layer to secure wiring connection points), and high integration is difficult.
In addition, in order to form a p ⁺ -type source / drain region in the lower semiconductor layer in a self-aligned manner with the integrated surrounding gate electrode, a part of the upper semiconductor layer other than the portion corresponding to the channel region and the interlayer insulating film immediately below must be temporarily removed. Therefore, when the manufacturing process becomes complicated and a part of the removed upper semiconductor layer and the interlayer insulating film are restored, fine vacancies exist, and n ⁺ type and n formed in the upper semiconductor layer There has been a problem that the leakage characteristics between the type source / drain region and the integrated surrounding type gate electrode deteriorate.
In addition, the channel region is formed all around the upper and lower semiconductor layers, but the channel length becomes longer as it goes to the lower part than the upper part (a source / drain region having a curvature is formed, and the lower the semiconductor layer, Since the diffusion distance in the direction is shortened), there are problems such that the shorter the channel is, the more unstable the driving current value of the MIS field effect transistor and the breakdown voltage between the source and drain regions deteriorate.

JP2014-96441

The problem to be solved by the present invention is, as shown in the prior art, in the case of forming a stacked CMOS with a highly integrated SOI structure having an integrated surrounding gate electrode,
(1) Since the lower semiconductor layer had to be formed longer than the upper semiconductor layer in order to form the connection from the upper wiring, high integration was difficult.
(2) It is difficult to form a source / drain region in the lower semiconductor layer by self-alignment with the integrated surrounding gate electrode, and it has not been possible to improve the complexity of the manufacturing process and the deterioration of leakage characteristics.
(3) Since an integrally enclosed gate electrode type MIS field effect transistor having an equal channel length around the entire circumference of the semiconductor layer could not be formed, stable characteristics (driving current value and breakdown voltage between source / drain regions, etc.) It was difficult to obtain a MIS field effect transistor.
Such problems are becoming more prominent, and it is difficult to realize a three-dimensional CMOS that achieves higher speed and higher integration only by forming a MIS field effect transistor having a fine SOI structure with the current technology. That is.

The above-described problems include a semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate, a lower semiconductor layer selectively provided on the first interlayer insulating film, and the lower semiconductor layer. A second interlayer insulating film provided; an upper semiconductor layer selectively provided on the second interlayer insulating film; and a gate insulating film provided on the entire periphery of part of the lower and upper semiconductor layers. And an integrated surrounding gate electrode having a gate length all around which is provided in a structure surrounding a part of the lower and upper semiconductor layers via the gate insulating film, and the integrated surrounding gate electrode The one-conductivity type source region and the one-conductivity are provided so as to fill the remaining portion of the lower semiconductor layer in a self-aligned manner, and have an end portion having a plane perpendicular to the main surface of the semiconductor substrate. Type drain region and part of the lower semiconductor layer The channel region and the integrated surrounding gate electrode are self-aligned to fill the remaining portion of the upper semiconductor layer, and the end portion has a plane perpendicular to the main surface of the semiconductor substrate and is opposed to An opposite conductivity type source region and an opposite conductivity type drain region, a channel region provided in a part of the upper semiconductor layer, the integrated surrounding gate electrode, the one conductivity type source region, the one The semiconductor device according to the present invention includes a conductive drain region, a wiring provided in each of the opposite conductivity type source region and the opposite conductivity type drain region.
Here, the integrated surrounding gate electrode means that the surrounding gate electrode of the N-channel MIS field effect transistor and the surrounding gate electrode of the P-channel MIS field effect transistor which are stacked one above the other are integrated as a single surrounding gate electrode. It is a thing.

As described above, according to the present invention, an ordinary inexpensive semiconductor substrate is used, and the second semiconductor layer is formed on the semiconductor substrate via a plurality of insulating films using the selective epitaxial growth method of the semiconductor layer. A lower semiconductor layer composed of a pair of first semiconductor layers sandwiched from the left and right, a pair of second semiconductor layers sandwiched from the left and right via an insulating film directly above the lower semiconductor layer, and An upper semiconductor layer comprising a pair of first semiconductor layers sandwiching a pair of second semiconductor layers from the outside is provided, and a gate oxide film is formed around the lower second semiconductor layer and the upper third semiconductor layer An integrated (commonized) surrounding gate electrode (integrated surrounding gate electrode) is formed through each of which a channel region is formed, a p ⁺ type source / drain region is formed in the lower first semiconductor layer, and an upper layer is formed. n ⁺ -type source to the first semiconductor layer Since the p-channel and n-channel MIS field effect transistors having SOI structures in which the n-type source / drain regions are formed in the drain / drain region and the upper second semiconductor layer can be formed, the junction capacitance of the source / drain region is reduced (substantially zero). In addition, the threshold voltage can be reduced and the power can be reduced by reducing the depletion layer capacitance, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics.
In both the P-channel and N-channel MIS field effect transistors, the end portions of the source / drain regions (p ⁺ -type source / drain regions or n-type and n ⁺ -type source / drain regions) are respectively perpendicular to the main surface of the semiconductor substrate. Can be formed (a structure in which the source region of the rectangular parallelepiped structure and the drain region of the rectangular parallelepiped structure are opposed to each other with an equal distance). As a result, it is possible to achieve stability of the drive current value by high control of the threshold voltage.
Further, since a source / drain region (p ⁺ -type source / drain region or n-type and n ⁺ -type source / drain region) in which lateral impurity diffusion is suppressed can be formed, an integrated surrounding gate electrode and a source / drain region (p ⁺ -type source / drain region) Since the overlap with the drain region or the n-type source / drain region can be suppressed (substantially zero), it is possible to increase the speed by reducing the stray capacitance and to reduce the channel length, thereby reducing the size.
Also a connection to the p ⁺ -type source and drain regions formed in the lower semiconductor layer, the lower surface of the p ⁺ -type source and drain regions, formed from a lower layer wiring (WSi) via a conductive plug having a barrier metal (TiN), the upper layer the connection to the n ⁺ -type source and drain regions formed in the semiconductor layer, the upper surface of the n ⁺ -type source and drain regions, it is possible to form the upper wiring (Cu) through a conductive plug having a barrier metal (TiN), very high An integrated stacked CMOS can be obtained.
In addition, a source / drain region (p ⁺ -type source / drain region or n ⁺ and n ⁺ -type source / drain region) self-aligned with the integrated surrounding gate electrode can be formed without forming a sidewall on the integrated surrounding gate electrode. It is possible to simplify the manufacturing process.
Further, an integrated surrounding gate electrode provided via a gate oxide film allows a lower second semiconductor layer (channel region of a P-channel MIS field effect transistor) and an upper third semiconductor layer (N-channel MIS field effect). Transistor channel region) can be formed so that current paths other than the channel can be cut off, and back channel leakage can be prevented (a problem that must be overcome in order to achieve CMOS SOI). As well as being able to control the channel, the channel can be formed on four surfaces (upper and lower surfaces and two side surfaces in the channel width direction), so the channel width can be increased without increasing the surface (upper surface) occupying area. The current can be increased, and the speed can be further increased.
In addition, the MIS field-effect transistor components (low and high concentration source / drain regions, gate oxide films, integrated enclosure type) are self-aligned with the second lower semiconductor layer and the third upper semiconductor layer. It is also possible to form a fine gate electrode.
In addition, since the channel region can be formed only in the lower second semiconductor layer and the upper third semiconductor layer with good crystallinity without the influence of the underlying insulating film, a MIS field effect transistor having stable characteristics is formed. It is possible.
Also, a Si layer (lower second semiconductor layer or upper third semiconductor layer) having a small lattice constant is applied to a SiGe layer (lower first semiconductor layer or upper first and second layers) having a large lattice constant from the left and right. It is also possible to form a single crystal semiconductor layer having a structure sandwiched between semiconductor layers), and from left and right SiGe layers (lower first semiconductor layer or upper first and second semiconductor layers) to strained Si layers ( Since the lattice constant of the lower second semiconductor layer or the upper third semiconductor layer) can be increased, the carrier mobility can be increased, thereby further increasing the speed.
Also, wirings for connecting the drain regions of the N-channel and P-channel MIS field effect transistors necessary for the inverter circuit or the like to the same voltage are p ⁺ -type drain regions formed in the lower semiconductor layer and n ⁺ -type drains formed in the upper semiconductor layer. By providing a conductive plug surrounded by a barrier metal between regions, it is possible to form finely.
The source / drain region is formed with high concentration phosphorus instead of high concentration arsenic, and the channel length tends to be slightly shortened. However, the hot electron effect can be achieved without providing the second semiconductor layer and the low concentration source / drain region. It is also possible to form a short-channel N-channel MIS field effect transistor with improved characteristics.
In addition, the drain region can be formed in an LDD structure with improved hot electron effect, and the source region can be formed in a self-alignment with a high concentration source region structure in which there is no unnecessary low concentration region. It is also possible to form a higher-speed N-channel asymmetric MIS field effect transistor.
In other words, high-speed, high-reliability, high-performance, and high-speed, capable of manufacturing large-scale semiconductor integrated circuits that can handle high-speed and large-capacity communication devices, portable information terminals, various electronic mechanical devices, in-vehicle devices, space-related devices An extremely low power CMOS type semiconductor device having integration can be obtained.
The present inventor has the art, and named stacked CMOS having equal channel length and integral encircling the gate electrode on the insulating film (Accumulated CMOS with S ame C hannel L ength and S implified S urrounding G ate on insulator), This structure is abbreviated as SCLSSG.

Schematic side sectional view of the first embodiment of the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the first embodiment in the semiconductor device of the present invention (channel width direction, channel region portion) Schematic side sectional view of the first embodiment of the semiconductor device of the present invention (channel width direction, drain region portion) Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Schematic side sectional view of the second embodiment of the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the third embodiment of the semiconductor device of the present invention (channel length direction) Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Schematic side sectional view of the fourth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the fifth embodiment in the semiconductor device of the present invention (channel length direction) Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Schematic side sectional view of the sixth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of a conventional semiconductor device (channel length direction)

In particular, the present invention
(1) A first semiconductor of a lower semiconductor layer on a first interlayer insulating film by selective growth of an epitaxial semiconductor layer in a vertical (vertical) direction or a horizontal (horizontal) direction with a semiconductor substrate made of a complete single crystal as a nucleus. Formation of layer (part of SOI substrate).
(2) Formation of an activated one-conductivity type high-concentration impurity region that fills the lower first semiconductor layer.
(3) Formation of a second interlayer insulating film on the lower first semiconductor layer.
(4) By selectively growing a vertical (vertical) direction or a horizontal (horizontal) direction epitaxial semiconductor layer with the remaining vertical (vertical) direction epitaxial semiconductor layer as a nucleus, the upper semiconductor layer on the second interlayer insulating film is formed. Formation of a first semiconductor layer (a part of an SOI substrate).
(5) The vertical (vertical) direction epitaxial semiconductor layer is removed, and an insulating film is embedded to convert to an insulating region.
(6) Formation of an activated opposite conductivity type high concentration impurity region that fills the upper first semiconductor layer.
(7) Formation of an insulating film serving as a mask material on the upper first semiconductor layer.
(8) Opposition by separating the upper first semiconductor layer on which the insulating film serving as a mask material and the opposite-conductivity type high-concentration impurity region are formed by opening (anisotropic etching) for forming the surrounding gate electrode Formation of high concentration source region and high concentration drain region of conductivity type.
(9) Formation of a pair of gaps by side-surface minimal isotropic etching of the upper first semiconductor layer through the apertures.
(10) Formation of an upper second semiconductor layer filled with a low concentration impurity region of opposite conductivity type by lateral epitaxial growth between the remaining upper first semiconductor layers.
(11) The upper second semiconductor layer exposed in the opening portion, the insulating film around the upper second semiconductor layer, the lower first semiconductor layer, and the insulating film around the lower first semiconductor layer High conductivity of one conductivity type filled with a low concentration source region and a low concentration drain region of opposite conductivity type filled with an upper second semiconductor layer buried in a gap portion by anisotropic etching or a lower first semiconductor layer Formation of a concentration source region and a high concentration drain region.
(12) Formation of the upper third semiconductor layer or the lower second semiconductor layer by lateral epitaxial growth between the remaining upper second semiconductor layer or the lower first semiconductor layer. (Restoration of the removal layer semiconductor layer)
(13) Growth of a gate insulating film on the upper third semiconductor layer and the lower second semiconductor layer.
(14) Control of the threshold voltage of the upper third semiconductor layer or the lower second semiconductor layer.
(15) Formation of an integral surrounding gate electrode through a gate insulating film in the upper third semiconductor layer and the lower second semiconductor layer by flat filling of the opening.
Using technology such as
A lower semiconductor layer composed of first and second semiconductor layers is provided on a semiconductor substrate via a first interlayer insulating film composed of a plurality of layers, and the first semiconductor layer is disposed on the lower semiconductor layer via a second interlayer insulating film. A structure in which an upper semiconductor layer composed of the second and third semiconductor layers is provided and is self-aligned and is surrounded by a gate insulating film around the lower second semiconductor layer and the upper third semiconductor layer Is provided with an integrated surrounding gate electrode, self-aligned with the integrated surrounding gate electrode, and having a structure in which the opposite end portion forms a vertical plane with respect to the main surface of the semiconductor substrate. Lamination having one conductivity type source / drain region and an opposite conductivity type source / drain region having a structure in which an end facing the first and second semiconductor layers of the upper layer is perpendicular to the main surface of the semiconductor substrate N-channel and P-channel MIS electric field of structure It is obtained by forming a CMOS made of fruits transistor.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side sectional view are shown only on the main insulating film, and the wiring is drawn with a slight back-and-forth displacement, and the horizontal and vertical sizes are accurate to show the main part of the invention. The dimensions are not shown.
1 to 36 show a first embodiment of the semiconductor device of the present invention. FIG. 1 is a schematic side sectional view in the channel length direction, FIG. 2 is a schematic side sectional view in the channel width direction, and FIG. Is a schematic side cross-sectional view of the drain region in the channel width direction, and FIGS. 4 to 36 are process cross-sectional views of the manufacturing method.

1 to 3 show a part of a CMOS type semiconductor integrated circuit comprising a short channel N-channel and P-channel MIS field effect transistor using a silicon (Si) substrate and having a SCLSSG structure. A p-type silicon (Si) substrate of about ¹⁵ cm ⁻³ , 2 is a silicon oxide film (SiO ₂ ) of about 100 nm, 3 is a silicon nitride film (Si ₃ N ₄ ) of about 100 nm, and 4 is a silicon oxide of about 100 nm Films (SiO ₂ ), 5 is a silicon oxide film (SiO ₂ ) of an element isolation region of about 50 nm, 6 is a silicon oxide film (SiO ₂ ) of about 100 nm, and 7 is a silicon oxide film (SiO ₂ ) of an element isolation region of about 50 nm. _2), 8 lower wiring (WSi), the conductive plug 9 (W), 10 is 10nm approximately barrier metal (TiN), 11 1 ¹⁷ cm ^-3 of about n-type lateral (horizontal) direction epitaxial Si layer (first semiconductor layer of the lower layer, source and drain region formation portion) 12 of the n-type of about ¹⁰ 17 ^{cm -3} lateral (horizontal) direction epitaxial Si layer (second semiconductor layer of the lower layer, the channel region forming portion), ¹⁰ 20 ^{cm -3} of about ^{p +} -type drain region 13, 14 ¹⁰ 20 ^{cm -3} of about ^{p +} -type source region, 15 10 ¹⁷ cm ^-3 of about p-type lateral (horizontal) direction epitaxial Si layer (first semiconductor layer of the upper layer, the high-concentration source drain regions forming section), 16 about 5 × ¹⁰ 17 ^{cm -3} of n-type lateral (horizontal) direction epitaxial Si layer (second semiconductor layer of the upper layer, lightly doped source drain region formation portion) 17 of p-type of about ¹⁰ 17 ^{cm -3} lateral (horizontal) direction epitaxial Si layer (upper layer of Semiconductor layer ,, a channel region formed of 3), 18 ¹⁰ 20 ^{cm -3} of about ^{n +} -type drain region 19 is about 5 × ¹⁰ 17 ^{cm -3} of n-type drain region 20 is 5 × ¹⁰ 17 cm N − type source region of about ⁻³ , 21 is an n ⁺ type source region of about 10 ²⁰ cm ⁻³ , 22 is a gate oxide film (SiO ₂ ) of about 5 nm, 23 is an integrated unit of about 20 nm in length and about 100 nm in thickness. Surrounding gate electrode (WSi), 24 is a phosphosilicate glass (PSG) film of about 400 nm, 25 is a silicon nitride film (Si ₃ N ₄ ) of about 20 nm, 26 is a barrier metal (TiN) of about 10 nm, 27 is Conductive plug (W), 28 is about 500 nm insulating film (SiOC), 29 is about 10 nm barrier metal (TaN), 30 is about 500 nm Cu wiring (including Cu seed layer) , 31 indicates a barrier insulating film (Si ₃ N ₄ ) of about 20 nm.

In FIG. 1 (channel length direction), a silicon oxide film (SiO ₂ ) 2 is provided on a p-type silicon substrate 1, and a silicon nitride film (Si ₂ ) is selectively formed on the silicon oxide film (SiO ₂ ) 2. ₃ N ₄ ) 3 is provided, a silicon oxide film (SiO ₂ ) 4 is selectively provided on the silicon nitride film (Si ₃ N ₄ ) 3, and a silicon oxide film (SiO ₂ ) 4 is provided on the silicon oxide film (SiO ₂ ) 4. A lower semiconductor layer (11, 12) having a structure in which a pair of n-type Si layers 11 is provided and an n-type Si layer 12 is sandwiched between the opposing side surfaces of the pair of Si layers 11, The device isolation region is provided in an island shape by a silicon oxide film (SiO ₂ ) 5 and a buried silicon oxide film (SiO ₂ ) 7. A silicon oxide film (SiO ₂ ) 6 is provided on the lower semiconductor layers (11, 12), and a pair of p-type Si layers 15 are provided on the silicon oxide film (SiO ₂ ) 6. A pair of n-type Si layers 16 are provided so that one side surface is in contact between the opposing side surfaces of the Si layer 15, and a p-type Si layer 17 is provided between the opposing side surfaces of the pair of Si layers 16. The upper semiconductor layers (15, 16, 17) having the structure described above are provided so as to be separated into island shapes by an element isolation region / buried silicon oxide film (SiO ₂ ) 7. Surrounding each of the Si layer 12 and the Si layer 17 whose ends coincide with each other in the vertical direction, a surrounding gate electrode (WSi) 23 integrated (shared) via a gate oxide film (SiO ₂ ) 22 is silicon nitride. A p ⁺ -type drain region 13 or a p ⁺ -type source region 14 provided on the film (Si ₃ N ₄ ) 3 is filled with the Si layer 11 and the side surfaces are completely opposed to each other. The Si layer 12 is provided with a channel region having the same channel length on the entire periphery, and conductive plugs having a barrier metal (TiN) 10 on the lower surfaces of the p ⁺ type drain region 13 and the p ⁺ type source region 14, respectively. Lower layer wiring (WSi) 8 is connected through (W) 9 (barrier metal (TiN) 10 is a special structure existing only on the upper surface of conductive plug (W) 9). Field effect transistors are formed in the lower semiconductor layers (11, 12). On the other hand, the pair of Si layers 15 is provided with an n ⁺ -type drain region 18 or an n ⁺ -type source region 21 that is filled with the Si layer 15 and whose side surfaces are completely opposed to each other. filled layer 16, the side surface is completely opposite to that n-type drain region 19 or n-type source region 20 is provided, the Si layer 17 a channel region is provided with a total circumference equal channel length, n ⁺ -type An upper wiring (Cu) 30 having a barrier metal (TaN) 29 is connected to the upper surfaces of the drain region 18 and the n ⁺ -type source region 21 via a conductive plug (W) 27 having a barrier metal (TiN) 26. (The barrier metal (TiN) 26 is a conventional structure existing on the side surface and the lower surface of the conductive plug (W) 27) An N-channel MIS field effect transistor having an LDD structure. A jitter is formed in the upper semiconductor layer (15, 16, 17). (The manufacturing method will be described later, but in the present invention, an N-channel MIS field effect transistor having an LDD structure does not have a conventional sidewall (SiO ₂ ) on the side wall of the integral surrounding gate electrode. It has a special structure.) A cross-sectional side view in the channel length direction is shown in a stacked CMOS composed of P-channel and N-channel MIS field effect transistors.

In FIG. 2 (channel width direction, channel region portion), a silicon oxide film (SiO ₂ ) 2 is provided on a p-type silicon substrate 1, and a silicon nitride film (SiO ₂ ) 2 is formed on the silicon oxide film (SiO ₂ ) 2. Si ₃ N ₄ ) 3 is provided, and the silicon nitride film (Si ₃ N ₄ ) 3 is surrounded by an integrated surrounding gate electrode (WSi) 23 via a gate oxide film (SiO ₂ ) 22. The Si layer 12 (a part of the lower semiconductor layer) and the Si layer 17 (a part of the upper semiconductor layer) are provided, and the integrated surrounding gate electrode (WSi) 23 has a barrier metal (TiN). And a P-channel and N-channel MIS field effect transistor to which an upper layer wiring (Cu) 30 having a barrier metal (TaN) 29 is connected via a conductive plug (W) 27 having 26. In some layers CMOS, side cross-sectional view in the channel width direction of the channel region portion is shown.

In FIG. 3 (channel width direction, drain region portion), a silicon oxide film (SiO ₂ ) 2 is provided on a p-type silicon substrate 1, and silicon is selectively formed on the silicon oxide film (SiO ₂ ) 2. A nitride film (Si ₃ N ₄ ) 3 is provided, a silicon oxide film (SiO ₂ ) 4 is selectively provided on the silicon nitride film (Si ₃ N ₄ ) 3, and a silicon oxide film (SiO ₂ ) 4 On top of this, an n-type Si layer 11 forming a part of the lower semiconductor layer (11, 12) is selectively provided, and is isolated in an island shape by a silicon oxide film (SiO ₂ ) 5 in the element isolation region. . A silicon oxide film (SiO ₂ ) 6 is provided on the Si layer 11, and p-type Si forming a part of the upper semiconductor layer (15, 16, 17) on the silicon oxide film (SiO ₂ ) 6. The layer 15 is selectively provided, and is isolated in an island shape by a silicon oxide film (SiO ₂ ) 7 in the element isolation region. The Si layer 11, ^{p +} -type drain region 13 is provided which fills the Si layer 11 on the lower surface of the ^{p +} -type drain region 13, a conductive plug (W) 9 having a barrier metal (TiN) 10 The lower layer wiring (WSi) 8 is connected to the lower layer wiring (WSi) 8 via the conductive plug (W) 27 having the barrier metal (TiN) 26 and the upper layer wiring (TaN) 29 having the barrier metal (TaN) 29 ( Cu) 30 is connected. On the other hand, the Si layer 15, ^{n +} -type drain region 18 is provided which fills the Si layer 15 on the upper surface of the ^{n +} -type drain region 18, conductive plugs (W) 27 with a barrier metal (TiN) 26 An upper layer wiring (Cu) 30 having a barrier metal (TaN) 29 is connected through the via. A side sectional view in the channel width direction of the drain region is shown in a part of a stacked CMOS composed of P-channel and N-channel MIS field effect transistors.

Therefore, using a normal inexpensive semiconductor substrate and utilizing the selective epitaxial growth method of the semiconductor layer, a pair of first semiconductor layers sandwiching the second semiconductor layer from the left and right via a plurality of insulating films on the semiconductor substrate. A lower semiconductor layer made of a semiconductor layer is provided, and a pair of second semiconductor layers sandwiching the third semiconductor layer from the left and right via an insulating film directly above the lower semiconductor layer, and a pair of second semiconductor layers, respectively An upper semiconductor layer composed of a pair of first semiconductor layers sandwiched from the outside is provided, and is integrated (shared) around the lower second semiconductor layer and the upper third semiconductor layer via a gate oxide film The surrounding gate electrode (integrated surrounding gate electrode) is provided, each channel region is formed, ap ⁺ type source / drain region is formed in the lower first semiconductor layer, and n ⁺ type is formed in the upper first semiconductor layer. Source drain region and Since p-channel and n-channel MIS field effect transistors having SOI structures, each of which has an n-type source / drain region formed in the second semiconductor layer of the layer, a junction capacitance of the source / drain region can be reduced (substantially zero), a depletion layer It is possible to reduce the threshold voltage, lower power, etc. by reducing the capacitance, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics.
In both the P-channel and N-channel MIS field effect transistors, the end portions of the source / drain regions (p ⁺ -type source / drain regions or n-type and n ⁺ -type source / drain regions) are respectively perpendicular to the main surface of the semiconductor substrate. Can be formed (a structure in which the source region of the rectangular parallelepiped structure and the drain region of the rectangular parallelepiped structure are opposed to each other with an equal distance), so that the electric field concentration can be prevented and the breakdown voltage between the source and drain regions can be improved and the entire channel has the same channel length. As a result, it is possible to achieve stability of the drive current value by high control of the threshold voltage.
Further, since a source / drain region (p ⁺ -type source / drain region or n-type and n ⁺ -type source / drain region) in which lateral impurity diffusion is suppressed can be formed, an integrated surrounding gate electrode and a source / drain region (p ⁺ -type source / drain region) Since the overlap with the drain region or the n-type source / drain region can be suppressed (substantially zero), it is possible to increase the speed by reducing the stray capacitance and to reduce the channel length, thereby reducing the size.
Also a connection to the p ⁺ -type source and drain regions formed in the lower semiconductor layer, the lower surface of the p ⁺ -type source and drain regions, formed from a lower layer wiring (WSi) via a conductive plug having a barrier metal (TiN), the upper layer the connection to the n ⁺ -type source and drain regions formed in the semiconductor layer, the upper surface of the n ⁺ -type source and drain regions, it is possible to form the upper wiring (Cu) through a conductive plug having a barrier metal (TiN), very high An integrated stacked CMOS can be obtained.
In addition, a source / drain region (p ⁺ -type source / drain region or n ⁺ and n ⁺ -type source / drain region) self-aligned with the integrated surrounding gate electrode can be formed without forming a sidewall on the integrated surrounding gate electrode. It is possible to simplify the manufacturing process.
Further, an integrated surrounding gate electrode provided via a gate oxide film allows a lower second semiconductor layer (channel region of a P-channel MIS field effect transistor) and an upper third semiconductor layer (N-channel MIS field effect). Transistor channel region) can be formed so that current paths other than the channel can be cut off, and back channel leakage can be prevented (a problem that must be overcome in order to achieve CMOS SOI). As well as being able to control the channel, the channel can be formed on four surfaces (upper and lower surfaces and two side surfaces in the channel width direction), so the channel width can be increased without increasing the surface (upper surface) occupying area. The current can be increased, and the speed can be further increased.
In addition, the MIS field-effect transistor components (low and high concentration source / drain regions, gate oxide films, integrated enclosure type) are self-aligned with the second lower semiconductor layer and the third upper semiconductor layer. It is also possible to form a fine gate electrode.
In addition, since the channel region can be formed only in the lower second semiconductor layer and the upper third semiconductor layer with good crystallinity without the influence of the underlying insulating film, a MIS field effect transistor having stable characteristics is formed. It is possible.
In other words, high-speed, high-reliability, high-performance, and high-speed, capable of manufacturing large-scale semiconductor integrated circuits that can handle high-speed and large-capacity communication devices, portable information terminals, various electronic mechanical devices, in-vehicle devices, space-related devices An extremely low power CMOS type semiconductor device having integration can be obtained.

  Next, the manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 4 to 36 and FIGS. 1 to 3 mainly using the schematic side sectional view showing the channel length direction. However, here, only the manufacturing method relating to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.

Fig. 4 (channel length direction)
A silicon oxide film (SiO ₂ ) 2 of about 100 nm is grown on the p-type silicon substrate 1 by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 3 is grown to about 100 nm by chemical vapor deposition.

Figure 5 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 3 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. Next, the resist (not shown) is removed.

Fig. 6 (channel length direction)
Next, a tungsten silicide film (WSi) 8 of about 100 nm is grown by sputtering. Next, chemical mechanical polishing (hereinafter abbreviated as CMP) is performed, and the tungsten silicide film (WSi) 8 grown on the silicon nitride film (Si ₃ N ₄ ) 3 is removed to form a tungsten silicide serving as a lower layer wiring (WSi). A film (WSi) 8 is buried flat in the opening.

Fig. 7 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 4 of about 100 nm is grown by chemical vapor deposition.

Fig. 8 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon oxide film (SiO ₂ ) 4 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. Next, the resist (not shown) is removed. Next, a tungsten film (W) 9 of about 100 nm is grown by chemical vapor deposition. Next, the tungsten film (W) 9 grown on the silicon oxide film (SiO ₂ ) 4 is subjected to chemical mechanical polishing (CMP) to bury the tungsten film (W) 9 flatly in the opening.

Figure 9 (channel length direction)
Next, the tungsten film (W) 9 is subjected to anisotropic dry etching by about 10 nm to form a minute opening. Next, a titanium nitride film (TiN) 10 serving as a barrier metal of about 10 nm is grown by chemical vapor deposition. Next, the titanium nitride film (TiN) 10 grown on the silicon oxide film (SiO ₂ ) 4 is subjected to chemical mechanical polishing (CMP), and the titanium nitride film (TiN) 10 is embedded in the opening portion flatly. In this way, a conductive plug (W) 9 having a barrier metal (TiN) 10 on top is formed on the lower layer wiring (WSi) 8.

Figure 10 (channel length direction)
Next, a silicon nitride film (Si ₃ N ₄ ) 32 is grown to about 50 nm by chemical vapor deposition.

FIG. 11 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 32, a silicon oxide film (SiO ₂ ) 4, a silicon nitride film (Si ₃ N ₄ ) 3 and silicon oxide film (SiO ₂ ) 2 are sequentially subjected to anisotropic dry etching to form an opening. (The opening width is about 100 nm) Next, the resist (not shown) is removed.

Figure 12 (channel length direction)
Next, an n-type longitudinal (vertical) epitaxial Si layer 33 is grown on the exposed p-type silicon substrate 1. Next, chemical mechanical polishing (CMP) is performed to planarize the vertical (vertical) epitaxial Si layer 33 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 32. Next, a tungsten film (W) 34 of about 50 nm is grown by selective chemical vapor deposition.

FIG. 13 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 32 is anisotropically dry etched using the resist (not shown) and the tungsten film (W) 34 as a mask layer, and opened. A hole is formed. Next, the resist (not shown) is removed.

Fig. 14 (channel length direction)
Next, an n-type lateral (horizontal) direction epitaxial Si layer 11 is grown on the exposed side surface of the longitudinal (vertical) direction epitaxial Si layer 33 and a hole portion of the silicon nitride film (Si ₃ N ₄ ) 32 is buried.

FIG. 15 (channel length direction)
Next, the exposed tungsten film (W) 34 and silicon nitride film (Si ₃ N ₄ ) 32 are sequentially subjected to anisotropic dry etching to form an opening.

FIG. 16 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 5 of about 50 nm is grown by chemical vapor deposition. Next, the silicon oxide film (SiO ₂ ) 5 grown on the Si layer 11 and the Si layer 33 is subjected to chemical mechanical polishing (CMP), and the silicon oxide film (SiO ₂ ) 5 is flatly embedded in the opening portion to obtain an element isolation region. Form.

FIG. 17 (channel length direction)
Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, boron ions are implanted into the Si layer 11. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. (Here, a heat treatment step for activation and depth control of ion-implanted boron is not performed, but the p ⁺ -type impurity region 35 is illustrated.)

FIG. 18 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 6 of about 100 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 36 of about 50 nm is grown by chemical vapor deposition.

FIG. 19 (channel length direction)
Next, using an ordinary lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 36 and the silicon oxide film (SiO ₂ ) 6 are sequentially anisotropic dry etched using a resist (not shown) as a mask layer. Then, an opening that exposes the upper surface of the Si layer 33 is formed. Next, the resist (not shown) is removed.

FIG. 20 (channel length direction)
Next, a p-type longitudinal (vertical) epitaxial Si layer 37 is grown on the exposed Si layer 33. Next, chemical mechanical polishing (CMP) is performed to planarize the vertical (vertical) epitaxial Si layer 37 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 36. Next, a tungsten film (W) 38 of about 50 nm is grown by selective chemical vapor deposition.

FIG. 21 (channel length direction)
Next, the silicon nitride film (Si ₃ N ₄ ) 36 is anisotropically dry-etched and opened using a resist (not shown) and the tungsten film (W) 38 as a mask layer using a normal lithography technique using an exposure drawing apparatus. A hole is formed. Next, the resist (not shown) is removed.

FIG. 22 (channel length direction)
Next, a p-type lateral (horizontal) direction epitaxial Si layer 15 is grown on the exposed side surface of the longitudinal (vertical) direction epitaxial Si layer 37 to fill the opening of the silicon nitride film (Si ₃ N ₄ ) 36.

FIG. 23 (channel length direction)
Next, the surface of the lateral (horizontal) epitaxial Si layer 15 is thermally oxidized at about 900 ° C. to grow a silicon oxide film (SiO ₂ ) 39 of about 10 nm.

FIG. 24 (channel length direction)
Next, using the thermally oxidized silicon oxide film (SiO ₂ ) 39 as a mask layer, the tungsten film (W) 38, the longitudinal (vertical) direction epitaxial Si layer 37, the longitudinal (vertical) direction epitaxial Si layer 33, and the silicon nitride film (Si ₃₎ N ₄ ) 36 is sequentially subjected to anisotropic dry etching to form an opening.

FIG. 25 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 7 of about 60 nm is grown by chemical vapor deposition. Next, the silicon oxide film (SiO ₂ ) 7 and the silicon oxide film (SiO ₂ ) 39 above the flat surface of the lateral (horizontal) epitaxial Si layer 15 are chemically mechanically polished (CMP) to obtain a silicon oxide film (SiO ₂ ). 7 is embedded in the opening portion flatly to form an element isolation region.

FIG. 26 (channel length direction)
Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, arsenic ions are implanted into the Si layer 15. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, annealing is performed at about 900 ° C. to form a p ⁺ -type impurity region 35 filling the Si layer 11 and an n ⁺ -type impurity region 40 filling the Si layer 15.

FIG. 27 (channel length direction)
Next, a silicon nitride film (Si ₃ N ₄ ) 41 of about 100 nm is grown by chemical vapor deposition.

FIG. 28 (channel length direction)
Next, the silicon nitride film (Si ₃ N ₄ ) 41 and the Si layer 15 are sequentially anisotropically dry-etched using a resist (not shown) as a mask layer by using a normal lithography technique using an exposure drawing apparatus. Subsequently, the Si layer 15 is isotropically dry-etched by about 15 nm in the lateral (horizontal) direction. At this time, the n ⁺ -type impurity region 40 is divided into an n ⁺ -type drain region 18 and an n ⁺ -type source region 21. Next, the resist (not shown) is removed.

FIG. 29 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial Si layer 16 in which phosphorus of about 5 × 10 ¹⁷ cm ⁻³ is filled between the side surfaces of the exposed lateral (horizontal) epitaxial Si layer 15 is grown.

FIG. 30 (channel length direction)
Next, using the silicon nitride film (Si ₃ N ₄ ) 41 as a mask layer, the Si layer 16, the silicon oxide film (SiO ₂ ) 7 (existing on both sides of the Si layer 16), the silicon oxide film (SiO ₂ ) 6, and the Si layer 11, silicon oxide film (SiO ₂ ) 5 (existing on both sides of Si layer 11) and silicon oxide film (SiO ₂ ) 4 are selectively and sequentially subjected to anisotropic dry etching to form silicon nitride film (Si ₃ N ₄ ) An opening is formed to expose a part of 3. At this time, the p ⁺ -type impurity region 35 is divided into a p ⁺ -type drain region 13 and a p ⁺ -type source region 14, and an n-type lateral (horizontal) direction filled with phosphorus of about 5 × 10 ¹⁷ cm ^−3. The epitaxial Si layer 16 is divided into an n-type drain region 19 and an n-type source region 20.

Figure 31 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial Si layer 12 or an n-type lateral (horizontal) epitaxial Si layer 17 is simultaneously grown between the exposed side surfaces of the Si layer 11 or the Si layer 16, respectively, and is partially formed below. A lower semiconductor layer (11, 12) and an upper semiconductor layer (15, 16, 17) having holes are formed. (At this time, a single crystal silicon layer having no influence of the base is formed immediately above the holes.)

Figure 32 (channel length direction)
Next, the entire periphery of the exposed Si layer 12 and Si layer 17 is oxidized to grow a gate oxide film (SiO ₂ ) 22 of about 5 nm. Next, boron ions for controlling the threshold voltage are implanted into the Si layer 12 at an acceleration voltage of about 25 kev that penetrates the Si layer 17. (The concentration of the n-type Si layer 12 is lowered.) Next, boron ions for threshold voltage control are implanted into the Si layer 17 at an acceleration voltage of about 10 kev. (The n-type Si layer 17 is inverted to the p-type.) Next, by chemical vapor deposition, the open portions left over the entire surface including the entire periphery of each gate oxide film (SiO ₂ ) 22 are completely embedded. A tungsten silicide film (WSi) of about 100 nm is grown. Next, chemical mechanical polishing (CMP) is performed, and the tungsten silicide film (WSi) grown on the silicon nitride film (Si ₃ N ₄ ) 41 is removed and planarized. In this way, an integrated (commonized) surrounding gate electrode (WSi) 23 embedded flatly in the opening is formed. Next, annealing is performed at about 800 ° C. to activate the channel region.

FIG. 33 (channel length direction)
Next, the silicon nitride film (Si ₃ N ₄ ) 41 is removed by etching.

FIG. 34 (channel length direction)
Next, a PSG film 24 of about 400 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, a silicon nitride film (Si ₃ N ₄ ) 25 of about 20 nm is grown by chemical vapor deposition.

FIG. 35 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 25, a PSG film 24 and a silicon oxide film (SiO ₂ ) (4-7) Then, the portions connected to the lower layer wiring 8) are sequentially anisotropic dry etched to form vias. Next, the resist (not shown) is removed.

FIG. 36 (channel length direction)
Next, a TiN film 26 which becomes a barrier metal of about 10 nm is grown by chemical vapor deposition. Next, a tungsten film (W) 27 is grown by chemical vapor deposition. Next, a conductive plug (W) 27 having a barrier metal (TiN) 26 buried in the via is formed by chemical mechanical polishing (CMP).

FIG. 1 (channel length direction) FIG. 2 (channel width direction, channel region portion) and FIG. 3 (channel width direction, drain region portion)
Next, an insulating film (SiOC) 28 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the SiOC film 28 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 25 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 29 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded in the opening portion flatly, and a Cu wiring 30 having a barrier metal (TaN) 29 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 31 serving as a Cu barrier insulating film is grown by chemical vapor deposition to complete the SCLSSG structure semiconductor device of the present invention.

FIG. 37 (channel length direction) is a schematic cross-sectional side view of the second embodiment of the semiconductor device of the present invention. The short channel N-channel and P-channel MIS electric fields formed in the SCLSSG structure using a silicon (Si) substrate. 1 shows a part of a CMOS type semiconductor integrated circuit including an effect transistor, wherein 1 to 10, 13, 14, and 18 to 31 are the same as those in FIG. 1, and 42 is an n-type lateral (horizontal) direction epitaxial SiGe layer ( Lower first semiconductor layer, source / drain region forming portion) 43 is an n-type lateral (horizontal) epitaxial strained Si layer (lower second semiconductor layer, channel region forming portion), 44 is a p-type lateral. (Horizontal) direction epitaxial SiGe layer (upper first semiconductor layer, high-concentration source / drain region forming portion), 45 is an n-type lateral (horizontal) direction epitaxial SiGe layer (upper layer) The second semiconductor layer, lightly doped source drain region formation portion) of, 46 denotes a p-type lateral (horizontal) direction epitaxial strained Si layer (third semiconductor layer of the upper layer, the channel region forming unit).
In the figure, the lower semiconductor layer has a structure in which an n-type strained Si layer is sandwiched between a pair of n-type SiGe layers, and the upper semiconductor layer is a p-type strained Si layer between a pair of n-type SiGe layers. Is formed, and a semiconductor device having substantially the same structure as that of FIG. 1 is formed except that a pair of p-type SiGe layers are provided at both ends.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, a Si layer having a small lattice constant is sandwiched between SiGe layers having a large lattice constant from the left and right. Since a single crystal semiconductor layer can be formed, the lattice constant of the strained Si layer can be increased from the left and right SiGe layers, and the carrier mobility can be increased, thereby further increasing the speed.

FIG. 38 (channel length direction) is a schematic cross-sectional side view of the third embodiment of the semiconductor device of the present invention. The short channel N-channel and P-channel MIS electric fields formed in the SCLSSG structure using a silicon (Si) substrate. 1 shows a part of a CMOS type semiconductor integrated circuit including an effect transistor, wherein 1-31 are the same as those in FIG. 1, 47 is a barrier metal (TiN), 48 is a conductive plug (W), and 49 is a barrier metal (TiN). ).
In the figure, the connection to the p ⁺ type drain region 13 is not formed from the lower layer wiring (WSi) 8, and a barrier that directly connects the upper surface of the p ⁺ type drain region 13 and the lower surface of the n ⁺ type drain region 18. A semiconductor device having substantially the same structure as that of FIG. 1 is formed except that the conductive plug (W) surrounded by the metal (TiN) (47, 49) is formed as a common drain region.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method becomes somewhat complicated, but the degree of freedom of wiring can be increased, and higher integration can be achieved in an inverter circuit or the like. .

  Next, a manufacturing method of the third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 39 to 43 and FIG. However, here, only the manufacturing method relating to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.

  After the steps of FIGS. 4 to 17 shown in the first embodiment are performed, the steps of FIGS. 39 to 43 are performed.

FIG. 39 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 6 of about 100 nm is grown by chemical vapor deposition.

FIG. 40 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon oxide film (SiO ₂ ) 6 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. Next, the resist (not shown) is removed.

FIG. 41 (channel length direction)
Next, a titanium nitride film (TiN) 47 serving as a barrier metal of about 10 nm is grown by chemical vapor deposition. Next, a tungsten film (W) 48 of about 90 nm is grown by chemical vapor deposition. Next, the titanium nitride film (TiN) 47 and the tungsten film (W) 48 grown on the silicon oxide film (SiO ₂ ) 6 are subjected to chemical mechanical polishing (CMP) to obtain the titanium nitride film (TiN) 47 and the tungsten film (W). 48 is embedded flat in the opening.

Fig. 42 (channel length direction)
Next, the tungsten film (W) 48 is subjected to anisotropic dry etching by about 10 nm to form a minute opening. Next, a titanium nitride film (TiN) 49 serving as a barrier metal of about 10 nm is grown by chemical vapor deposition. Next, the titanium nitride film (TiN) 49 grown on the silicon oxide film (SiO ₂ ) 6 is subjected to chemical mechanical polishing (CMP), and the titanium nitride film (TiN) 49 is embedded in the opening portion flatly to form a titanium nitride film ( A conductive plug (W) 48 surrounded by (TiN) (47, 49) is formed.

Fig. 43 (channel length direction)
Next, a silicon nitride film (Si ₃ N ₄ ) 36 of about 50 nm is grown by chemical vapor deposition.

  Thereafter, the steps of FIGS. 19 to 36 and FIG. 1 shown in the first embodiment are performed to complete the SCLSSG structure semiconductor device of the present invention. (Completed drawing, Fig. 38 (channel length direction))

FIG. 44 (channel length direction) is a schematic sectional side view of the fourth embodiment of the semiconductor device of the present invention. The short channel N-channel and P-channel MIS electric fields formed in the SCLSSG structure using a silicon (Si) substrate. A part of a CMOS type semiconductor integrated circuit including an effect transistor is shown, and 1 to 15, 17, 18, 21 to 31 are the same as those in FIG.
In the figure, the upper second semiconductor layer 16 is not provided, and the n ⁺ -type drain region 18 and the n ⁺ -type source region 21 can be high-concentration phosphorus (gradient junction in which the impurity distribution changes gradually). 1 and the semiconductor device having substantially the same structure as that of FIG. 1 is formed except that the n-type drain region 19 and the n-type source region 20 are not provided.
In this embodiment, the same effect as in the first embodiment can be obtained, and although the channel length tends to be slightly short, a short channel in which the hot electron effect is improved without providing a low concentration source / drain region. Since the N-channel MIS field-effect transistor can be formed, the miniaturization and the manufacturing process can be simplified.

FIG. 45 (channel length direction) is a schematic cross-sectional side view of the fifth embodiment of the semiconductor device of the present invention. The short channel N-channel and P-channel MIS electric fields formed in the SCLSSG structure using a silicon (Si) substrate. 1 shows a part of a CMOS type semiconductor integrated circuit including an effect transistor, and reference numerals 1 to 19 and 21 to 31 denote the same components as those in FIG.
In the figure, a semiconductor device having substantially the same structure as that of FIG. 1 is formed except that the upper second semiconductor layer 16 is not provided on the source region side and the n-type source region 20 is not provided. Yes. (The N channel side is formed in an asymmetric MIS field effect transistor.)
In this embodiment, the same effect as that of the first embodiment can be obtained. Further, the drain region can be formed in an LDD structure with improved hot electron effect, and the source region has no unnecessary low concentration region. Since it can be formed in a self-aligned manner with the concentration source region structure, it is possible to increase the speed by reducing the resistance of the source region.

Next, a manufacturing method of the fifth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 46 to 50 and FIG.
After the steps of FIGS. 4 to 27 shown in the first embodiment are performed, the step of FIG. 46 is performed.

FIG. 46 (channel length direction)
Next, the silicon nitride film (Si ₃ N ₄ ) 41 and the Si layer 15 are sequentially anisotropically dry-etched using a resist (not shown) as a mask layer by using a normal lithography technique using an exposure drawing apparatus. At this time, the n ⁺ -type impurity region 40 is divided into an n ⁺ -type drain region 18 and an n ⁺ -type source region 21. Next, the resist (not shown) is removed.

FIG. 47 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the resist layer (not shown) is used as a mask layer, and the Si layer 15 in the drain region where the side surface is exposed in the opening is subjected to isotropic dry etching by about 15 nm. A minute aperture is formed in the (horizontal) direction. Next, the resist (not shown) is removed.

FIG. 48 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial Si layer 16 is grown between the exposed side surfaces of the Si layer 15 by an ECR plasma CVD apparatus capable of low-temperature growth (500 ° C. or less). (The n-type impurity region 29 having a phosphorus concentration of about 5 × 10 ¹⁷ cm ⁻³ is filled.)

FIG. 49 (channel length direction)
Next, using the silicon nitride film (Si ₃ N ₄ ) 41 as a mask layer, the Si layer 16, the silicon oxide film (SiO ₂ ) 7 (existing on both sides of the Si layer 16), the silicon oxide film (SiO ₂ ) 6, and the Si layer 11, silicon oxide film (SiO ₂ ) 5 (existing on both sides of Si layer 11) and silicon oxide film (SiO ₂ ) 4 are selectively and sequentially subjected to anisotropic dry etching to form silicon nitride film (Si ₃ N ₄ ) An opening is formed to expose a part of 3. At this time, the p ⁺ -type impurity region 35 is divided into a p ⁺ -type drain region 13 and a p ⁺ -type source region 14, and an n-type lateral (horizontal) direction filled with phosphorus of about 5 × 10 ¹⁷ cm ^−3. Only the n-type drain region 19 is formed in the epitaxial Si layer 16.

Figure 50 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial Si layer 12 is formed between the exposed side surfaces of the Si layer 11 or between the side surfaces of the Si layer 16 and the Si layer 15 by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less). Alternatively, an n-type lateral (horizontal) epitaxial Si layer 17 is grown at the same time to form a lower semiconductor layer (11, 12) and an upper semiconductor layer (15, 16, 17) having vacancies in a part of the lower part. (At this time, a single crystal silicon layer having no influence of the base is formed immediately above the holes.)

  Next, the steps of FIGS. 32 to 36 and FIG. 1 shown in the first embodiment are performed to complete the SCLSSG structure semiconductor device of the present invention. (An asymmetric MIS field effect transistor is formed on the N channel side.) (Completed drawing, FIG. 45 (channel length direction))

FIG. 51 (channel width direction) is a schematic sectional side view of the sixth embodiment of the semiconductor device of the present invention. The short channel N channel and P channel MIS electric fields formed in the SCLSSG structure using a silicon (Si) substrate. A part of a CMOS type semiconductor integrated circuit including an effect transistor is shown, and 1, 3 to 7, 11 to 31 are the same as those in FIG.
In the drawing, the conductive plug (W) 9 having the silicon oxide film (SiO ₂ ) 2, the lower layer wiring (WSi) 8 and the lower layer barrier metal (TiN) 10 is not formed, and the p ⁺ type drain region 13 is not formed. 1 except that it is connected to the upper layer wiring (Cu) having the barrier metal (TaN) 29 via the conductive plug (W) 27 having the barrier metal (TiN) 26 on the upper surface of the p ⁺ type source region 14. A semiconductor device having almost the same structure is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and although there is some difficulty in high integration, the manufacturing process can be simplified.

In the above embodiment, chemical vapor deposition is used when growing the semiconductor layer. However, the present invention is not limited to this, and molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) is also used. Alternatively, atomic layer crystal growth (ALE) or any other crystal growth method may be used.
In the fourth embodiment, a CMOS type semiconductor integrated circuit is formed in which a P-channel MIS field effect transistor is formed in the lower semiconductor layer and an N-channel MIS field effect transistor is formed in the upper semiconductor layer. May be formed.
The gate electrode, the gate oxide film, the barrier metal, the conductive plug, the wiring, the insulating film, and the like are not limited to the above embodiments, and any material may be used as long as it has the same characteristics.
In addition, although all of the above embodiments describe the case where an enhancement type MIS field effect transistor is formed, a depletion type MIS field effect transistor may be formed. In this case, an epitaxial semiconductor layer having the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing an epitaxial semiconductor layer and then ion-implanting an impurity of the opposite conductivity type to convert the conductivity type. A MIS field effect transistor may be formed.
In the above-described embodiment, the case where a two-layer SOI substrate is formed is described. However, even when a four-layer or more SOI substrate is formed, if the present invention is used, manufacturing is easy.
In the above embodiment, the CMOS type semiconductor integrated circuit is formed in which the MIS field effect transistors of different conductivity types are formed in the upper and lower semiconductor layers, respectively. However, when the MIS field effect transistors of the same conductivity type are formed. It can also be used.

The present invention is particularly aimed at a semiconductor device with extremely high integration, high speed, and high reliability. However, the present invention is not limited to high speed and can be used for all CMOS type semiconductor integrated circuits.
In addition to the MIS field effect transistor, there is a possibility that it can be used for a semiconductor integrated circuit composed of other field effect transistors.

1 p-type silicon (Si) substrate 2 silicon oxide film (SiO ₂ )
3 Silicon nitride film (Si ₃ N ₄ )
4 Silicon oxide film (SiO ₂ )
5 Silicon oxide film (SiO ₂ ) in element isolation region
6 Silicon oxide film (SiO ₂ )
7 Silicon oxide film (SiO ₂ ) in element isolation region
8 Lower layer wiring (WSi)
9 Conductive plug (W)
10 Barrier metal (TiN)
11 n-type lateral (horizontal) direction epitaxial Si layer (lower first semiconductor layer, source / drain region forming portion)
12 n-type lateral (horizontal) epitaxial Si layer (lower second semiconductor layer, channel region forming portion)
13 p ⁺ type drain region 14 p ⁺ type source region 15 p type lateral (horizontal) direction epitaxial Si layer (upper first semiconductor layer, high concentration source / drain region forming part)
16 n-type lateral (horizontal) direction epitaxial Si layer (upper second semiconductor layer, low concentration source / drain region forming portion)
17 p-type lateral (horizontal) epitaxial Si layer (upper third semiconductor layer, channel region forming portion)
18 n ⁺ type drain region 19 n type drain region 20 n type source region 21 n ⁺ type source region 22 Gate oxide film (SiO ₂ )
23 Integrated Surround Gate Electrode (WSi)
24 Phosphorsilicate glass (PSG) film 25 Silicon nitride film (Si ₃ N ₄ )
26 Barrier metal (TiN)
27 Conductive plug (W)
28 SiOC film 29 Barrier metal (TaN)
30 Cu wiring (including Cu seed layer)
31 Barrier insulating film (Si ₃ N ₄ )
32 Silicon nitride film (Si ₃ N ₄ )
33 n-type vertical (vertical) epitaxial Si layer 34 selective chemical vapor deposition conductive film (W)
35 p ⁺ type impurity region 36 Silicon nitride film (Si ₃ N ₄ )
37 p-type vertical (vertical) epitaxial Si layer 38 selective chemical vapor deposition conductive film (W)
39 Silicon oxide film (SiO ₂ )
40 n ⁺ type impurity region 41 Silicon nitride film (Si ₃ N ₄ )
42 n-type lateral (horizontal) epitaxial SiGe layer (lower first semiconductor layer, source / drain region forming portion)
43 n-type lateral (horizontal) direction epitaxial strained Si layer (lower second semiconductor layer, channel region forming portion)
44 p-type lateral (horizontal) direction epitaxial SiGe layer (upper first semiconductor layer, high concentration source / drain region forming portion)
45 n-type lateral (horizontal) direction epitaxial SiGe layer (upper second semiconductor layer, low concentration source / drain region forming portion)
46 p-type lateral (horizontal) epitaxial strained Si layer (upper third semiconductor layer, channel region forming portion)
47 Barrier metal (TiN)
48 Conductive plug (W)
49 Barrier metal (TiN)

Claims (5)

  A semiconductor substrate; a first interlayer insulating film provided on the semiconductor substrate; a lower semiconductor layer selectively provided on the first interlayer insulating film; and a first semiconductor layer provided on the lower semiconductor layer Two interlayer insulating films, an upper semiconductor layer selectively provided on the second interlayer insulating film, a gate insulating film provided all around the lower layer and the upper semiconductor layer, and the gate An integrated surrounding gate electrode having an equal gate length around the entire periphery, provided in a structure surrounding a part of the lower and upper semiconductor layers via an insulating film, and self-aligning with the integrated surrounding gate electrode And filling the remaining portion of the lower semiconductor layer, the end portion having a plane perpendicular to the main surface of the semiconductor substrate, and the one conductivity type source region and the one conductivity type drain region provided opposite to each other, A channel provided in a part of the lower semiconductor layer. A region and the integrated surrounding gate electrode are self-aligned to fill the remaining portion of the upper semiconductor layer, and the end portion has a plane perpendicular to the main surface of the semiconductor substrate, and is provided opposite to it. The opposite conductivity type source region and the opposite conductivity type drain region, the channel region provided in a part of the upper semiconductor layer, the integrated surrounding gate electrode, the one conductivity type source region, and the one conductivity type drain And a wiring provided in each of the regions, the opposite conductivity type source region, and the opposite conductivity type drain region.   The lower semiconductor layer includes two semiconductor layers: a first semiconductor layer provided with the one-conductivity type source region and the one-conductivity type drain region, and a second semiconductor layer provided with the channel region. The upper semiconductor layer includes a first semiconductor layer provided with an opposite conductivity type high concentration source region and an opposite conductivity type high concentration drain region, and an opposite conductivity type low concentration source region and an opposite conductivity type low concentration drain region. 2. The semiconductor device according to claim 1, comprising three semiconductor layers, a second semiconductor layer provided and a third semiconductor layer provided with the channel region.   A lower layer wiring is connected to the lower surface of the one-conductivity type source region and the one-conductivity type drain region provided in the lower semiconductor layer through a conductive plug having a barrier metal, and the lower semiconductor layer is provided in the upper semiconductor layer. 2. The semiconductor device according to claim 1, wherein an upper layer wiring is connected to upper surfaces of the one-conduction type source region and the one-conduction type drain region through a conductive plug having a barrier metal.   The lattice constant of the first semiconductor layer of the lower semiconductor layer is larger than the lattice constant of the second semiconductor layer of the lower semiconductor layer, and the lattice constants of the first and second semiconductor layers of the upper semiconductor layer are The semiconductor device according to claim 2, wherein the semiconductor device is larger than a lattice constant of the third semiconductor layer of the upper semiconductor layer.   A lower semiconductor layer that is selectively provided on a semiconductor substrate via an insulating film and is filled with one conductivity type impurity region, and an upper semiconductor layer that is filled with an opposite conductivity type impurity region via the insulating film on the lower semiconductor layer In the semiconductor device in which a layer is selectively provided and a film serving as a mask material is provided on the upper semiconductor layer, the mask material film, a part of the upper semiconductor layer, and a part of the upper semiconductor layer An upper semiconductor separated into left and right by selectively anisotropically etching an insulating film, a part of the lower semiconductor layer, and an insulating film around a part of the lower semiconductor layer in order to form an opening. In the layer, the end portion forms a vertical plane with respect to the main surface of the semiconductor substrate, and the opposite opposite conductivity type source region or opposite conductivity type drain region is formed. For the main surface of the semiconductor substrate By forming a one-conductivity type source region or a one-conductivity type drain region facing each other and forming a perpendicular plane, lateral (horizontal) direction epitaxial semiconductor layers are grown between the exposed upper and lower semiconductor layers, respectively. The lower semiconductor layer and the upper semiconductor layer are restored, and a gate insulating film is grown on the restored portion of the lower semiconductor layer and the upper semiconductor layer, and then the integrated surrounding electrode is flattened in the opening portion. By embedding, the integrated surrounding electrode, the opposite conductivity type source region, the opposite conductivity type drain region, the one conductivity type source region, and the one conductivity type drain region are formed in a self-aligned manner. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: