JP6125802B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having a structure of SOI (in the present invention, it means a semiconductor on insulator in a broad sense and does not mean a silicon on insulator in a narrow sense). The present invention relates to forming a CMOS type semiconductor integrated circuit composed of N-channel and P-channel MIS field effect transistors with increased mobility of electrons and holes.

49 shows a CMOS NOT circuit (inverter), FIG. 50 shows a CMOS 2-input NAND circuit, and FIG. 51 shows a CMOS 2-input NOR circuit. FIG. 52 is a schematic side cross-sectional view of a conventional semiconductor device. In order to form the representative logic circuit, an N channel and a P channel having a strained SOI structure formed by using a SIMOX (Separation by Implanted Oxygen) method. A part of a CMOS type semiconductor integrated circuit made up of MIS field effect transistors is shown (however, another pair is required to construct a two-input NAND circuit and a two-input NOR circuit), 61 is a p-type Si substrate , 62 is a p-type SiGe layer, 63 is an n-type SiGe layer, 64 is a buried silicon oxide film (SiO ₂ ), 65 is an element isolation region (SiO ₂ ), 66 is a p-type strained Si layer, and 67 is n Type strained Si layer, 68 is an n ⁺ type source region, 69 is an n type source region, 70 is an n type drain region, 71 is an n ⁺ type drain region, 72 is a p ⁺ type drain region, 73 is a p ⁺ type source region, 74 is a gate oxide film, 75 is a gate electrode, 76 is a side wall, 77 is a PSG film, 78 is an insulating film, 79 is a barrier metal, and 80 is conductive. The plug, 81 is an interlayer insulating film, 82 is a barrier metal, 83 is a Cu wiring, and 84 is a barrier insulating film.
In the figure, an element is introduced through a buried oxide film 64 (SIMOX method) formed by high-temperature heat treatment by implanting oxygen ions into a p-type SiGe layer 62 laminated on a p-type silicon substrate 61. A p-type strained SOI substrate composed of a p-type strained Si layer 66 on a p-type SiGe layer 62 isolated in an island shape by an isolation region (SiO ₂ ) 65 and n on the n-type SiGe layer 63. An n-type strained SOI substrate composed of a strain-type strained Si layer 67 is formed. In the p-type strained SOI substrate, n-type source / drain regions (69, 70) self-aligned with the gate electrode 75 are formed on the sidewalls 76. N channel LDD (Lightly Doped Drain) composed of self-aligned n ⁺ type source / drain regions (68, 71)
A MIS field effect transistor having a structure is formed, and a P ⁺ type source / drain region (72, 73) self-aligned on a sidewall 76 self-aligned on a gate electrode 75 is formed on an n-type strained SOI substrate. A channel MIS field effect transistor is formed. Further, a Cu wiring 83 having a barrier metal 82 is connected to the n ⁺ type source / drain region (68, 71) and the p ⁺ type source / drain region (72, 73) through a barrier metal 79 and a conductive brag 80, respectively. A desired voltage is applied.
Therefore, the junction capacitance can be reduced by forming a source / drain region surrounded by an insulating film, the depletion layer capacitance can be reduced by completely depleting a thin-film strained SOI substrate, the breakdown voltage of the source / drain region can be improved, and the subthreshold characteristics can be achieved. Compared to CMOS consisting of MIS field-effect transistors formed on a normal bulk wafer by reducing threshold voltage due to improvement, removal of contact region to strained SOI substrate, etc., higher speed, lower power and higher integration are possible Become.
In addition, since a MIS field-effect transistor can be formed on a strained SOI substrate in which a strained Si layer is stacked on a SiGe layer, strain can be formed in the Si layer due to the tensile stress caused by the SiGe layer having a large lattice constant, and the lattice constant can be expanded. The speed can be increased and the speed can be increased.
However, since both the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor are formed on the strained SOI substrate in which the strained Si layer is laminated on the SiGe layer, the mobility of electrons and holes can be improved. Although there is a difference of about 4 times in the mobility of electrons and holes from the beginning, although there is a high speed, there is a disadvantage that the on / off special balance of switching speed is bad. The channel width of the MIS field effect transistor has to be widened, making it difficult to achieve high integration.
Both the N channel MIS field effect transistor and the P channel MIS field effect transistor form a strained Si layer. However, in the plane orientation of the Si layer that increases the mobility of holes in the P channel MIS field effect transistor, the N channel The MIS field effect transistor has a drawback that the electron mobility is lowered.
In particular, in the case of a CMOS in which N-channel and P-channel MIS field effect transistors having opposite on / off states coexist, the MIS field effect of one channel is set regardless of whether the semiconductor substrate is set to the ground voltage or the power supply voltage. The back channel of the transistor is always off, but the back channel of the NIS field-effect transistor of the other channel is always on, causing not only excess current to flow, but also causing malfunctions. Therefore, it has been difficult to manufacture an SOI structure CMOS type semiconductor integrated circuit aiming at low power.
In the case of a CMOS circuit, the gate electrodes of a pair of N-channel and P-channel MIS field effect transistors are generally connected and applied with the same voltage. Since the gate electrode connection wirings are separately formed on the electrodes and connected to each other, it is difficult to miniaturize the wiring and to achieve high integration.
In addition, since the SIMOX method is used as a means for creating an SOI structure, it is necessary to purchase an extremely expensive high-dose ion implantation machine, and a long-time manufacturing process for implanting high-dose oxygen ions. The problem of high cost due to the need for high-density wafers, the problem of instability of characteristics related to the repair of crystal defects by oxygen ion implantation in the use of large-diameter wafers of 10 inches to 12 inches, and thick embedding even when ion implantation of high dose oxygen There are also disadvantages such as the problem that it is difficult to reduce the capacitance with the lower layer region because an oxide film cannot be obtained.

JP2012-142492

The problem to be solved by the present invention, as shown in the conventional example,
(1) Since the SOI structure is formed by the SIMOX method, the cost is considerably high, and it can be used only for special purpose products with high added value, and the technology applicable to inexpensive general-purpose products is scarce.
(2) Since it is difficult to control the thinning of the SOI substrate in a large-diameter wafer, it is difficult to form a fully depleted SOI substrate, and it is difficult to obtain stability of characteristics of a large number of built-in MIS field effect transistors. .
(3) When a conductor (semiconductor substrate or lower layer wiring) is present under the SOI substrate of the MIS field effect transistor formed in the SOI structure, when a voltage different from the voltage applied to the gate electrode is applied (particularly the on-voltage) In other words, a minute back channel leak generated at the bottom of the SOI substrate could not be prevented.
(4) In a CMOS in which N-channel and P-channel MIS field effect transistors having opposite on / off states coexist, the MIS field effect of one channel regardless of whether the semiconductor substrate is set to the ground voltage or the power supply voltage. The back channel of the transistor is always off, but the back channel of the NIS field effect transistor of the other channel is always on, causing not only an excessive current to flow but also causing a malfunction. It was difficult to manufacture integrated circuits.
(5) In the strained Si layer, the plane orientation that increases the mobility of electrons and holes is different, and in the plane orientation that increases the mobility of holes in the P-channel MIS field effect transistor, the electron orientation of the N-channel MIS field effect transistor The mobility decreased, and it was difficult to manufacture a highly integrated CMOS semiconductor integrated circuit having high-speed switching characteristics.
(6) Gate electrode connection wirings are formed on the individual gate electrodes of a pair of N-channel and P-channel MIS field effect transistors and connected to each other. It was difficult to achieve high integration.
Such problems are becoming more prominent, and it is difficult to achieve higher speed, higher performance, and higher reliability simply by forming a MIS field effect transistor having a fine strained SOI structure with the current technology. is there.

The object is to provide a flat plate comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a second semiconductor layer selectively provided on the insulating film and sandwiching the first semiconductor layer from the left and right. a lower semiconductor layer of the structure, the and the lower semiconductor layer interlayer insulating film and the holes provided on, provided on the interlayer insulating film and the pores on the fourth sandwiched from the left and right of the third semiconductor layer An upper semiconductor layer of a flat plate structure composed of the semiconductor layer, a gate insulating film provided all around the first semiconductor layer and the third semiconductor layer, and the first insulating layer through the gate insulating film. An integrated surrounding gate electrode having a gate length all around the same provided in a structure surrounding the semiconductor layer and the third semiconductor layer, and the second semiconductor layer self-aligned with the integrated surrounding gate electrode One conductivity type source / drain region provided in , Said first channel region provided in the semiconductor layer, and opposite conductivity type source drain regions self aligned provided on the fourth semiconductor layer to said integrated encircling gate electrode, said third semiconductor And a channel region provided in the layer, and at least the first semiconductor layer and the third semiconductor layer are solved by the semiconductor device of the present invention made of different single element semiconductors.
Here, the integrated surrounding gate electrode means that the surrounding gate electrode of the N-channel MIS field effect transistor and the surrounding gate electrode of the P-channel MIS field effect transistor which are stacked one above the other are integrated as a single surrounding gate electrode. It is a thing.

As described above, according to the present invention, an SOI substrate is not formed by the SIMOX method, which increases the cost, and a normal inexpensive semiconductor substrate is used, and each layer is laminated on an insulating film using an epitaxial growth technique. An SOI substrate composed of a lower semiconductor layer (strained Ge layer / SiGe layer having a strained Ge layer sandwiched from the left and right) and an upper semiconductor layer (SiGe layer sandwiching a strained Si layer from the left and right) of the single crystal semiconductor layer Each of the SOI substrates is provided with a surrounding gate electrode integrated (commonized) via a gate oxide film around a part of the SOI substrate (a channel region made of a strained Ge layer or a strained Si layer). A stacked SOI structure in which a source / drain region is provided on a remaining SOI substrate (a strained Ge layer / SiGe layer or SiGe layer having a two-layer structure). N-channel and P-channel MIS field effect transistors can be formed, so that the threshold voltage is reduced by reducing the junction capacitance of the source / drain region (substantially zero), reducing the depletion layer capacitance, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics. Reduction, lower power consumption, and the like.
In addition, by forming an epitaxially grown semiconductor layer by providing a base insulating film barrier layer on the upper surface of the base insulating film so that the epitaxially grown semiconductor layer and the base insulating film do not come into contact with each other during the growth of the semiconductor layer by epitaxial growth, the base insulating film is formed. It is possible to form an SOI substrate made of a fully depleted single crystal semiconductor layer in which partial amorphization due to the influence of the above is prevented.
Further, since the thickness of the semiconductor layer (strained Si layer, strained Ge layer, SiGe layer, etc.) can be determined by the thickness of the silicon nitride film (Si ₃ N ₄ ) grown on the base insulating film barrier layer, a large-diameter wafer It is possible to easily form an SOI substrate made of a thin film fully depleted single crystal semiconductor layer that can be manufactured by the above-described manufacturing method.
In addition, since the gate electrode (WSi) provided through the gate oxide film (HfO ₂ ) can be formed so as to surround the semiconductor layer (a channel region made of a strained Si layer or a strained Ge layer), a back channel unique to the SOI structure can be formed. The effect can be improved, current paths other than the channel can be cut off, and the channel can be formed on four sides (upper and lower sides and two sides in the channel width direction) as well as complete channel control by the gate electrode (WSi). Therefore, the channel width can be increased without increasing the area occupied by the surface (upper surface), so that the drive current can be increased.
In addition, the lower and upper single crystal semiconductor layers can be formed through an insulating film by an easy manufacturing process, and the N channel formed in the upper semiconductor layer is directly above the P channel MIS field effect transistor formed in the lower semiconductor layer. Since the MIS field effect transistors can be formed by being stacked, a CMOS circuit (inverter) having a fine surface (upper surface) occupied area that does not require an occupied area of the surface (upper surface) of each MIS field effect transistor can be formed. Can be formed as an enclosed gate electrode in which the gate electrode of the P-channel MIS field effect transistor and the gate electrode of the N-channel MIS field effect transistor are integrated (shared) by self-alignment. P-channel MIS field effect stacked almost directly above Since the drain regions of the transistor and the N-channel MIS field effect transistor can be side-connected in the vertical direction, it is possible to achieve miniaturization because the wiring can be highly integrated.
Strained Ge layer that can greatly improve hole mobility (hole mobility is about 5 times that of Si layer in the case of Ge layer, but the lattice constant is slightly higher than that of normal Ge layer due to compressive stress of SiGe layer) P-channel MIS field-effect transistor can be formed with a slightly reduced mobility, and a SiGe layer sandwiching a strained Si layer that can increase the mobility of electrons (the lattice constant is increased by the tensile stress of the SiGe layer). The N-channel MIS field effect transistor can be formed in such a manner that the mobility is improved), and therefore, it is possible to obtain an extremely well-balanced high-speed CMOS that is not affected by the characteristics of the other MIS field effect transistor.
In addition, since a complete SOI structure CMOS circuit (inverter) can be formed, it is possible to completely prevent malfunction due to high voltage noise generated in a semiconductor substrate due to static electricity or the like or latch-up characteristics peculiar to CMOS.
Further, high reliability by being able to convert the vertical (vertical) direction epitaxial semiconductor layer necessary for forming each semiconductor layer (SOI substrate) into a buried insulating film that forms a part of the element isolation region by self-alignment, and High integration can be achieved.
In addition, it is self-aligned with a part of a fine semiconductor layer having excellent crystallinity (a channel region made of a strained Si layer or a strained Ge layer), and constitutes a component of a MIS field effect transistor (low and high concentration source / drain). It is also possible to finely form the region, the gate oxide film, and the integrated surrounding gate electrode.
In addition, by providing holes between the upper and lower semiconductor layers, the capacitance between the p ⁺ type source region (connected to the power supply line) and the n ⁺ type source region (connected to the ground line) can be reduced (generally, air and silicon oxide) It is possible to realize a high speed due to the difference in dielectric constant from the film (SiO ₂ ).
In addition, a thin silicon oxide film (SiO ₂ ) surrounding the vacancies can be easily formed so that the vacancies do not exist directly under the source / drain regions of the N-channel MIS field effect transistor, and the current leakage resistance is further improved. It can also be strengthened.
Further, it is possible to form the lower semiconductor layer only with an unstrained Ge layer, and the hole mobility can be further increased, so that the speed of the P-channel MIS field effect transistor can be further increased.
In addition, an N-channel MIS field effect transistor formed in the upper semiconductor layer can be formed in the metal source / drain region, and the resistance of the source / drain region of the N-channel MIS field effect transistor can be reduced, resulting in higher speed. it can.
In addition, the drain regions of the N-channel and P-channel MIS field effect transistors can be independently connected to the wiring layer, and can be applied to a 2-input NAND circuit or a 2-input NOR circuit in addition to a fine NOT circuit (inverter). Since a possible configuration can be obtained, it is possible to form an extremely highly integrated CMOS type semiconductor integrated circuit by properly using them.
In other words, high-speed, high-reliability, high-performance, and high-speed, capable of manufacturing large-scale semiconductor integrated circuits that can be used for high-speed, large-capacity communication devices, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. A CMOS semiconductor device having an extremely low power SOI structure having integration can be obtained.
The present inventors named CMOS (CMOS with Di fferent S emiconductor Layer and S implified Su rrounding G ate on Insulator) with a heterologous semiconductor layer and integrally surrounding gate electrode on the art insulating film, hereinafter the technology It is abbreviated as DISSSUG.

Schematic side sectional view of the first embodiment of the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the first embodiment in the semiconductor device of the present invention (channel width direction, channel portion) Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel width direction, channel area | region part) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel width direction, channel area | region part) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel width direction, channel area | region part) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel width direction, source region part) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel width direction, source region part) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel width direction, source region part) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of 1st Example in the semiconductor device of this invention Schematic side sectional view of the second embodiment of the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the third embodiment of the semiconductor device of the present invention (channel length direction) Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel width direction, source region part) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Process sectional drawing (channel width direction, source region part) of the manufacturing method of the 3rd Example in the semiconductor device of this invention Schematic side sectional view of the fourth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the fifth embodiment in the semiconductor device of the present invention (channel length direction) Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Process sectional drawing (channel length direction) of the manufacturing method of the 5th Example in the semiconductor device of this invention Schematic side sectional view of the sixth embodiment in the semiconductor device of the present invention (channel length direction) Schematic side sectional view of the seventh embodiment in the semiconductor device of the present invention (channel length direction) CMOS NOT circuit (inverter) CMOS 2-input NAND circuit CMOS 2-input NOR circuit Schematic side sectional view of a conventional semiconductor device (channel length direction)

The present invention is
(1) An insulating film consisting of a plurality of layers and a base insulating film barrier layer (TiN) are formed on a Si substrate, selectively opened, and a first vertical (vertical) epitaxial Si layer is grown from the surface of the Si substrate. Let
(2) A lateral (horizontal) direction epitaxial SiGe layer (Ge concentration of about 20%) is grown on a base insulating film barrier layer (TiN) from a part of the side surface of the first longitudinal (vertical) direction epitaxial Si layer.
(3) The SiGe layer is thermally oxidized to increase the Ge concentration (the Si concentration is lowered by oxidizing Si and forming a silicon oxide film) (Ge concentration is about 80%).
(4) A longitudinal (vertical) direction epitaxial Ge layer (which becomes a strained Ge layer) is grown on the SiGe layer (Ge concentration of about 80%). (Formation of lower semiconductor layer)
(5) An interlayer insulating film composed of a plurality of layers and a base insulating film barrier layer (TiN) are formed on the entire surface including the lower semiconductor layer (a strained Ge layer / SiGe layer having a two-layer structure), and selectively opened. The surface of the first longitudinal (vertical) epitaxial Si layer is exposed.
(6) A second longitudinal (vertical) epitaxial Si layer is grown on the first longitudinal (vertical) epitaxial Si layer.
(7) A lateral (horizontal) direction epitaxial Si layer is grown on a part of the side surface of the second longitudinal (vertical) direction epitaxial Si layer on the base insulating film barrier layer (TiN). (Formation of upper semiconductor layer)
(8) A part of the upper semiconductor layer (Si layer), a part of the interlayer insulating film, and the second and first longitudinal (vertical) epitaxial Si layers are removed to form an opening.
(9) A p ⁺ -type source / drain region is formed in a part of the lower semiconductor layer (a strained Ge layer / SiGe layer having a two-layer structure) under the opening.
(10) An element isolation region is formed by filling the opening with a flat insulating film.
(11) A part of the element isolation region is selectively opened, and part of the side surfaces of the upper semiconductor layer (Si layer) and the lower semiconductor layer (two-layer strained Ge layer / SiGe layer) are exposed and formed. The conductive film is flatly embedded in the opened hole, and side connection is performed.
(12) After forming an insulating film on the entire surface including the upper semiconductor layer (Si layer), a part of the upper semiconductor layer (Si layer) and the lower semiconductor layer (two-layer strained Ge layer / SiGe layer) (channel region) And a hole portion for removing each underlying insulating film barrier layer (TiN) and its surrounding insulating film immediately below.
(13) A lateral (horizontal) direction epitaxial Ge layer (strained Ge layer) is disposed between the side surfaces of the exposed lower semiconductor layer (strained Ge layer / SiGe layer having a two-layer structure), and a lateral (horizontal) region is disposed between the side surfaces of the upper semiconductor layer. Directional epitaxial Si layers (which eventually become strained Si layers) are grown sequentially.
(14) A monolithic surrounding gate electrode is embedded flatly around the strained Ge layer and strained Si layer for forming the channel region via a gate insulating film.
(15) A part of the upper semiconductor layer (Si layer) (source / drain region forming portion), a base insulating film barrier layer (TiN) directly below, and an interlayer insulating film directly below the self-aligned gate electrode An opening part for removing a part is formed, and a p ⁺ type source / drain region is formed in a lower semiconductor layer (a strained Ge layer / SiGe layer having a two-layer structure) below the opening part.
(16) A lateral (horizontal) epitaxial SiGe layer (a source / drain region forming portion of the upper semiconductor layer, Ge concentration of about 20%) is grown on the side surface of the exposed upper semiconductor layer (Si layer).
(17) An n-type source / drain region is formed in the upper semiconductor layer (SiGe layer) in a self-aligned manner with the integrated surrounding gate electrode.
(18) After forming a sidewall on the side wall of the integral surrounding gate electrode, an n ⁺ type source / drain region is formed in the upper semiconductor layer (SiGe layer) in a self-aligned manner with the sidewall.
(19) A wiring is formed, and P-channel and N-channel MIS field effect transistors formed in the lower semiconductor layer and the upper semiconductor layer, respectively, are appropriately connected.
Using technology such as
1) Formation of a single crystal semiconductor layer by epitaxial growth provided with a base insulating film barrier layer (TiN).
2) Lowering the temperature of the epitaxially grown semiconductor layer after ion implantation of impurities for forming the source / drain region.
3) Optimization of the Ge concentration in the SiGe layer for forming the strained Ge layer and the strained Si layer.
Etc.
A lower semiconductor layer composed of a strained Ge layer / SiGe layer (Ge concentration of about 80%) having a two-layer structure in which a strained Ge layer is sandwiched from the left and right is provided on a Si substrate via a silicon nitride film and a silicon oxide film. An upper semiconductor layer composed of a SiGe layer (Ge concentration of about 20%) sandwiching the strained Si layer from the left and right is provided via a thin insulating film and a hole directly above, and gate insulation is provided around the strained Ge layer and the strained Si layer. Through the film, an integrated surrounding gate electrode is provided in the surrounding structure, and is self-aligned with the integrated surrounding gate electrode to form a strained Ge layer / SiGe layer (Ge concentration of about 80%) in a two-layer structure. , Approximately p ⁺ -type source / drain regions) are provided in the SiGe layer (Ge concentration of about 20%), respectively, and approximately n-type and n ⁺ -type source / drain regions are provided, respectively. Cha Le region is provided, which is constituted of the highly integrated CMOS consisting of N-channel and P-channel MIS field effect transistor of the stacked SOI structure.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side sectional view are shown only on the main insulating film, and the wiring is drawn with a slight back-and-forth displacement, and the horizontal and vertical sizes are accurate to show the main part of the invention. The dimensions are not shown.
1 to 32 show a first embodiment of the semiconductor device according to the present invention. FIG. 1 is a schematic side sectional view (channel length direction), and FIG. 2 is a schematic side sectional view (channel width direction, channel region portion). 3 to 32 are process sectional views of the manufacturing method.
1 and 2 show a part of a CMOS type semiconductor integrated circuit including a short-channel N-channel and P-channel MIS field-effect transistor formed on a DISSSUG structure using a silicon (Si) substrate. A p-type silicon (Si) substrate of about 10 ¹⁵ cm ⁻³ , 2 is a silicon nitride film (Si ₃ N ₄ ) of about 100 nm, 3 is a silicon oxide film (SiO ₂ ) of about 80 nm, and 4 is a base of about 20 nm An insulating film barrier layer (TiN), 5 is a silicon nitride film (Si ₃ N ₄ ) in an element isolation region of about 80 nm, 6 is an n-type epitaxial SiGe layer (Ge) having a thickness of about 15 nm and a concentration of about 10 ¹⁷ cm ^−3. N is an n-type epitaxial strain G having a film thickness of about 45 nm and a concentration of about 10 ¹⁷ cm ^−3. An e layer (source / drain region forming portion), 8 is an n-type epitaxial strained Ge layer (channel region forming portion) having a film thickness of about 60 nm and a concentration of about 10 ¹⁷ cm ⁻³ , and 9 is a silicon nitride film (Si ₃ ) having a thickness of about 10 nm. N ₄ ), 10 is a gate oxide film (HfO ₂ ) having a thickness of about 5 nm, 11 is an integrated surrounding gate electrode (WSi) having a gate length of about 30 nm and a film thickness of about 100 nm, and 12 is a p ^{+ of} about 10 ²⁰ cm ^−3. Type source region, 13 is a p ⁺ type drain region of about 10 ²⁰ cm ⁻³ , 14 is a silicon oxide film (SiO ₂ ) of about 70 nm, and 15 is a silicon in an element isolation region of about 80 nm (including a part of the thick film part). nitride film _{(Si 3} N 4), 16 is embedded conductive film (WSi, for side connection), 17 holes, 18 thickness of about 60 nm, the concentration ¹⁰ 17 ^{cm -3} of about p-type d Takisharu SiGe layer (Ge concentration of 20% of the source drain region formation unit), 19 the film thickness 60nm approximately, concentration ¹⁰ 17 ^{cm -3} of about p-type epitaxial strained Si layer (channel region forming part) 20 ^{10 20} n ⁺ -type source region of about cm ⁻³ , 21 is an n-type source region of about 5 × 10 ¹⁷ cm ⁻³ , 22 is an n-type drain region of about 5 × 10 ¹⁷ cm ⁻³ , and 23 is 10 ²⁰ cm ^−3. N ⁺ -type drain region, 24 is a sidewall (SiO ₂ ) of about 20 nm, 25 is a phosphosilicate glass (PSG) film of about 300 nm, 26 is a silicon nitride film (Si ₃ N ₄ ) of about 20 nm, 27 is Barrier metal (TiN) of about 10 nm, 28 is a conductive plug (W), 29 is an insulating film (SiOC) of about 500 nm, and 30 is a barrier metal of about 10 nm. (TaN), 31 is a Cu wiring (including a Cu seed layer) of about 500 nm, and 32 is a barrier insulating film (Si ₃ N ₄ ) of about 20 nm.

In FIG. 1 (channel length direction), a silicon nitride film (Si ₃ N ₄ ) 2 is provided on a p-type silicon substrate 1, and silicon is selectively formed on the silicon nitride film (Si ₃ N ₄ ) 2. An oxide film (SiO ₂ ) 3 is provided, a base insulating film barrier layer (TiN) 4 is selectively provided on the silicon oxide film (SiO ₂ ) 3, and a base insulating film barrier layer (TiN) 4 is provided. Is provided with a pair of n-type SiGe layer 6 and strained Ge layer 7, and n-type strained Ge layer 8 is sandwiched between the opposing side surfaces of the pair of SiGe layer 6 and strained Ge layer 7. The lower semiconductor layer (6, 7, 8) having the structure provided is provided, and a hole 17 is formed in a part on the strained Ge layer 7 through a silicon nitride film (Si ₃ N ₄ ) 9. A pair of p-type SiGe layers 18 are provided on the holes, An upper semiconductor layer (18, 19) having a structure in which a p-type strained Si layer 19 is sandwiched between the opposing side surfaces of the pair of SiGe layers 18 is provided, and the lower semiconductor layers (6, 7, 8) are provided. ) And the upper semiconductor layers (18, 19) are insulated and isolated in an island shape by silicon nitride films (Si ₃ N ₄ ) (5, 15) in the element isolation region. Further, around the strained Ge layer 8 and the Si layer 19 that coincide with each other in the vertical direction, an integrated enclosed gate electrode (WSi) 11 is formed through a gate oxide film (HfO ₂ ) 10 and a silicon nitride film (Si ₃ N _4). ) 2 and a side wall (SiO ₂ ) 24 is provided on the side wall of the upper surface portion of the integral surrounding gate electrode 11 via a gate oxide film (HfO ₂ ) 10, and the SiGe layer 6 and the strained Ge layer 7 is provided with an approximately p ⁺ type source / drain region (12, 13), and the strained Ge layer 8 is provided with an approximate channel region (actually, the p ⁺ type source / drain region (12, 13). P-channel MIS field effect transistors are formed in the lower semiconductor layers (6, 7, 8), while the SiGe layer 18 has a substantially n-type source / drain region ( 1, 22) and ^{n +} -type source and drain regions (20, 23) is provided, on the strained Si layer 19 is a schematic channel region is provided (actually a n-type source drain region (21, 22) An N-channel MIS field effect transistor having an LDD structure (which is slightly diffused in the lateral direction) is formed in the upper semiconductor layers (18, 19). The p ⁺ -type drain region 13 and the n ⁺ -type drain region 23 are connected to each other by a buried conductive film (WSi) 16, and the buried conductive film (WSi) 16, the p ⁺ -type source region 12, and the n ⁺ -type source region 20. The Cu wiring 31 having the barrier metal (TaN) 30 is connected to each via the conductive plug (W) 28 having the barrier metal (TiN) 27.

Figure 2 (channel width direction, the channel region portion) in the silicon nitride film _{(Si 3 N} 4) 2 is provided on the silicon substrate 1 of p-type, on the silicon nitride film _{(Si 3 N} 4) 2 is A strained Ge layer 8 (a part of the lower semiconductor layer) and a strained Si layer 19 (upper semiconductor layer) each surrounded by a monolithic surrounding gate electrode (WSi) 11 via a gate oxide film (SiO ₂ ) 10. A Cu wiring 31 having a barrier metal (TaN) 30 is connected to the integrated surrounding gate electrode 11 via a conductive plug (W) 28 having a barrier metal (TiN) 27. Has been.

Therefore, using an ordinary inexpensive semiconductor substrate and utilizing epitaxial growth technology (the manufacturing method will be described in detail separately), the lower semiconductor layer (single-Ge layer from the left and right) of each single crystal semiconductor layer stacked on the insulating film An SOI substrate composed of a sandwiched two-layer strained Ge layer / SiGe layer) and an upper semiconductor layer (SiGe layer sandwiching the strained Si layer from the left and right) is provided, and each SOI substrate includes a part of the SOI substrate (strained Ge layer). A surrounding gate electrode integrated (commonized) via a gate oxide film is provided around a channel region or a channel region made of a strained Si layer) to form a channel region, and a rough remaining SOI substrate (a strain of a two-layer structure) N-channel and P-channel MIS field effect transistors having a stacked SOI structure in which a source / drain region is provided in a Ge layer / SiGe layer or SiGe layer) Since it can be formed, the junction capacitance of the source / drain region can be reduced (substantially zero), the depletion layer capacitance can be reduced, the breakdown voltage of the source / drain region can be improved, and the subthreshold characteristics can be reduced, thereby reducing the threshold voltage and reducing the power consumption. .
In addition, by forming an epitaxially grown semiconductor layer by providing a base insulating film barrier layer on the upper surface of the base insulating film so that the epitaxially grown semiconductor layer and the base insulating film do not come into contact with each other during the growth of the semiconductor layer by epitaxial growth, the base insulating film is formed. It is possible to form an SOI substrate made of a fully depleted single crystal semiconductor layer in which partial amorphization due to the influence of the above is prevented.
Further, since the thickness of the semiconductor layer (strained Si layer, strained Ge layer, SiGe layer, etc.) can be determined by the thickness of the silicon nitride film (Si ₃ N ₄ ) grown on the base insulating film barrier layer, a large-diameter wafer It is possible to easily form an SOI substrate made of a thin film fully depleted single crystal semiconductor layer that can be manufactured by the above-described manufacturing method.
In addition, since the gate electrode (WSi) provided through the gate oxide film (HfO ₂ ) can be formed so as to surround the semiconductor layer (a channel region made of a strained Si layer or a strained Ge layer), a back channel unique to the SOI structure can be formed. The effect can be improved, current paths other than the channel can be cut off, and the channel can be formed on four sides (upper and lower sides and two sides in the channel width direction) as well as complete channel control by the gate electrode (WSi). Therefore, the channel width can be increased without increasing the area occupied by the surface (upper surface), so that the drive current can be increased.
In addition, by a simple manufacturing process, a single crystal semiconductor layer of a lower layer and an upper layer stacked via an insulating film can be formed, and N formed in the upper semiconductor layer is directly above the P-channel MIS field effect transistor formed in the lower semiconductor layer. Since channel MIS field effect transistors can be formed by being stacked, a CMOS circuit (inverter) having a fine surface (upper surface) occupation area that does not require an area occupied by the surface (upper surface) of each MIS field effect transistor can be formed. Miniaturization can be formed as an enclosed gate electrode in which the gate electrode of the P-channel MIS field effect transistor and the gate electrode of the N-channel MIS field effect transistor are integrated (shared) by self-alignment, thereby allowing high integration of gate electrode wiring. P-channel MIS electric field effect layered almost immediately above Since the drain regions of the fruit transistor and the N-channel MIS field effect transistor can be connected to the side surfaces in the vertical direction, it is possible to achieve miniaturization because the wiring can be highly integrated.
Strained Ge layer that can greatly improve hole mobility (hole mobility is about 5 times that of Si layer in the case of Ge layer, but the lattice constant is slightly higher than that of normal Ge layer due to compressive stress of SiGe layer) P-channel MIS field-effect transistor can be formed with a slightly reduced mobility, and a SiGe layer sandwiching a strained Si layer that can increase the mobility of electrons (the lattice constant is increased by the tensile stress of the SiGe layer). The N-channel MIS field effect transistor can be formed in such a manner that the mobility is improved), and therefore, it is possible to obtain an extremely well-balanced high-speed CMOS that is not affected by the characteristics of the other MIS field effect transistor.
In addition, since a complete SOI structure CMOS circuit (inverter) can be formed, it is possible to completely prevent malfunction due to high voltage noise generated in a semiconductor substrate due to static electricity or the like or latch-up characteristics peculiar to CMOS.
Further, high reliability by being able to convert the vertical (vertical) direction epitaxial semiconductor layer necessary for forming each semiconductor layer (SOI substrate) into a buried insulating film that forms a part of the element isolation region by self-alignment, and High integration can be achieved.
In addition, it is self-aligned with a part of a fine semiconductor layer having excellent crystallinity (a channel region made of a strained Si layer or a strained Ge layer), and constitutes a component of a MIS field effect transistor (low and high concentration source / drain). It is also possible to finely form the region, the gate oxide film, and the integrated surrounding gate electrode.
In addition, by providing holes between the upper and lower semiconductor layers, the capacitance between the p ⁺ type source region (connected to the power supply line) and the n ⁺ type source region (connected to the ground line) can be reduced (generally, air and silicon oxide) It is possible to realize a high speed due to the difference in dielectric constant from the film (SiO ₂ ).
In other words, high-speed, high-reliability, high-performance, and high-speed, capable of manufacturing large-scale semiconductor integrated circuits that can be used for high-speed, large-capacity communication devices, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. A CMOS semiconductor device having an extremely low power SOI structure having integration can be obtained.

  Next, the manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 1 to 32 using schematic side sectional views showing the channel length direction. A schematic side cross-sectional view showing directions will also be described as appropriate. (Here, only the manufacturing method related to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method related to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is Omitted.

Figure 3 (channel length direction)
A silicon nitride film (Si ₃ N ₄ ) 2 is grown on the p-type silicon substrate 1 by about 100 nm by chemical vapor deposition. Next, a silicon oxide film (SiO ₂ ) 3 of about 80 nm is grown by chemical vapor deposition. Next, a base insulating film barrier layer (TiN) 4 of about 20 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 33 serving as an insulating film for defining the epitaxial semiconductor layer thickness is grown by about 60 nm by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 33, a base insulating film barrier layer (TiN) 4, a silicon oxide film (SiO 2) ₂ ) 3 and silicon nitride film (Si ₃ N ₄ ) 2 are sequentially subjected to anisotropic dry etching to form openings. Next, the resist (not shown) is removed.

Fig. 4 (channel length direction)
Next, an n-type longitudinal (vertical) epitaxial Si layer 34 is grown on the exposed p-type silicon substrate 1. Next, chemical mechanical polishing (hereinafter abbreviated as CMP) is performed to planarize the epitaxial Si layer 34 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 33. Next, a tungsten film 35 of about 30 nm is grown on the epitaxial Si layer 34 by selective chemical vapor deposition.

Figure 5 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 33 is anisotropically dry etched using a resist (not shown) as a mask layer, and a partial side surface of the epitaxial Si layer 34 And an opening that exposes the upper surface of the underlying insulating film barrier layer (TiN) 4 is formed. Next, the resist (not shown) is removed.

Fig. 6 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial SiGe layer (Ge concentration of about 20%) 36 is grown on the underlying insulating film barrier layer (TiN) 4 from the exposed side surface of the epitaxial Si layer 34, and a silicon nitride film (Si ₃ N ₄ ) 33 holes are embedded. The epitaxial SiGe layer 36 grown here becomes a complete single crystal semiconductor layer that is not affected by the underlying silicon oxide film (SiO ₂ ) 3 by the underlying insulating film barrier layer (TiN) 4. (Without this underlying insulating film barrier layer (TiN) 4, a part of the semiconductor layer becomes amorphous due to the influence of the underlying silicon oxide film (SiO ₂ ) 3, and a minute amount is formed between the source and drain regions. However, this underlying insulating film barrier layer (TiN) may be present when the semiconductor layer is epitaxially grown, and even if it is removed after the growth of the semiconductor layer, the grown single crystal semiconductor layer has no problem. (There is no problem. As will be described later, in the completed drawing, the base insulating film barrier layer (TiN) is removed and does not exist under the upper semiconductor layer.)

Fig. 7 (channel length direction)
Next, the surface of the SiGe layer 36 is oxidized at about 1000 ° C. to grow a silicon oxide film (SiO ₂ ) (not shown) of about 90 nm. At this time, since Ge does not diffuse into the silicon oxide film, the SiGe layer remaining in a film thickness of about 15 nm becomes the SiGe layer 6 having a Ge concentration of about 80%. Next, the silicon oxide film (SiO ₂ ) (not shown) on the SiGe layer 6 is removed by etching.

Fig. 8 (channel length direction)
Next, an n-type longitudinal (vertical) direction epitaxial Ge layer 7 is grown on the SiGe layer 6. Next, chemical mechanical polishing (CMP) is performed to flatten the epitaxial Ge layer 7 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 33 to form a Ge layer 7 (to be a strained Ge layer) of about 45 nm. . At this time, the tungsten film 35 is also removed. Next, annealing is performed at about 900 ° C. to relax the distortion of the Ge layer 7. In this way, the lower semiconductor layer (6, 7) composed of a strained Ge layer / SiGe layer having a two-layer structure is formed.

Figure 9 (channel length direction)
Next, using the strained Ge layer 7 and the Si layer 34 as a mask layer, the silicon nitride film (Si ₃ N ₄ ) 33 and the base insulating film barrier layer (TiN) 4 are sequentially subjected to anisotropic dry etching to form an opening. Next, a silicon nitride film (Si ₃ N ₄ ) of about 80 nm is grown by chemical vapor deposition. Next, the silicon nitride film (Si ₃ N ₄ ) on the flat surfaces of the strained Ge layer 7 and the Si layer 34 is chemically mechanically polished (CMP), and the silicon nitride film (Si ₃ N ₄ ) 5 is flattened in the opening portion. A buried element isolation region is formed.

Figure 10 (channel length direction)
Next, a silicon nitride film (Si ₃ N ₄ ) 9 is grown to about 10 nm by chemical vapor deposition. Next, a silicon oxide film (SiO ₂ ) 14 of about 70 nm is grown by chemical vapor deposition. Next, a base insulating film barrier layer (TiN) 37 of about 20 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 38 serving as an insulating film for defining the epitaxial semiconductor layer thickness is grown by chemical vapor deposition to about 60 nm.

FIG. 11 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 38, a base insulating film barrier layer (TiN) 37, a silicon oxide film (SiO 2) ₂ ) 14 and the silicon nitride film (Si ₃ N ₄ ) 9 are sequentially anisotropic dry etched to form an opening (opening width is about 100 nm) exposing the surface of the Si layer 34. Next, the resist (not shown) is removed.

Figure 12 (channel length direction)
Next, a p-type longitudinal (vertical) epitaxial Si layer 39 is grown on the exposed Si layer 34. Next, chemical mechanical polishing (CMP) is performed to planarize the vertical (vertical) epitaxial Si layer 39 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 38. Next, a tungsten film 40 of about 30 nm is grown by selective chemical vapor deposition.

FIG. 13 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 38 is anisotropically dry etched using a resist (not shown) as a mask layer, and a partial side surface of the epitaxial Si layer 39 is formed. In addition, an opening that exposes the upper surface of the base insulating film barrier layer (TiN) 37 is formed. Next, the resist (not shown) is removed.

Fig. 14 (channel length direction)
Next, a p-type lateral (horizontal) epitaxial Si layer 41 is grown on the underlying insulating film barrier layer (TiN) 37 from the exposed side surface of the epitaxial Si layer 39 to open the silicon nitride film (Si ₃ N ₄ ) 38. Embed the part. The grown Si layer 41 becomes a complete single crystal semiconductor layer that is not affected by the underlying silicon oxide film (SiO ₂ ) 14 by the underlying insulating film barrier layer (TiN) 37.

FIG. 15 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, a tungsten film 40, a Si layer (41, 39, 34), a base, using a resist (not shown) and a silicon nitride film (Si ₃ N ₄ ) 38 as a mask layer The insulating film barrier layer (TiN) 37 and the silicon oxide film (SiO ₂ ) 14 are sequentially subjected to anisotropic dry etching to form two-stage apertures. Next, boron ions are implanted into the strained Ge layer 7 and the SiGe layer 6 under the opening to form the p ⁺ type source region 12 (which becomes a part of the p ⁺ type source region). (Although not performed here the heat treatment step for activating and controlling the depth of the p ⁺ -type source region, p ⁺ -type source region previously shown. In this case, p-type silicon apertures subordinates (Si) substrate Boron is also ion-implanted into 1 but there is no problem.) Next, the resist (not shown) is removed.

FIG. 16 (channel length direction)
Next, using the Si layer 41 as a mask layer, the silicon nitride film (Si ₃ N ₄ ) 38 and the base insulating film barrier layer (TiN) 37 are sequentially subjected to anisotropic dry etching. Here, there are three openings. (At this time, the silicon nitride film (Si ₃ N ₄ ) 9 on the strained Ge layer 7 in the opening is also removed.) Next, a silicon nitride film (Si ₃ N ₄ ) of about 160 nm is formed by chemical vapor deposition. grow up. Next, the silicon nitride film (Si ₃ N ₄ ) existing above the flat surface of the Si layer 41 is subjected to chemical mechanical polishing (CMP), and the silicon nitride film (Si ₃ N ₄ ) 15 is embedded in the opening portion flatly. An isolation region is formed.

FIG. 17 (channel length direction)
Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 15, the silicon oxide film (SiO ₂ ) 14, and the silicon nitride are formed using the resist (not shown) and the Si layer 41 as a mask layer. The film (Si ₃ N ₄ ) (9, 5) is subjected to anisotropic dry etching in order to form an aperture (the aperture width is about 100 nm). Next, the resist (not shown) is removed.

FIG. 18 (channel length direction)
Next, a tungsten silicide (WSi) film of about 60 nm is grown by chemical vapor deposition. Next, the tungsten silicide (WSi) film existing above the flat surface of the Si layer 41 and the silicon nitride film (Si ₃ N ₄ ) 15 is chemically mechanically polished (CMP), and the tungsten silicide (WSi) is flatly formed in the opening portion. The film 16 is embedded, and the Si layer 41, the base insulating film barrier layer (TiN) 37, the strained Ge layer 7, the SiGe layer 6, and the base insulating film barrier layer (TiN) 4 are side-connected.

19 (channel length direction) and FIG. 20 (channel width direction, channel region portion)
Next, a silicon oxide film (SiO ₂ ) 42 is grown by about 10 nm by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 43 is grown by about 90 nm by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 43, a silicon oxide film (SiO ₂ ) 42, an Si layer 41, a base insulation A film barrier layer (TiN) 37, a silicon nitride film (Si ₃ N ₄ ) 15 (present on both sides in the width direction of the Si layer 41), a silicon oxide film (SiO ₂ ) 14, a silicon nitride film (Si ₃ N ₄ ) 9 , Strained Ge layer 7, SiGe layer 6, underlying insulating film barrier layer (TiN) 4, silicon nitride film (Si ₃ N ₄ ) 5 (present on both sides in the width direction of strained Ge layer 7 and SiGe layer 6), and silicon oxide The film (SiO ₂ ) 3 is selectively and sequentially subjected to anisotropic dry etching to form an opening. Next, the resist (not shown) is removed. (The wavy lines in FIG. 20 illustrate the Si layer 41, the strained Ge layer 7 and the SiGe layer 6 slightly behind the side cross section.)

21 (channel length direction) and FIG. 22 (channel width direction, channel region)
Next, between the strained Ge layer 7 and the SiGe layer 6 (Ge concentration of about 80%) whose side surfaces are exposed by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less) (electron coupling resonance plasma enhanced chemical deposition system). Then, an n-type lateral (horizontal) epitaxial Ge layer 8 (which becomes a strained Ge layer) is grown to form lower semiconductor layers (6, 7, 8) having vacancies in a part of the lower part. (At this time, a single crystal germanium layer having no influence of the base is formed immediately above the vacancy. Of course, the Ge layer does not grow between the Si layers 41.)

FIG. 23 (channel length direction) and FIG. 24 (channel width direction, channel region portion)
Next, a p-type lateral (horizontal) epitaxial Si layer 19 is grown between the Si layers 41 whose side surfaces are exposed by an ECR plasma CVD apparatus capable of low-temperature growth (500 ° C. or less), and empty at some lower portions. Upper semiconductor layers (19, 41) having holes are formed. (At this time, a single crystal silicon layer having no influence of the underlying layer is formed immediately above the vacancy.) Next, a gate oxide film (HfO ₂ ) 10 of about 5 nm is formed around the entire exposed Ge layer 8 and Si layer 19. To grow. (At this time, the gate oxide film (HfO ₂ ) 10 grows on the side and bottom surfaces of the opening and also on the upper surface of the silicon nitride film (Si ₃ N ₄ ) 43.) Next, about 25 kev penetrating the Si layer 19 Boron ions for threshold voltage control are implanted into the strained Ge layer 8 at the acceleration voltage of Next, boron ions for threshold voltage control are implanted into the Si layer 19 with an acceleration voltage of about 10 keV. Next, a tungsten silicide film (WSi) having a thickness of about 100 nm is grown by chemical vapor deposition so as to completely fill the open portions left over the entire surface including the entire periphery of the upper and lower gate oxide films (HfO ₂ ) 10. Next, chemical mechanical polishing (CMP) is performed to remove the excess gate oxide film (HfO ₂ ) 10 and tungsten silicide film (WSi) grown on the silicon nitride film (Si ₃ N ₄ ) 43 and planarize. In this way, an integrated surrounding gate electrode (WSi) 11 that is flatly embedded in the deep opening is formed. Next, it runs at about 900 ° C. to activate the channel region.

FIG. 25 (channel length direction) and FIG. 26 (channel width direction, source region portion)
Next, the silicon nitride film (Si ₃ N ₄ ) 43 and the silicon oxide film (SiO ₂ ) 42 are removed by etching. Next, using the integrated surrounding gate electrode (WSi) 11, the silicon nitride film (Si ₃ N ₄ ) 15 and the buried conductive film (WSi) 16 as a mask layer, the exposed Si layer 41, the underlying insulating film barrier layer (TiN) ) 37 and the silicon oxide film (SiO ₂ ) 14 are sequentially subjected to anisotropic dry etching to form an opening that exposes the silicon nitride film (Si ₃ N ₄ ) 9. Next, the integrated surrounding gate electrode (WSi) 11, the silicon nitride film (Si ₃ N ₄ ) 15 and the buried conductive film (WSi) 16 are used as mask layers, and the p ⁺ type source / drain region is formed on the strained Ge layer 7 and the SiGe layer 6. (12, 13) Boron ions are implanted. (Here it does not perform the heat treatment step for activating and controlling the depth of the p ⁺ -type source and drain regions, p ⁺ -type source and drain regions previously shown.)

FIG. 27 (channel length direction) and FIG. 28 (channel width direction, source region portion)
Next, a p-type lateral (horizontal) epitaxial SiGe layer 18 (Ge concentration of about 20%) is grown on the side surface of the Si layer 19 exposed by an ECR plasma CVD apparatus capable of low temperature growth (500 ° C. or less), The upper semiconductor layers (18, 19) having the holes 17 are formed. Therefore, the channel region becomes the strained Si layer 19. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, an n-type source / drain region (21, 22) is formed in the Si layer 18 using the integrated surrounding gate electrode (WSi) 11, the silicon nitride film (Si ₃ N ₄ ) 15 and the buried conductive film (WSi) 16 as a mask layer. I perform phosphorus ion implantation. (Here, a heat treatment step for activating and controlling the depth of the n-type source / drain region is not performed, but the n-type source / drain region is shown). Next, a silicon oxide film (SiO ₂ , shown) for ion implantation. 2) is removed by etching.

FIG. 29 (channel length direction) and FIG. 30 (channel width direction, source region portion)
Next, a silicon oxide film (SiO ₂ ) of about 20 nm is grown by chemical vapor deposition. Next, the entire surface is subjected to anisotropic dry etching to form a sidewall (SiO ₂ ) 24 on the side wall of the upper surface portion of the integrated surrounding gate electrode (WSi) 11. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, arsenic ions are implanted to form n ⁺ -type source / drain regions (20, 23) using the sidewalls (SiO ₂ ) 24 and the integrated surrounding gate electrode (WSi) 11 as mask layers. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, annealing is performed by an RTP (Rapid Thermal Processing) method to form n-type source / drain regions (21, 22), n ⁺ -type source / drain regions (20, 23), and p ⁺ -type source / drain regions (12, 13). .

Figure 31 (channel length direction)
Next, a PSG film 25 of about 300 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, a silicon nitride film (Si ₃ N ₄ ) 26 of about 20 nm is grown by chemical vapor deposition. Next, using a normal lithography technique using an exposure drawing apparatus, a silicon nitride film (Si ₃ N ₄ ) 26, a PSG film 25, and a silicon nitride film (Si ₃ N ₄ ) 15 are formed using a resist (not shown) as a mask layer. Sequential anisotropic dry etching is performed to form vias. Next, the resist (not shown) is removed.

Figure 32 (channel length direction)
Next, TiN27 to be a barrier metal is grown by chemical vapor deposition. Next, tungsten (W) 28 is grown by chemical vapor deposition. Next, a conductive plug (W) 28 having a barrier metal (TiN) 27 buried in the via is formed by chemical mechanical polishing (CMP).

1 (channel length direction) and FIG. 2 (channel width direction, channel region)
Next, an interlayer insulating film (SiOC) 29 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique using an exposure drawing apparatus, the interlayer insulating film (SiOC) 29 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 26 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 30 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded flat in the opening, and a Cu wiring 31 having a barrier metal (TaN) 30 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 32 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and a CMOS type semiconductor composed of N-channel and P-channel MIS field-effect transistors of the DISSSUG structure of the present invention. Complete the integrated circuit.

FIG. 33 is a schematic sectional side view of the second embodiment of the semiconductor device of the present invention, including a short channel N-channel and P-channel MIS field effect transistor formed in a DISSSUG structure using a silicon (Si) substrate. A part of a CMOS type semiconductor integrated circuit is shown, wherein 1-32 are the same as in FIG. 1, and 44 is a buried conductive film (WSi).
In the figure, an N channel having substantially the same structure as that in FIG. 1 except that a part of a semiconductor layer (a part of a source region) forming a P channel MIS field effect transistor is formed of a buried conductive film (WSi). And a P-channel MIS field effect transistor is formed.
In the present embodiment, the source region of the P-channel MIS field effect transistor can be performed by one ion implantation, and the same effect as in the first embodiment can be obtained.

34 to 38 show a third embodiment of the semiconductor device of the present invention. FIG. 34 is a schematic sectional side view, and FIGS. 35 to 38 are sectional views showing steps of the manufacturing method.
FIG. 34 is a schematic sectional side view of a third embodiment of the semiconductor device of the present invention, including a short channel N-channel and P-channel MIS field effect transistor formed in a DISSSUG structure using a silicon (Si) substrate. A part of the CMOS type semiconductor integrated circuit is shown, wherein 1-32 are the same as those in FIG. 1, and 45 is a silicon oxide film (SiO ₂ ) surrounding the holes.
In this figure, a silicon oxide film (SiO ₂ ) surrounding the holes is formed so that there is no hole directly under the source / drain region of the N-channel MIS field effect transistor. N-channel and P-channel MIS field effect transistors having the same structure are formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, although the capacitance between the source regions of the N-channel and P-channel MIS field effect transistors is slightly increased, N It is possible to further enhance the resistance to current leakage under the source / drain region of the channel MIS field effect transistor.

Next, a manufacturing method of the third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 35 to 38 and FIG.
After performing the steps of FIGS. 3 to 28 shown in the first embodiment, the steps of FIGS. 35 to 38 are performed.

35 (channel length direction) and FIG. 36 (channel width direction, source region portion)
Next, using a normal lithography technique by an exposure drawing apparatus, a silicon nitride film (Si ₃ N ₄ ) 15 (using a resist (not shown), the integrated surrounding gate electrode (WSi) 11 and the SiGe layer 18 as a mask layer) The silicon oxide film (SiO ₂ ) 14 and the silicon oxide film (SiO ₂ ) 14 are selectively and sequentially subjected to anisotropic dry etching so as to reach the holes 17 on both sides of the SiGe layer 18 in the width direction. About 40 nm). Next, the resist (not shown) is removed.

FIG. 37 (channel length direction) and FIG. 38 (channel width direction, source region)
Next, a silicon oxide film (SiO ₂ ) of about 20 nm is grown by chemical vapor deposition. Next, by performing anisotropic etching on the entire surface, the gap between the SiGe layer 18 and the silicon nitride film (Si ₃ N ₄ ) 15 is filled, and the lower surface of the SiGe layer 18 is integrated via the gate oxide film (HfO ₂ ) 10. Side surface of the middle part of the surrounding gate electrode (WSi) 11, side surface of the silicon oxide film (SiO ₂ ) 14 and conductive film (WSi) 16, and upper surface of the silicon nitride film (Si ₃ N ₄ ) 9 on the strained Ge layer 7 A silicon oxide film (SiO ₂ ) 45 having a thickness of about 20 nm is formed, and a hole 17 surrounded by the silicon oxide film (SiO ₂ ) 45 is provided, and an integrated surrounding gate through the gate oxide film (HfO ₂ ) 10 is provided. A sidewall (SiO ₂ ) 24 is formed on the side wall of the upper surface portion of the electrode (WSi) 11. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, arsenic ions are implanted to form n ⁺ -type source / drain regions (20, 23) using the sidewalls (SiO ₂ ) 24 and the integrated surrounding gate electrode (WSi) 11 as mask layers. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, annealing is performed by the RTP method to form n-type source / drain regions (21, 22), n ⁺ -type source / drain regions (20, 23), and p ⁺ -type source / drain regions (12, 13).

  Next, after performing the steps of FIGS. 31 to 32, the step of FIG. 34 (channel length direction) is performed.

FIG. 34 (channel length direction)
Next, an interlayer insulating film (SiOC) 29 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique using an exposure drawing apparatus, the interlayer insulating film (SiOC) 29 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 26 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 30 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded flat in the opening, and a Cu wiring 31 having a barrier metal (TaN) 30 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 32 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and a CMOS type semiconductor composed of N-channel and P-channel MIS field-effect transistors of the DISSSUG structure of the present invention. Complete the integrated circuit.

FIG. 39 is a schematic cross-sectional side view of a fourth embodiment of the semiconductor device of the present invention, including a short channel N-channel and P-channel MIS field effect transistor formed in a DISSSUG structure using a silicon (Si) substrate. A part of the CMOS type semiconductor integrated circuit is shown, and 1 to 6 and 8 to 32 are the same as those in FIG.
In this figure, the N channel having the same structure as that of FIG. 1 except that the lower semiconductor layer is formed in a structure in which a strained Ge layer forming a channel region is sandwiched between SiGe layers (Ge concentration of about 80%) from the left and right. And a P-channel MIS field effect transistor is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and the manufacturing method becomes somewhat simple. However, the strain Ge is subjected to the compressive stress of the SiGe layer having a small lattice constant (Ge concentration of about 80%). Since the lattice constant of the layer is somewhat reduced, the hole mobility is reduced, and the P-channel MIS field-effect transistor is slightly inferior in speed.

40 to 46 show a fifth embodiment of the semiconductor device of the present invention. FIG. 40 is a schematic sectional side view, and FIGS. 41 to 46 are sectional views of the manufacturing method.
FIG. 40 is a schematic sectional side view of a fifth embodiment of the semiconductor device of the present invention, including a short channel N-channel and P-channel MIS field effect transistor formed in a DISSSUG structure using a silicon (Si) substrate. 1 shows a part of a CMOS type semiconductor integrated circuit, wherein 1 to 5 and 8 to 32 are the same as those in FIG. 1, 46 is an n-type epitaxial Ge layer, 46a is a first epitaxially grown n-type Ge layer, and 46b. Is the second epitaxial growth n-type Ge layer, 47 is the n-type epitaxial Ge layer, 48 is a silicon nitride film (Si ₃ N ₄ ), 49 is a silicon oxide film (SiO ₂ ), and 50 is a selective chemical vapor deposition conductive film. (W) is shown.
In the figure, N-channel and P-channel MIS field effect transistors having substantially the same structure as in FIG. 1 are formed except that the lower semiconductor layer is entirely formed of a Ge layer.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, since the lower semiconductor layer can be formed only by the Ge layer, the mobility of holes can be further increased. Thus, it is possible to further increase the speed of the P-channel MIS field effect transistor.

Next, a manufacturing method of the fifth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 41 to 46 and FIG.
After performing the steps of FIGS. 3 to 9 shown in the first embodiment, the steps of FIGS. 41 to 46 are performed.

FIG. 41 (channel length direction)
Next, the Si layer 34 is anisotropically etched by about 20 nm to form an opening. Next, a silicon nitride film (Si ₃ N ₄ ) of about 20 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove the silicon nitride film (Si ₃ N ₄ ) grown on the strained Ge layer 7 and the silicon nitride film (Si ₃ N ₄ ) 5, and a nitride film (Si ₃ N ₄ ) 48 is embedded flat.

Fig. 42 (channel length direction)
Next, a silicon oxide film (SiO ₂ ) 49 of about 20 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, a silicon oxide film (SiO ₂ ) 49, a strained Ge layer 7 and a SiGe layer 6 are selectively and sequentially anisotropically dried using a resist (not shown) as a mask layer. Etching to form an opening. Next, the resist (not shown) is removed.

Fig. 43 (channel length direction)
Next, an n-type lateral (horizontal) epitaxial Ge layer 46 a is grown between the exposed side surfaces of the strained Ge layer 7 and the SiGe layer 6. (Because it grows epitaxially on the underlying insulating film barrier layer (TiN) 4, a complete single crystal germanium layer without the influence of the underlying insulating film can be obtained.) Next, 30 nm on the epitaxial Ge layer 46 a by selective chemical vapor deposition. A tungsten film 50 is grown to a degree.

FIG. 44 (channel length direction)
Next, the entire surface of the silicon oxide film (SiO ₂ ) 49 is subjected to anisotropic dry etching. Next, using the tungsten film 50 and the silicon nitride film (Si ₃ N ₄ ) (5, 48) as a mask layer, the strained Ge layer 7 and the SiGe layer 6 are sequentially subjected to anisotropic dry etching to form an opening.

Fig. 45 (channel length direction)
Next, an n-type lateral (horizontal) direction epitaxial Ge layer 46b is grown so as to fill the opening from the exposed side surface of the Ge layer 46a. (Because it grows epitaxially on the underlying insulating film barrier layer (TiN) 4, a complete single crystal germanium layer free from the influence of the underlying insulating film can be obtained.)

FIG. 46 (channel length direction)
Next, chemical mechanical polishing (CMP) is performed to remove the tungsten film 50 and planarize. Next, annealing is performed in a nitrogen atmosphere at about 1000 ° C. to form a Ge layer 46 without distortion.

  Next, after performing the steps of FIGS. 10 to 32, the step of FIG. 40 (channel length direction) is performed.

FIG. 40 (channel length direction)
Next, an interlayer insulating film (SiOC) 29 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique using an exposure drawing apparatus, the interlayer insulating film (SiOC) 29 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 26 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 30 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded flat in the opening, and a Cu wiring 31 having a barrier metal (TaN) 30 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 32 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and a CMOS type semiconductor composed of N-channel and P-channel MIS field-effect transistors of the DISSSUG structure of the present invention. Complete the integrated circuit.

FIG. 47 is a schematic sectional side view of the sixth embodiment of the semiconductor device of the present invention, including a short channel N-channel and P-channel MIS field effect transistor formed in a DISSSUG structure using a silicon (Si) substrate. A part of a CMOS type semiconductor integrated circuit is shown, wherein 1-32 are the same as those in FIG. 1, and 51 is a salicide layer (CoSi ₂ ).
In the figure, N-channel and P-channel structures having substantially the same structure as in FIG. 1 except that the source / drain region of the N-channel MIS field effect transistor formed in the upper semiconductor layer is formed in a so-called metal source / drain region. An MIS field effect transistor is formed.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method becomes somewhat complicated. However, the resistance of the source / drain region of the N-channel MIS field effect transistor is reduced by forming the metal source / drain region. Since it can be reduced, higher speed can be achieved.

FIG. 48 is a schematic sectional side view of the seventh embodiment of the semiconductor device of the present invention, including a short channel N-channel and P-channel MIS field effect transistor formed in a DISSSUG structure using a silicon (Si) substrate. A part of a CMOS type semiconductor integrated circuit is shown, and 1-32 shows the same thing as FIG.
In the figure, a fine CMOS of the drain region direct connection type N-channel and P-channel MIS field effect transistors having the same structure as that of the first embodiment is formed in the left half, and the right half has N A slightly larger CMOS is formed in which the drain regions of the channel and P-channel MIS field effect transistors are independently connected to the wiring layer.
In this embodiment, the same effect as that of the first embodiment can be obtained, and a configuration applicable to a 2-input NAND circuit or a 2-input NOR circuit in addition to the NOT circuit (inverter) is adopted. By using properly, it is possible to form an extremely highly integrated CMOS type semiconductor integrated circuit.

When the semiconductor layer is grown, not only by the normal chemical vapor deposition but also by the ECR plasma CVD method, the molecular beam growth method (MBE), the metal organic chemical vapor deposition method (MOCVD), the atomic layer Depending on the crystal growth method (ALE), any other crystal growth method may be used.
Although a Si substrate is used as a semiconductor substrate, the present invention is not limited to this, and a Ge substrate or a SiGe substrate may be used. In short, a device for changing the Ge concentration by interposing a SiGe layer may be used. That's fine.
Further, the Ge concentration described in the examples is only a guide and is not limited to this.
In addition, the gate electrode, gate oxide film, barrier metal, conductive plug, wiring, insulating film, base insulating film barrier layer, etc. are not limited to the above-described embodiments, and any material having similar characteristics may be used. May be.
In addition, although all of the above embodiments describe the case where an enhancement type MIS field effect transistor is formed, a depletion type MIS field effect transistor may be formed. In this case, an epitaxial semiconductor layer having the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing an epitaxial semiconductor layer and then ion-implanting an impurity of the opposite conductivity type to convert the conductivity type. A MIS field effect transistor may be formed.
The CMOS having the above structure can be applied to both an AND circuit and an OR circuit, and can be applied not only to two inputs but also to circuits having three or more inputs.

The present invention is particularly aimed at high-speed, high-reliability, and highly-integrated CMOS semiconductor integrated circuits. However, the present invention is not limited to high-speed and is used for all CMOS-type semiconductor integrated circuits equipped with MIS field effect transistors. It is possible to do.
Moreover, it can be used not only as a semiconductor integrated circuit but also as a single individual semiconductor element.
In addition to the MIS field effect transistor, there is a possibility that it can be used for other field effect transistors, TFTs for liquid crystals (Thin Film Transistor), and the like.

1 p-type silicon (Si) substrate 2 silicon nitride film (Si ₃ N ₄ )
3 Silicon oxide film (SiO ₂ )
4 Underlying insulating film barrier layer (TiN)
5 Silicon nitride film (Si ₃ N ₄ ) in element isolation region
6 n-type epitaxial SiGe layer (Ge concentration about 80%)
7 n-type epitaxial strained Ge layer 8 n-type epitaxial strained Ge layer 9 silicon nitride film (Si ₃ N ₄ )
10 Gate oxide film (HfO ₂ )
11 Integrated Surround Gate Electrode (WSi)
12 p ⁺ type source region 13 p ⁺ type drain region 14 Silicon oxide film (SiO ₂ )
15 Silicon nitride film (Si ₃ N ₄ )
16 Embedded conductive film (WSi, for side connection)
17 vacancies 18 p-type epitaxial SiGe layer (Ge concentration about 20%)
19 p-type epitaxial strained Si layer 20 n ⁺ type source region 21 n-type source region 22 n-type drain region 23 n ⁺ -type drain region 24 Side wall (SiO ₂ )
25 Phosphorsilicate glass (PSG) film 26 Silicon nitride film (Si ₃ N ₄ )
27 Barrier metal (TiN)
28 Conductive plug (W)
29 Interlayer insulation film (SiOC)
30 Barrier metal (TaN)
31 Cu wiring (including Cu seed layer)
32 Barrier insulating film (Si ₃ N ₄ )
33 Silicon nitride film (Si ₃ N ₄ )
34 n-type epitaxial Si layer 35 Selective chemical vapor deposition conductive film (W)
36 n-type epitaxial SiGe layer (Ge concentration about 20%)
37 Underlying insulating film barrier layer (TiN)
38 Silicon nitride film (Si ₃ N ₄ )
39 p-type epitaxial Si layer 40 selective chemical vapor deposition conductive film (W)
41 p-type epitaxial Si layer 42 silicon oxide film (SiO ₂ )
43 Silicon nitride film (Si ₃ N ₄ )
44 Embedded conductive film (WSi)
45 Silicon oxide film (SiO ₂ ) surrounding pores
46 n-type epitaxial Ge layer 46a n-type Ge layer for first epitaxial growth 46b n-type Ge layer for second epitaxial growth 47 n-type epitaxial Ge layer 48 silicon nitride film (Si ₃ N ₄ )
49 Silicon oxide film (SiO ₂ )
50 Selective chemical vapor deposition conductive film (W)
51 Salicide layer (CoSi ₂ )

Claims (4)

A lower-layer semiconductor having a planar structure comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a second semiconductor layer selectively provided on the insulating film and sandwiching the first semiconductor layer from the left and right a layer, wherein the lower semiconductor layer to provided an interlayer insulating film and the pores, from the interlayer insulating film and provided on the air hole, the fourth semiconductor layer sandwiched from the left and right of the third semiconductor layer An upper semiconductor layer having a flat plate structure, a gate insulating film provided all around the first semiconductor layer and the third semiconductor layer, and the first semiconductor layer and the An integrated surrounding gate electrode having a gate length that is equal to the entire circumference provided in a structure surrounding the third semiconductor layer, and provided in the second semiconductor layer in self-alignment with the integrated surrounding gate electrode a one conductivity type source and drain regions, the first A channel region provided in the semiconductor layer, and opposite conductivity type source drain regions self-aligned provided on the fourth semiconductor layer to said integrated encircling gate electrode, provided on the third semiconductor layer And a channel region, wherein at least the first semiconductor layer and the third semiconductor layer are made of different single element semiconductors.   The semiconductor device according to claim 1, wherein the second semiconductor layer includes a semiconductor layer having a two-layer structure. The semiconductor device according to claim 1, further comprising a base insulating film barrier layer made of a metal compound immediately below the second semiconductor layer.   4. The semiconductor according to claim 1, wherein one of the first semiconductor layer and the third semiconductor layer is single crystal germanium and the other is single crystal silicon. apparatus.