JP2015094997A - メモリシステムおよびメモリシステムのアセンブリ方法 - Google Patents
メモリシステムおよびメモリシステムのアセンブリ方法 Download PDFInfo
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Abstract
【解決手段】メモリパッケージに含まれる各メモリチップは、前記チップアドレスとの比較対象であるnビットの情報であって、自メモリチップを識別するための第1の情報を記憶する第1の記憶部と、nビットの前記第1の情報のうちの有効ビットを決定するための第2の情報を記憶する第2の記憶部と、前記第2の情報に基づいてnビットの前記第1の情報および前記チップアドレスの有効ビットを決定する制御部とを備える。
【選択図】図3
Description
図1に、メモリシステム100の構成例を示す。メモリシステム100は、ホストインタフェース2を介してホスト装置(以下、ホストと略す)1と接続され、ホスト1の外部記憶装置として機能する。ホスト1は、例えば、パーソナルコンピュータ、タブレット、スマートフォン、携帯電話、撮像装置などである。
(a)メモリパッケージ15に含まれる全てのメモリチップ#0〜#15のROM領域135のMCM140をMCM=4に変更設定すること
(b)MCM=4となるようにPCB上で、コントローラ20のCEピンCE0−CE3とメモリパッケージ15のCEピンCE0−CE7の配線接続を行って、メモリシステム100をアセンブリすること
を行う。但し、メモリシステム100の製造者は、LUN145の設定変更を行う必要はない。
(a)メモリパッケージ15に含まれる全てのメモリチップ#0〜#15のROM領域135のMCM140をMCM=8に変更設定すること
(b)MCM=8となるようにPCB上で、コントローラ20のCEピンCE0,CE1とメモリパッケージ15のCEピンCE0−CE7の配線を行って、メモリシステム100をアセンブリすること
を行う。但し、メモリシステム100の製造者は、LUN145の設定変更を行う必要はない。前述したように、(a)、(b)の順番はどちらを先にしても良い。
第2の実施形態においては、メモリシステム100の電源オンの度に、コントローラ20がMCMレジスタ140aの設定値を再設定するように、コントローラ20の制御シーケンスを変更する。
第3の実施形態では、MCMの変更に応じたIDコード出力を行うようにしている。NAND10は、IDコード出力という基本的な機能を持っている。コントローラ20からのIDコード読み出し要求に応じて、各メモリチップ#0〜#15は、製造者、プレーン数、電源電圧値などを含むIDコード情報を、コントローラ20に出力する。このIDコード情報の一つに、チップイネーブルCE当たりのメモリ容量を示す情報値がある。以下、この情報値を容量/CE情報という。そこで、第3の実施形態では、MCMの変更に応じた容量/CE情報を出力する。
Claims (7)
- 不揮発性のメモリセルアレイを有するメモリチップを複数個含むメモリパッケージと、
チップイネーブルおよびチップアドレスに基づいて前記メモリパッケージから1つのメモリチップを選択するコントローラとを備え、
前記各メモリチップは、
前記チップアドレスとの比較対象であるnビット(nは2以上の整数)の情報であって、自メモリチップを識別するための第1の情報を記憶する第1の記憶部と、
nビットの前記第1の情報のうちの有効ビットを決定するための第2の情報を記憶する第2の記憶部と、
前記第2の情報に基づいてnビットの前記第1の情報および前記チップアドレスの有効ビットを決定する制御部と、
を備えることを特徴とするメモリシステム。 - 前記第1の情報は、予め設定した所定個数まで複数のメモリチップを識別可能なビット数を有することを特徴とする請求項1に記載のメモリシステム。
- 前記制御部は、起動時に、各メモリチップのメモリセルアレイ領域に記憶されている前記第1および前記第2の情報を読み出して前記第1の記憶部および前記第2の記憶部に記憶することを特徴とする請求項1に記載のメモリシステム。
- 前記コントローラは、起動時に、前記第2の記憶部に第2の情報を設定するためのコマンドを前記メモリパッケージに送信することを特徴とする請求項1に記載のメモリシステム。
- 前記コマンドはブロードキャストコマンドであり、前記メモリパッケージ内の複数のメモリチップに一斉に送信されることを特徴とする請求項4に記載のメモリシステム。
- 前記制御部は、チップイネーブル当たりの記憶容量を示す第3の情報値を前記コントローラに出力する際、複数の異なる前記第2の情報値に対応して異なる値の第3の情報値を前記コントローラに出力することを特徴とする請求項1に記載のメモリシステム。
- 不揮発性のメモリセルアレイを有するメモリチップを複数個含むメモリパッケージと、チップイネーブルおよびチップアドレスに基づいて前記メモリパッケージから1つのメモリチップを選択するコントローラとをアセンブリするメモリシステムのアセンブリ方法において、
前記不揮発性のメモリセルアレイに記憶される第2の情報であって、前記チップアドレスとの比較対象であるnビット(nは2以上の整数)の第1の情報の有効ビットを決定するための第2の情報を変更設定する工程と、
変更設定される前記第2の情報に対応するようにコントローラのチップイネーブルピンと、メモリパッケージのチップイネーブルピンを配線接続する工程と、
を備えるメモリシステムのアセンブリ方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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WO2021106224A1 (ja) * | 2019-11-29 | 2021-06-03 | キオクシア株式会社 | 半導体記憶装置、及びメモリシステム |
JP7004033B1 (ja) | 2020-07-07 | 2022-01-24 | 日本電気株式会社 | 保管装置、保管システム、制御方法及びプログラム |
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US10198381B2 (en) | 2017-03-10 | 2019-02-05 | Toshiba Memory Corporation | Circuitry to alleviate printed circuit board routing congestion |
CN109634534B (zh) * | 2019-01-02 | 2022-04-01 | 威胜集团有限公司 | 存储芯片的容量快速判定方法 |
JP2022010482A (ja) | 2020-06-29 | 2022-01-17 | キオクシア株式会社 | メモリシステム |
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US20150131397A1 (en) | 2015-05-14 |
US9620218B2 (en) | 2017-04-11 |
US20160358656A1 (en) | 2016-12-08 |
US20160141033A1 (en) | 2016-05-19 |
US9286960B2 (en) | 2016-03-15 |
US9443595B2 (en) | 2016-09-13 |
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