JP2015070253A - Multiple piece forming wiring board - Google Patents

Multiple piece forming wiring board Download PDF

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JP2015070253A
JP2015070253A JP2013206452A JP2013206452A JP2015070253A JP 2015070253 A JP2015070253 A JP 2015070253A JP 2013206452 A JP2013206452 A JP 2013206452A JP 2013206452 A JP2013206452 A JP 2013206452A JP 2015070253 A JP2015070253 A JP 2015070253A
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conductor
wiring board
wiring
mother
plating
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JP6215636B2 (en
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志保 足柄
Shiho Ashigara
志保 足柄
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Kyocera Corp
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Kyocera Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a multiple piece forming wiring board that facilitates detection of short circuit and disconnection.SOLUTION: A multiple piece forming wiring board 1 includes: a mother board 2 for multiple piece forming which is formed of a plurality of laminated insulating layers, has a plurality of square-shaped wiring board regions 1a arrayed in a matrix on a main surface thereof and an outside region 1b of the wiring board regions 1a, and on a surface of which plated electrodes 3 are provided; first penetration conductors 4 that pass through at least one of the insulating layers to be derived to at least one of both main faces of the mother board 2 and provided at the outside region 1b; second penetration conductors 5 that are pass at least one of the insulating layers to be derived to at least one of both main faces of the mother board 2, provided at the outside region 1b next to the first penetration conductors 4 and electrically connected to the plated electrodes 3; and inner layer patterns 6 that are provided inside the mother board 2, electrically connected to the second penetration conductors 5 and have clearances 7 between the first penetration conductors 4 and the patterns.

Description

本発明は、母基板の中央部に電子部品を搭載するための配線基板領域が縦および横の少なくとも一方の並びに配列された多数個取り配線基板に関するものである。   The present invention relates to a multi-chip wiring board in which a wiring board region for mounting an electronic component in the center of a mother board is arranged in at least one of vertical and horizontal directions.

従来、半導体素子や水晶振動子等の電子部品を搭載するための配線基板は、例えば酸化アルミニウム質焼結体や樹脂等の電気絶縁材料から成る母基板にタングステンやモリブデン、銅等の金属粉末メタライズから成る配線導体が配置されることによって形成されている。そしてこのような配線基板上に電子部品を搭載するとともに、電子部品の各電極をはんだやボンディングワイヤ、金バンプ等の電気的接続手段を介して対応する配線導体に電気的に接続することによって電子装置が作製される。   Conventionally, wiring boards for mounting electronic components such as semiconductor elements and crystal resonators are made of metal powder metallization such as tungsten, molybdenum and copper on a mother board made of an electrically insulating material such as an aluminum oxide sintered body or resin. It is formed by arranging wiring conductors made of Electronic components are mounted on such a wiring board, and each electrode of the electronic component is electrically connected to a corresponding wiring conductor through electrical connection means such as solder, bonding wires, and gold bumps. A device is made.

このような配線基板は近年の電子装置の小型化の要求に伴い、その大きさが極めて小さなものとなってきており、複数の配線基板および電子装置を効率よく制作するために、中央部に複数の配線基板領域が縦横に配列された、いわゆる多数個取り配線基板を作製し、これを各配線基板領域の境界に沿って切断分割することによって作製するということが行われている。   Such wiring boards have become extremely small in size with the recent demand for miniaturization of electronic devices, and in order to efficiently produce a plurality of wiring boards and electronic devices, a plurality of wiring boards are provided in the central portion. A so-called multi-cavity wiring board in which the wiring board regions are arranged vertically and horizontally is manufactured, and is manufactured by cutting and dividing the wiring board regions along the boundaries of the wiring board regions.

また、このような多数個取り配線基板においては、配線基板領域に上記の配線導体の一部が配線基板領域の表面に露出して形成されており、複数の配線基板はそれぞれ導通している。配線基板領域を取り囲むように外側領域が設けられている。この外側領域には、例えば各配線基板領域の配線導体に電気的に接続された、めっき用の枠状パターン(めっき枠)が形成されている。また、この多数個取り配線基板をめっき浴に浸漬して、めっき用の枠状パターンを介して各配線導体に電流を供給することで、電解めっき法によって配線導体の露出した表面にめっき層を被着させる。なお、めっき用の枠状パターン(めっき枠)へのめっき用電流の供給は、母基板の外周縁にめっき用の枠状パターンに電気的に接続されためっき電極を形成しておき、このめっき電極に治具を接触させ、めっき用の電源から治具およびめっき電極を介してめっき用の枠状パターンに所定の電流を流すことによって行なわれる。   Further, in such a multi-piece wiring board, a part of the wiring conductor is formed in the wiring board region so as to be exposed on the surface of the wiring board region, and the plurality of wiring boards are electrically connected. An outer region is provided so as to surround the wiring board region. In this outer region, for example, a frame pattern for plating (plating frame) electrically connected to the wiring conductor of each wiring board region is formed. In addition, by dipping this multi-piece wiring board in a plating bath and supplying a current to each wiring conductor through a plating frame pattern, a plating layer is formed on the exposed surface of the wiring conductor by electrolytic plating. Adhere. The plating current is supplied to the plating frame pattern (plating frame) by forming a plating electrode electrically connected to the plating frame pattern on the outer periphery of the mother substrate. A jig is brought into contact with the electrode, and a predetermined current is passed from the power source for plating to the frame pattern for plating through the jig and the plating electrode.

そして、多数個取り配線基板は各配線基板領域毎に切断分割、あるいは各配線基板領域の上面に電子部品を搭載した後、配線基板領域毎に切断分割される。
(例えば、特許文献1参照)
Then, the multi-piece wiring board is cut and divided for each wiring board area, or after mounting an electronic component on the upper surface of each wiring board area, the wiring board area is cut and divided for each wiring board area.
(For example, see Patent Document 1)

特開平5−304370号JP-A-5-304370

しかしながら、近年の配線基板は更なる小型化および電子部品の高機能化により、配線基板の多ピン化および配線基板の内部の配線導体(内部配線層および貫通配線導体)の高密度化が要求されている。多ピン化および配線導体の高密度化により、複数の配線基板の内部配線層間のギャップや絶縁層を厚み方向に貫通している複数の貫通配線導体間のクリアランスの狭小化が進んできており、製造時のズレや配線導体を印刷する際に発生する配線導体のにじみ等によって、配線基板の内部において、結線の異なる配線導体間に短絡が発生する可能性があった。このとき、各配線基板領域の配線導体は、めっき用の枠状パタ
ーンを介して電気的に接続しているため、多数個取り配線基板の状態では電気チェック等の検査方法において結線の異なる配線導体間の短絡が検出できず、多数個取り配線基板状態での配線基板の良品/不良品を識別することが困難であった。
However, recent wiring boards are required to have more pins and higher density of wiring conductors (internal wiring layers and through wiring conductors) in the wiring board due to further miniaturization and higher functionality of electronic components. ing. With the increase in the number of pins and the density of wiring conductors, gaps between internal wiring layers of multiple wiring boards and clearances between multiple through-wiring conductors that penetrate the insulating layer in the thickness direction are progressing. There is a possibility that a short circuit may occur between wiring conductors with different connections inside the wiring board due to, for example, misalignment during manufacturing or bleeding of the wiring conductor that occurs when the wiring conductor is printed. At this time, since the wiring conductors of the respective wiring board regions are electrically connected via the frame pattern for plating, the wiring conductors having different connections in the inspection method such as the electrical check in the state of the multi-cavity wiring board. It was difficult to identify a non-defective product / defective product of the wiring board in the multi-cavity wiring board state.

本発明は、上記の従来技術の問題点に鑑み案出されたものであり、その目的は、配線基板領域内の配線導体間の短絡の可能性を容易に検出することができる多数個取り配線基板を提供することにある。   The present invention has been devised in view of the above-mentioned problems of the prior art, and its purpose is to provide a multi-piece wiring that can easily detect the possibility of a short circuit between wiring conductors in a wiring board region. It is to provide a substrate.

本発明の第1の多数個取り配線基板は、複数の絶縁層が積層されてなるとともに、中央
部に縦横に配列された複数の四角形状の配線基板領域と該配線基板領域の外側領域とを有しており、表面にめっき電極が設けられた多数個取り用の母基板と、前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に設けられた第1貫通導体と、前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に前記第1貫通導体と隣り合って設けられ、前記めっき電極と電気的に接続された第2貫通導体と、前記母基板の内部に設けられ、前記第2貫通導体と電気的に接続されており、前記第1貫通導体との間ではクリアランスを有する内層パターンと、を有している。
The first multi-cavity wiring board of the present invention is formed by laminating a plurality of insulating layers, and includes a plurality of rectangular wiring board regions arranged vertically and horizontally at a central portion and an outer region of the wiring substrate region. A plurality of mother substrates each having a plating electrode provided on a surface thereof, and are led to at least one of both main surfaces of the mother substrate through at least one of the insulating layers, The first through conductor provided in the outer region and at least one of the insulating layers are led out to at least one of both main surfaces of the mother board, and the first through conductor is adjacent to the outer region. A second penetrating conductor that is electrically connected to the plating electrode, and is provided inside the mother board and electrically connected to the second penetrating conductor; and Between the inner layer pattern with clearance and ,have.

本発明の第2の多数個取り配線基板は、複数の絶縁層が積層されてなるとともに、中央部に縦横に配列された複数の四角形状の配線基板領域と該配線基板領域の外側領域とを有しており、表面にめっき電極が設けられた多数個取り用の母基板と、前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に設けられた第1貫通導体と、前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に前記第1貫通導体と隣り合って設けられ、前記めっき電極と電気的に接続された第2貫通導体と、前記母基板の内部に設けられ、前記第1貫通導体と電気的に接続されており、前記第2貫通導体との間ではクリアランスを有する内層パターンと、を有している。   The second multi-cavity wiring board of the present invention comprises a plurality of insulating layers stacked, and a plurality of rectangular wiring board regions arranged vertically and horizontally at the center and an outer region of the wiring substrate region. A plurality of mother substrates each having a plating electrode provided on a surface thereof, and are led to at least one of both main surfaces of the mother substrate through at least one of the insulating layers, The first through conductor provided in the outer region and at least one of the insulating layers are led out to at least one of both main surfaces of the mother board, and the first through conductor is adjacent to the outer region. A second through conductor that is electrically connected to the plating electrode, and is electrically connected to the first through conductor, provided in the mother board, and the second through conductor; Inner layer pattern with clearance between , The has.

上記の第1の構成によれば、例えば複数の絶縁層を積層する際の製造時のズレによって配線基板領域内部で結線の異なる内部配線層と貫通配線導体、あるいは結線の異なる貫通配線導体が接触して短絡が起こった場合には、第1貫通導体とめっき電極に電気的に接続された内層パターンとが短絡するため、めっき層を被着させた際、第1貫通導体の露出した表面へのめっき層の被着の有無を確認することによって、配線基板領域内部において結線の異なる内部配線層と貫通配線導体間に短絡が発生している可能性を容易に検出することが可能となる。   According to the first configuration described above, for example, an internal wiring layer and a through wiring conductor having different connections in the wiring board region or a through wiring conductor having a different connection are in contact with each other due to a manufacturing deviation when stacking a plurality of insulating layers. When a short circuit occurs, the first through conductor and the inner layer pattern electrically connected to the plating electrode are short-circuited. Therefore, when the plating layer is deposited, the first through conductor is exposed to the exposed surface. By confirming the presence or absence of deposition of the plating layer, it is possible to easily detect the possibility that a short circuit has occurred between the internal wiring layer and the through wiring conductor having different connections in the wiring board region.

上記の第2の構成によれば、例えば複数の絶縁層を積層する際の製造時のズレによって配線基板領域内部で結線の異なる内部配線層と貫通配線導体、あるいは結線の異なる貫通配線導体が接触して短絡が起こった場合には、第1貫通導体と接続された内層パターンが、めっき電極に電気的に接続された第2貫通導体と短絡するため、めっき層を被着させた際、第1貫通導体の露出した表面へのめっき層の被着の有無を確認することによって、配線基板領域内部において結線の異なる内部配線層と貫通配線導体間に短絡が発生している可能性を容易に検出することが可能となる。   According to the second configuration, for example, an internal wiring layer and a through wiring conductor having different connections within the wiring board region or a through wiring conductor having a different connection are in contact with each other due to a manufacturing deviation when stacking a plurality of insulating layers. When the short circuit occurs, the inner layer pattern connected to the first through conductor is short-circuited to the second through conductor electrically connected to the plating electrode. By confirming whether or not the plating layer is deposited on the exposed surface of one through conductor, it is easy to detect the possibility of a short circuit between the internal wiring layer and the through wiring conductor having different connections in the wiring board region. It becomes possible to detect.

本発明の第1の実施形態に係る多数個取り配線基板の外観を示す上面図である。It is a top view which shows the external appearance of the multi-cavity wiring board which concerns on the 1st Embodiment of this invention. (a)は、図1のA部の要部拡大上面図であり、(b)は(a)の最上層の絶縁層と上から2つ目の絶縁層の間の平面透視図であり、(c)は(a)のX−X線に対応する縦断面図の一例である。(A) is the principal part enlarged top view of the A section of FIG. 1, (b) is a plan perspective view between the uppermost insulating layer of (a) and the second insulating layer from the top, (C) is an example of the longitudinal cross-sectional view corresponding to the XX line of (a). (a)、(b)、(c)ともに、本発明の多数個取り配線基板に積層ずれが生じた状態を示す、要部拡大断面図である。(A), (b), (c) is the principal part expanded sectional view which shows the state which the lamination | stacking shift | offset | difference produced in the multi-piece wiring board of this invention. (a)は、本発明の第2の実施形態に係る多数個取り配線基板の要部拡大上面図であり、(b)は(a)の最上層の絶縁層と上から2つ目の絶縁層の間の平面透視図であり、(c)は(a)のX−X線に対応する縦断面図の一例である。(A) is a principal part enlarged top view of the multi-piece wiring board based on the 2nd Embodiment of this invention, (b) is the uppermost insulating layer of (a), and the 2nd insulation from the top It is a plane perspective view between layers, (c) is an example of the longitudinal cross-sectional view corresponding to the XX line of (a). 本発明の第3の実施形態に係る多数個取り配線基板の外観を示す上面図である。It is a top view which shows the external appearance of the multi-cavity wiring board which concerns on the 3rd Embodiment of this invention. (a)は、図5のB部の要部拡大上面図であり、(b)は(a)のX−X線に対応する要部拡大縦断面図である。(A) is a principal part expanded top view of the B section of FIG. 5, (b) is a principal part expanded longitudinal sectional view corresponding to the XX line of (a). (a)は図6の絶縁層間αにおける上面透視図であり、(b)は図6の絶縁層間βにおける上面透視図である。FIG. 7A is a top perspective view of the insulating layer α in FIG. 6, and FIG. 7B is a top perspective view of the insulating layer β in FIG. 6. (a)は図6の絶縁層間γにおける上面透視図であり、(b)は図6の絶縁層間δ層における上面透視図である。FIG. 7A is a top perspective view of the insulating layer γ of FIG. 6, and FIG. 7B is a top perspective view of the insulating layer δ layer of FIG. 6.

以下、本発明のいくつかの例示的な実施形態について図面を参照して説明する。   Hereinafter, some exemplary embodiments of the present invention will be described with reference to the drawings.

(第1の実施形態)
図1〜図4を参照して本発明の第1の実施形態における多数個取り配線基板1について説明する。本実施形態における多数個取り配線基板1は、縦横に複数配列された配線基板領域1aと配線基板領域1aを囲うように配置された外側領域1bとを有する母基板2を備えている。外側領域1bにはめっき電極3と第1貫通導体4と第2貫通導体5とが設けられている。第1貫通導体4と第2貫通導体5とは、母基板2の主面の少なくとも一方に導出されている。多数個取り配線基板1は、母基板2の各絶縁層の表面と厚み方向とに形成された配線導体とを有している。多数個取り配線基板1は、いずれの方向が上方若しくは下方とされてもよいものであるが、便宜的に、縦断面視においては、直交座標系xyzを定義するとともに、z方向の正側を上方として、上面若しくは下面の語を用いるものとする。
(First embodiment)
With reference to FIGS. 1 to 4, the multi-cavity wiring board 1 according to the first embodiment of the present invention will be described. The multi-piece wiring board 1 in the present embodiment includes a mother board 2 having a plurality of wiring board areas 1a arranged in the vertical and horizontal directions and an outer area 1b arranged so as to surround the wiring board area 1a. A plating electrode 3, a first through conductor 4, and a second through conductor 5 are provided in the outer region 1b. The first through conductor 4 and the second through conductor 5 are led out to at least one of the main surfaces of the mother board 2. The multi-cavity wiring board 1 has wiring conductors formed on the surface and thickness direction of each insulating layer of the mother board 2. The multi-sided wiring board 1 may be either upward or downward, but for convenience, in the longitudinal sectional view, the orthogonal coordinate system xyz is defined and the positive side in the z direction is As used above, the word “upper surface” or “lower surface” is used.

多数個取り配線基板1は、母基板2の中央部に複数の配線基板領域1aが縦および横の並びに複数配列されており、これらの複数の配線基板領域1aの周囲に外側領域1bが設けられている。このような中央部に配線基板領域1aが複数配列された多数個取り配線基板1は、配線基板領域1aを個々に切断分割することによって、複数の矩形状の小型の配線基板を良好に作製することができる。なお、図1に示す例では、母基板2の中央部に縦方向に8列、横方向に4列の計32個の配線基板領域1aが配列されている。配線基板領域1aは、縦もしくは横のいずれか一方に2列の計2個配列されていればよく、縦方向の列のみまたは横方向の列のみの配列であってもよい。また、多数個取り配線基板1は複数の絶縁層を有した多層基板である。図2(c)および図4(c)に示す例において、多数個取り配線基板1は3層の絶縁層を有した例を示しているが、絶縁層は2層以上であれば何層であっても良い。   In the multi-cavity wiring board 1, a plurality of wiring board regions 1a are arranged in the vertical and horizontal directions at the center of the mother board 2, and an outer region 1b is provided around the wiring board regions 1a. ing. In such a multi-piece wiring board 1 in which a plurality of wiring board regions 1a are arranged in the central portion, a plurality of small rectangular wiring boards can be satisfactorily manufactured by cutting and dividing the wiring board regions 1a individually. be able to. In the example shown in FIG. 1, a total of 32 wiring board regions 1 a are arranged in the central portion of the mother board 2 in 8 rows in the vertical direction and 4 rows in the horizontal direction. The wiring board region 1a only needs to be arranged in a total of two rows in either the vertical or horizontal direction, and may be an arrangement of only the vertical columns or only the horizontal columns. The multi-piece wiring board 1 is a multilayer board having a plurality of insulating layers. In the example shown in FIG. 2C and FIG. 4C, the multi-piece wiring board 1 shows an example in which three insulating layers are provided. There may be.

母基板2は例えば、酸化アルミニウム質焼結体,ムライト質焼結体,炭化珪素質焼結体,窒化アルミニウム質焼結体,窒化珪素質焼結体,ガラスセラミックス焼結体等の電気絶縁性セラミックス、またはエポキシ樹脂,ポリイミド樹脂,アクリル樹脂,フェノール樹脂,ポリエステル樹脂または四フッ化エチレン樹脂を始めとするフッ素系樹脂等の樹脂(プラスティックス)から成る略四角形の絶縁層を複数上下に積層して形成されている。   The base substrate 2 is made of, for example, an electrical insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a silicon nitride sintered body, or a glass ceramic sintered body. A plurality of substantially rectangular insulating layers made of ceramics or plastics such as epoxy resin, polyimide resin, acrylic resin, phenol resin, polyester resin or tetrafluoroethylene resin (plastics) are stacked up and down. Is formed.

各配線基板領域1aには、母基板2の各絶縁層の表面と厚み方向とに形成された配線導
体が形成されている。配線導体は、複数の配線基板に分割した際に搭載される電子部品と外部回路基板とを電気的に接続するための導通路として用いられる。配線導体は、母基板2の絶縁層間に形成された内部配線層と、絶縁層の厚み方向に形成した貫通配線導体とを有している。
In each wiring board region 1a, wiring conductors formed on the surface and thickness direction of each insulating layer of the mother board 2 are formed. The wiring conductor is used as a conduction path for electrically connecting an electronic component mounted when divided into a plurality of wiring boards and an external circuit board. The wiring conductor has an internal wiring layer formed between the insulating layers of the mother board 2 and a through wiring conductor formed in the thickness direction of the insulating layer.

外側領域1bには、少なくとも母基板2の一方主面に露出した端部を有する第1貫通導体4および第2貫通導体5と、第2貫通導体5に電気的に接続された内層パターン6と、第2貫通導体5に電気的に接続されためっき電極3とが設けられている。また、各配線基板領域1aの一方主面には凹部や配線導体が設けられていてもよく、配線導体は、他方主面や個々の配線基板に分割した際に、配線基板の側面となる領域に設けられていてもよい。   The outer region 1b includes at least a first through conductor 4 and a second through conductor 5 having end portions exposed on one main surface of the mother board 2, and an inner layer pattern 6 electrically connected to the second through conductor 5. The plating electrode 3 electrically connected to the second through conductor 5 is provided. Further, a concave portion or a wiring conductor may be provided on one main surface of each wiring board region 1a, and the wiring conductor is a region that becomes a side surface of the wiring board when divided into the other main surface or individual wiring boards. May be provided.

めっき電極3は配線基板領域1aに設けられた配線導体とめっき用の電源に接続された治具とを電気的に接続するためのものである。図1〜図4に示す例では、めっき電極3は、多数個取り配線基板1の外辺に設けた切欠き部の内面に形成されている。これらのめっき電極3は母基板2がセラミックスから成る場合、セラミックグリーンシートを金型等で打ちぬいて切欠き部となる貫通孔を形成した後、この貫通孔内面に、後述する配線導体と同様の材料および同様の方法でめっき電極3を形成し、この貫通孔を分断することによって形成する。また、めっき電極3は多数個取り配線基板1が樹脂から成る場合には、予め貫通孔を備えた母基板2として形成しておくか、母基板2を多数個取り配線基板1を略平板上に形成した後にレーザー加工などを用いて貫通孔を形成した後、貫通孔の内面に、母基板2が樹脂である場合に使用する配線導体と同様の材料及び同様の方法でめっき電極3を形成し、この貫通孔を分断することによって形成できる。   The plating electrode 3 is for electrically connecting a wiring conductor provided in the wiring board region 1a and a jig connected to a power source for plating. In the example shown in FIGS. 1 to 4, the plating electrode 3 is formed on the inner surface of a notch provided on the outer side of the multi-piece wiring board 1. In the case where the mother substrate 2 is made of ceramic, these plating electrodes 3 are formed by punching a ceramic green sheet with a mold or the like to form a through hole that becomes a notch, and then, on the inner surface of the through hole, the same as the wiring conductor described later The plating electrode 3 is formed by the same material and the same method, and the through hole is divided. Further, when the multi-piece wiring board 1 is made of resin, the plating electrodes 3 are formed in advance as a mother board 2 having through holes, or a large number of the mother boards 2 are taken so that the wiring board 1 is substantially flat. After forming the through hole using laser processing or the like, the plating electrode 3 is formed on the inner surface of the through hole by the same material and the same method as the wiring conductor used when the mother board 2 is resin. And it can form by dividing this through-hole.

また、図1〜図4に示す例においては、めっき電極3は切欠き部の内面に設けているが、外側領域1bに貫通孔を形成しておき、この貫通孔の内面に形成しても構わない。このようにめっき電極3を切欠き部あるいは貫通孔の内面に形成しておくと、めっき用の電源に接続された治具との接触を容易に行うことができ、精度よくめっき層を被着することができる。   Moreover, in the example shown in FIGS. 1-4, although the plating electrode 3 is provided in the inner surface of a notch part, a through-hole is formed in the outer side area | region 1b, and it may form in the inner surface of this through-hole. I do not care. When the plating electrode 3 is formed on the inner surface of the notch or the through hole in this way, the contact with the jig connected to the power source for plating can be easily performed, and the plating layer is applied with high accuracy. can do.

図2(c)に示す例のように、第2貫通導体5は各絶縁層間にて各内層パターン6と電気的に接続しており、各内層パターン6は、第1貫通導体との間に幅Gのクリアランス7が設けられている。また、第2貫通導体5はめっき電極3に電気的に接続しており、第1
貫通導体4と内層パターン6とは電気的に導通していない。この状態が多数個取り配線基板1の正常状態を示している。つまり、正常な状態での多数個取り配線基板1をめっき浴に浸漬し、電解めっき法によりめっき層を被着させた際には、第1貫通導体4の露出する表面にはめっき層は被着されず、第2貫通導体5の露出する表面にはめっき層が被着される。
2C, the second through conductor 5 is electrically connected to each inner layer pattern 6 between each insulating layer, and each inner layer pattern 6 is connected to the first through conductor. A clearance 7 having a width G is provided. Further, the second through conductor 5 is electrically connected to the plating electrode 3, and the first
The through conductor 4 and the inner layer pattern 6 are not electrically connected. This state indicates the normal state of the multi-piece wiring board 1. That is, when the multi-piece wiring board 1 in a normal state is immersed in a plating bath and a plating layer is deposited by an electrolytic plating method, the plating layer is not covered on the exposed surface of the first through conductor 4. A plating layer is applied to the exposed surface of the second through conductor 5 without being attached.

図2(c)に示す例では、第1貫通導体4および第2貫通導体5の露出した表面にめっき層が被着された状態を横線のハッチングにより示しており、めっき層が被着されていない状態を白抜きにて示している。このことによって、目視または画像検査にて第1貫通導体4および第2貫通導体5の露出した表面へのめっき層の被着の有無を確認することによって、多数個取り配線基板1の状態にて、最上層の絶縁層と上から2つ目の絶縁層との層間又は他の層間でずれが発生し、これらの絶縁層間にて結線の異なる配線導体間の短絡が発生している可能性を確認することができる。   In the example shown in FIG. 2C, the state in which the plating layer is applied to the exposed surfaces of the first through conductor 4 and the second through conductor 5 is indicated by horizontal hatching, and the plating layer is applied. No state is shown in white. By confirming the presence or absence of the plating layer on the exposed surface of the first through conductor 4 and the second through conductor 5 by visual inspection or image inspection, it is possible to obtain the multi-piece wiring board 1 in the state. There is a possibility that a gap has occurred between the uppermost insulating layer and the second insulating layer from the top or other layers, and a short circuit has occurred between wiring conductors with different connections between these insulating layers. Can be confirmed.

また、前述した正常な状態とは、図2(c)で示すように、第1貫通導体4と内層パターンとがショートしておらず、第2貫通導体5で断線が生じていない状態を意味する。この状態のときは、図2(c)で示すように、第1貫通導体4の露出端部にめっき層が被着
しておらず、かつ、第2貫通導体5の露出端部にめっき層が被着されている。
The normal state described above means a state in which the first through conductor 4 and the inner layer pattern are not short-circuited and the second through conductor 5 is not disconnected as shown in FIG. To do. In this state, as shown in FIG. 2C, the plating layer is not deposited on the exposed end portion of the first through conductor 4, and the plating layer is formed on the exposed end portion of the second through conductor 5. Is attached.

反対に、後述するが、正常でない状態の場合には、図3(a)〜(c)に示す例のように、第1貫通導体4の露出端部にめっき層が被着しているか、または、第2貫通導体5の露出端部にめっき層が被着されていない。   Conversely, as will be described later, in the case of an abnormal state, as in the example shown in FIGS. 3A to 3C, is the plating layer deposited on the exposed end of the first through conductor 4, Alternatively, the plating layer is not deposited on the exposed end portion of the second through conductor 5.

図3(a)および図3(b)に、本発明の多数個取り配線基板1を構成する絶縁層間にズレが生じた場合の一例を示す。図3(a)に示す例は、複数の絶縁層を積層して加圧する際に最上層の絶縁層が2つめの絶縁層よりも左側にずれた状態を示している。この状態では、最上層の絶縁層と2つめの絶縁層との間で、内層パターン6が最上層の第1貫通導体4に接触している。このような状態の多数個取り配線基板1を、電解めっき法を用いてめっき層を被着させると、2つめの絶縁層の第2貫通導体5と内層パターン6を介して、第1貫通導体4aの露出した表面にもめっき層が被着される。また、その他の第1貫通導体4bは内層パターン6と接していないため、めっき層が被着されない。   FIG. 3A and FIG. 3B show an example in the case where a deviation occurs between the insulating layers constituting the multi-piece wiring board 1 of the present invention. The example shown in FIG. 3A shows a state in which the uppermost insulating layer is shifted to the left side with respect to the second insulating layer when a plurality of insulating layers are stacked and pressed. In this state, the inner layer pattern 6 is in contact with the uppermost first through conductor 4 between the uppermost insulating layer and the second insulating layer. When a plating layer is deposited on the multi-piece wiring board 1 in such a state by using an electrolytic plating method, the first through conductor is passed through the second through conductor 5 and the inner layer pattern 6 of the second insulating layer. A plating layer is also deposited on the exposed surface of 4a. Further, since the other first through conductors 4b are not in contact with the inner layer pattern 6, the plating layer is not deposited.

また図3(a)に示す例では、第2貫通導体5aは、まだ断線するに至っていない。しかし、断線するに至っていない場合であっても、一定量ずれが生じてしまうと、例えば、配線基板領域1a内の貫通配線導体は、電気抵抗等の特性を維持できなくなってしまう場合がある。従って、断線するに至っていない場合であって、かつ、所定のずれ量を検出する必要がある。そのような場合には、クリアランス7の幅Gを、貫通配線導体の接合の信頼性の為に必要な幅と同一にすれば良い。このような構成により、例えば図3(a)の示す例においては、第2貫通導体5aで断線していないものの、第1貫通導体4aの母基板
2に露出した面にめっきが被着しているので、断線はしていないものの、貫通配線導体が電気抵抗等の特性を維持できなくなっている状態であり不良品であることを確認することができる。
In the example shown in FIG. 3A, the second through conductor 5a has not yet been disconnected. However, even if the wire has not been disconnected, if a certain amount of deviation occurs, for example, the through wiring conductor in the wiring board region 1a may not be able to maintain characteristics such as electrical resistance. Accordingly, it is necessary to detect a predetermined deviation amount even when the wire has not been disconnected. In such a case, the width G of the clearance 7 may be made the same as the width required for the reliability of joining of the through wiring conductors. With such a configuration, for example, in the example shown in FIG. 3A, although the second through conductor 5a is not disconnected, the plating is applied to the surface of the first through conductor 4a exposed on the mother board 2. Therefore, although there is no disconnection, it is possible to confirm that the through-wiring conductor cannot maintain the characteristics such as electric resistance and is a defective product.

図3(b)に示す例において、図3(a)に示した例よりも、最上層の絶縁層が2つめの絶縁層よりも大きく左側にずれた状態を示している。この状態では、最上層の絶縁層と2つめの絶縁層との間で、内層パターン6が最上層の第1貫通導体4に接触しており、内層パターン6が最上層の第2貫通導体5に接触していない。このような状態の多数個取り配線基板1を、電解めっき法を用いてめっき層を被着させると、めっき電極3に電気的に接続している2つ目の絶縁層の第2貫通導体5aと内層パターン6とを介して、最上層の、第1貫通導体4aの露出した表面にもめっき層が被着される。また、その他の第1貫通導体4bは内層パターン6と接触していないため、めっき層が被着されない。また、最上層の第2貫通導体5aは2つめの絶縁層の第2貫通導体5aとはズレにより電気的な接続がされていないため、第2貫通導体5aの露出する表面にはめっき層は被着されない。つまり、目視または画像検査にて第2貫通導体5aの露出した表面へのめっき層の被着の有無を確認することによって、同じ結線である第2貫通導体5a同士で断線が発生するほどのズレが発生していることを確認することができ、第1貫通導体4aのみに配線導体の印刷時のにじみなどによるものではなく、全体的にズレが生じていることを確認することができる。   In the example shown in FIG. 3B, the uppermost insulating layer is shifted to the left more than the second insulating layer as compared with the example shown in FIG. In this state, the inner layer pattern 6 is in contact with the uppermost first through conductor 4 between the uppermost insulating layer and the second insulating layer, and the inner layer pattern 6 is the uppermost second through conductor 5. Not touching. When a plating layer is deposited on the multi-piece wiring board 1 in such a state using an electrolytic plating method, the second through conductor 5a of the second insulating layer electrically connected to the plating electrode 3 is used. The plating layer is also applied to the exposed surface of the first through conductor 4a, which is the uppermost layer, through the inner layer pattern 6. Further, since the other first through conductors 4b are not in contact with the inner layer pattern 6, the plating layer is not deposited. Further, since the uppermost second through conductor 5a is not electrically connected to the second through conductor 5a of the second insulating layer by displacement, a plating layer is not formed on the exposed surface of the second through conductor 5a. Not attached. In other words, by confirming the presence or absence of deposition of the plating layer on the exposed surface of the second through conductor 5a by visual inspection or image inspection, a deviation that causes the disconnection between the second through conductors 5a having the same connection is generated. It is possible to confirm that the occurrence of the occurrence of the ink is not generated due to bleeding at the time of printing the wiring conductor only on the first through conductor 4a, and it is possible to confirm that the displacement is generated as a whole.

図3(c)に示す例において、めっき電極3に電気的に接続している第2貫通導体5aに接続されている内層パターン6と、第1貫通導体4aとは電気的に接続していない状態を示している。このような状態の多数個取り配線基板1を、電解めっき法を用いてめっき層を被着させると、第1貫通導体4aの露出する表面と第2貫通導体5aの露出する表面とにはにめっき層が被着されない。このことから、第1貫通導体4aだけを確認する場合
には、多数個取り配線基板1が正常な状態であるとして誤検出してしまう可能性があるが、第2貫通導体5aも確認することで、多数個取り配線基板1が正常な状態でない可能性を確認することができる。
In the example shown in FIG. 3C, the inner layer pattern 6 connected to the second through conductor 5a electrically connected to the plating electrode 3 and the first through conductor 4a are not electrically connected. Indicates the state. When a plating layer is applied to the multi-piece wiring board 1 in such a state using an electrolytic plating method, the exposed surface of the first through conductor 4a and the exposed surface of the second through conductor 5a The plating layer is not deposited. From this, when only the first through conductor 4a is confirmed, there is a possibility that the multi-piece wiring board 1 is erroneously detected as being in a normal state, but the second through conductor 5a is also confirmed. Thus, the possibility that the multi-piece wiring board 1 is not in a normal state can be confirmed.

なお、上述の例では、最上層の絶縁層と2つめの絶縁層とにズレが発生した例を示しているが、2つめの絶縁層と3つめの絶縁層とにズレが発生した場合等、他の絶縁層間にズレが発生した状態においても、上述の場合と同様に考えることができる。   In the above example, an example is shown in which a deviation occurs between the uppermost insulating layer and the second insulating layer. However, when a deviation occurs between the second insulating layer and the third insulating layer, etc. Even in a state where a deviation occurs between other insulating layers, it can be considered in the same manner as described above.

クリアランス7の幅Gは、例えば母基板2がセラミックから成る場合、母基板2となる複数のセラミックグリーンシートを積層加圧する工程を含んだ全行程において許容できるズレ量と同程度にしておくと、製造時に許容量以上のズレが生じた場合においてもズレを検出でき、信頼性の高い多数個取り配線基板1を提供することが可能となり、内部配線層と貫通配線導体との短絡の確認は目視もしくは画像検査機等で検出することが可能となる。この許容できるズレ量は、例えば貫通配線導体の径の半分程度である。   For example, when the mother board 2 is made of ceramic, the width G of the clearance 7 is approximately equal to the amount of deviation that can be allowed in the entire process including the step of laminating and pressing a plurality of ceramic green sheets to be the mother board 2. Even when a deviation larger than the allowable amount occurs during manufacturing, it is possible to detect the deviation, and to provide a highly reliable multi-piece wiring board 1. Visual confirmation of a short circuit between the internal wiring layer and the through wiring conductor is possible. Alternatively, it can be detected by an image inspection machine or the like. The allowable deviation amount is, for example, about half of the diameter of the through wiring conductor.

また、前述したように、母基板2には複数の配線導体が設けられており、クリアランスGは、配線導体どうしの最小の間隔と同程度であることが好ましい。各絶縁層間において、クリアランス7の幅Gを配線基板領域1aの中でも隣り合う内部配線層や貫通配線導体等との間、あるいは結線が異なる貫通配線導体間の距離が最も小さい距離と同程度にすることにおいて、配線基板領域1a内部で結線が異なる内部配線層と貫通配線導体との間、あるいは結線が異なる貫通配線導体間に短絡が起きた場合、より精度よく検出することが可能となる。   As described above, the mother board 2 is provided with a plurality of wiring conductors, and the clearance G is preferably about the same as the minimum interval between the wiring conductors. Between each insulating layer, the width G of the clearance 7 is set to the same distance as the smallest distance between adjacent internal wiring layers and through wiring conductors in the wiring board region 1a, or between through wiring conductors having different connections. In this regard, when a short circuit occurs between the internal wiring layer and the through wiring conductor having different connections within the wiring board region 1a, or between the through wiring conductors having different connections, it becomes possible to detect with higher accuracy.

また、第2貫通導体5の径は、配線基板領域1aの各絶縁層における貫通配線導体の最小の径以下としていると、第2貫通導体5の上下の電気的接続が配線基板領域1aのズレによる影響と同程度の影響をうけ、配線基板領域1aの状態と類似した状態となるため、より精度よく配線基板領域1a内の同じ結線であるはずの内部配線層と貫通配線導体との断線、あるいは同じ結線であるはずの貫通導体間の断線を確認することが可能となる。   Further, if the diameter of the second through conductor 5 is set to be equal to or smaller than the minimum diameter of the through wiring conductor in each insulating layer of the wiring board region 1a, the upper and lower electrical connections of the second through conductor 5 are shifted from the wiring board region 1a. Is affected by the same degree of influence as the state of the wiring board region 1a, and thus the disconnection between the internal wiring layer and the through wiring conductor, which should be the same connection in the wiring board region 1a, more accurately. Or it becomes possible to confirm the disconnection between the penetration conductors which should be the same connection.

また、第1貫通導体4および第2貫通導体5は、母基板2の4つの角部周辺のすべてに
設けられていることが好ましい。第1貫通導体4と第2貫通導体5とのペアPを多数個取り配線基板1の角部に設けることで、例えば母基板2がセラミックスから成る場合において、母基板2の中央部に設けられた配線基板領域1a内で配線導体同士が短絡する値の境界値付近であったとしても、配線導体同士が短絡しているもしくは短絡する可能性がある多数個取り配線基板1を検出することができる。これは、母基板2がセラミックスから成る場合、積層して加圧する工程において角部周辺がもっともズレや変形の影響を大きく受けやすく、第1貫通導体4の変動が中央部に配置される配線基板領域1aよりも大きく出るためである。このことによって、より検出の精度を高めることができる。
Further, the first through conductor 4 and the second through conductor 5 are preferably provided around all four corners of the mother board 2. By providing a large number of pairs P of the first through conductors 4 and the second through conductors 5 at the corners of the wiring board 1, for example, when the mother board 2 is made of ceramics, it is provided at the center of the mother board 2. Even in the vicinity of the boundary value of the values at which the wiring conductors are short-circuited in the wiring board region 1a, it is possible to detect a multi-piece wiring board 1 in which the wiring conductors are short-circuited or possibly short-circuited. it can. This is because, when the mother board 2 is made of ceramics, the wiring board in which the periphery of the corner is most susceptible to displacement and deformation in the process of laminating and pressing, and the variation of the first through conductor 4 is arranged in the center. This is because it appears larger than the area 1a. As a result, the detection accuracy can be further improved.

また、第1貫通導体4と第2貫通導体5とのペアPが多数個取り配線基板1の4つの角部周辺にそれぞれ設けることで、例えば多数個取り配線基板1がセラミックスから成り、1つの角部のみにペアPがある場合においては、配線導体などのメタライズペーストをスクリーン印刷等でセラミックグリーンシートに印刷する際にメタライズペーストのノビやニジミが発生した場合や、積層して加圧を行う際にセラミックグリーンシートに局所的な変形が起きた場合など、配線基板領域1aにおいては不具合が見られないが、第1貫通導体4にめっき層が被着する、もしくは、第2貫通導体5にめっき層が被着しない事例が発生する可能性がある。このとき、同じ絶縁層間のズレを検出するペアPを4つの角部周辺の同一の絶縁層間にそれぞれ設けられていることで、ペアPにて検出された不具合が多数個取り配線基板1全体で起こっている現象であるのか、不具合が検出されたペアPのみもしくは一部分で起きている現象であるのかを確認することができ、正常な状態でない多数個取り配線基板1が正常な状態であるものとして誤検出してしまう可能性を低減させることができる。   Further, by providing a plurality of pairs P of the first through conductors 4 and the second through conductors 5 around the four corners of the wiring board 1, for example, the multi-wiring board 1 is made of ceramics. When there is a pair P only at the corners, when metallized paste such as a wiring conductor is printed on a ceramic green sheet by screen printing or the like, or when the metallized paste is distorted or smeared, it is stacked and pressed When a local deformation occurs in the ceramic green sheet at this time, no defect is observed in the wiring board region 1a, but a plating layer is deposited on the first through conductor 4 or the second through conductor 5 There may be cases where the plating layer is not deposited. At this time, the pair P for detecting the deviation between the same insulating layers is provided between the same insulating layers around the four corners, so that a large number of defects detected in the pair P can be obtained in the entire wiring board 1. It is possible to confirm whether this is a phenomenon that has occurred or only a part of the pair P in which a defect has been detected, or a part of the wiring board 1 that is not in a normal state. As a result, it is possible to reduce the possibility of erroneous detection.

また、ペアPは検出する同じ絶縁層を確認する第1貫通導体4と第2貫通導体5とが隣接し、かつ同一面に露出していることが好ましい。これは目視や画像検査における外観検査において、めっき層が被着しているか否かを容易に比較することができ、また画像検査を用いる場合において、配線基板領域1a内の配線導体間にて短絡または断線が発生している可能性を1回で確認することができる為である。   In the pair P, it is preferable that the first through conductor 4 and the second through conductor 5 that confirm the same insulating layer to be detected are adjacent to each other and exposed on the same surface. This can easily compare whether or not the plating layer is applied in visual inspection or visual inspection in image inspection. In addition, when using image inspection, a short circuit occurs between the wiring conductors in the wiring board region 1a. This is because the possibility of occurrence of disconnection can be confirmed once.

第1貫通導体4、第2貫通導体5、内層パターン6、配線導体は、母基板2がセラミックスから成る場合には、タングステン(W),モリブデン(Mo),マンガン(Mn),銀(Ag)または銅(Cu)等のメタライズから成る。また、第1貫通導体4、第2貫通導体5、内層パターン6、配線導体は、母基板2が樹脂から成る場合には、銅(Cu),金(Au),アルミニウム(Al),ニッケル(Ni),クロム(Cr),モリブデン(Mo)またはチタン(Ti)およびそれらの合金等の金属材料から成る。   The first through conductor 4, the second through conductor 5, the inner layer pattern 6, and the wiring conductor are tungsten (W), molybdenum (Mo), manganese (Mn), silver (Ag) when the mother board 2 is made of ceramics. Or it consists of metallization, such as copper (Cu). Further, the first through conductor 4, the second through conductor 5, the inner layer pattern 6, and the wiring conductor are copper (Cu), gold (Au), aluminum (Al), nickel (when the mother board 2 is made of resin). It is made of a metal material such as Ni), chromium (Cr), molybdenum (Mo) or titanium (Ti) and alloys thereof.

母基板2の主面に露出している配線導体を保護して酸化防止をするとともに、電子部品や外部回路基板との電気的接続を良好なものとするために母基板2の主面に露出している配線導体の表面に、厚さ0.5〜10μmのNiめっき層を被着させるか、またはこのNiめ
っき層および厚さ0.5〜3μmの金(Au)めっき層を順次被着させる。
In order to protect the wiring conductor exposed on the main surface of the mother board 2 and prevent oxidation, and to improve electrical connection with electronic components and external circuit boards, it is exposed on the main surface of the mother board 2. The Ni plating layer having a thickness of 0.5 to 10 μm is deposited on the surface of the wiring conductor, or the Ni plating layer and the gold (Au) plating layer having a thickness of 0.5 to 3 μm are sequentially deposited.

なお、配線導体は、第2貫通導体5と同様に、同じめっき電極3に接続しておくことで、電解めっき法により、母基板2の表面に露出した配線導体に電解めっき層を被着させるとともに、第1貫通導体4または第2貫通導体5への電解めっき層への被着状態により、多数個取り配線基板1における短絡及び断線の状態を確認することができる。   The wiring conductor is connected to the same plating electrode 3 in the same manner as the second through conductor 5, so that an electrolytic plating layer is deposited on the wiring conductor exposed on the surface of the mother board 2 by electrolytic plating. At the same time, the state of short circuit and disconnection in the multi-piece wiring board 1 can be confirmed by the state of the first through conductor 4 or the second through conductor 5 attached to the electrolytic plating layer.

次に、本実施形態の多数個取り配線基板1の製造方法について説明する。   Next, a method for manufacturing the multi-cavity wiring board 1 of this embodiment will be described.

(1)まず、母基板2を構成するセラミックグリーンシートを形成する。例えば、酸化アルミニウム(Al)質焼結体である母基板2を得る場合には、Alの粉末に焼結助材としてシリカ(SiO),マグネシア(MgO)またはカルシア(CaO)等の粉末を添加し、さらに適当なバインダー、溶剤および可塑剤を添加し、次にこれらの混合物を混錬してスラリー状となす。その後、従来周知のドクターブレード法またはカレンダーロール法等の成形方法によって多数個取り用のセラミックグリーンシートを得る。 (1) First, a ceramic green sheet constituting the mother board 2 is formed. For example, when obtaining the mother substrate 2 which is an aluminum oxide (Al 2 O 3 ) sintered material, silica (SiO 2 ), magnesia (MgO) or calcia (as a sintering aid) is added to the Al 2 O 3 powder. A powder such as CaO) is added, an appropriate binder, a solvent and a plasticizer are added, and then the mixture is kneaded to form a slurry. Thereafter, a ceramic green sheet for multi-piece production is obtained by a conventionally known forming method such as a doctor blade method or a calender roll method.

なお、母基板2が、例えば樹脂から成る場合は、所定の形状に成形できるような金型を用いて、トランスファーモールド法またはインジェクションモールド法等によって成形することによって母基板2を形成することができる。また、母基板2は、例えばガラスエポキシ樹脂のように、ガラス繊維から成る基材に樹脂を含浸させたものであってもよい。この場合には、ガラス繊維から成る基材にエポキシ樹脂の前駆体を含浸させ、このエポキシ樹脂前駆体を所定の温度で熱硬化させることによって母基板2を形成できる。   When the mother board 2 is made of, for example, a resin, the mother board 2 can be formed by molding by a transfer molding method or an injection molding method using a mold that can be molded into a predetermined shape. . Further, the mother board 2 may be obtained by impregnating a base material made of glass fiber with a resin, such as glass epoxy resin. In this case, the mother substrate 2 can be formed by impregnating a base material made of glass fiber with an epoxy resin precursor and thermally curing the epoxy resin precursor at a predetermined temperature.

(2)スクリーン印刷法等によって、得られたセラミックグリーンシートに第1貫通導体4や第2貫通導体5や内層パターン6、内部配線層と貫通配線導体とを含む配線導体となる部分に金属ペーストを塗布および充填する。このメタライズペーストは、母基板2となるセラミックグリーンシートと同時に焼成することによって、母基板2の表面または内部となる部位に設けられる第1貫通導体4や第2貫通導体5や内層パターン6、内部配線層と貫通配線導体とを含む配線導体とを含む配線導体が形成される。この金属ペーストは、タングステン,モリブデン,マンガン,銀または銅等の金属粉末に適当な溶剤およびバインダーを加えて混練することによって、適度な粘度に調整して作製される。なお、メタライズペーストは、母基板2との接合強度を高めるために、ガラス、セラミックスを含んでいても構わない。   (2) A metal paste is applied to a portion that becomes a wiring conductor including the first through conductor 4, the second through conductor 5, the inner layer pattern 6, and the inner wiring layer and the through wiring conductor on the obtained ceramic green sheet by a screen printing method or the like. Apply and fill. This metallized paste is fired at the same time as the ceramic green sheet to be the mother substrate 2, so that the first through conductor 4, the second through conductor 5, the inner layer pattern 6, the inner layer pattern 6, and the like A wiring conductor including a wiring layer and a wiring conductor including a through wiring conductor is formed. This metal paste is prepared by adjusting an appropriate viscosity by adding an appropriate solvent and a binder to a metal powder such as tungsten, molybdenum, manganese, silver or copper and kneading. The metallized paste may contain glass or ceramics in order to increase the bonding strength with the mother board 2.

(3)各絶縁層となるセラミックグリーンシートを積層して加圧することによりセラミックグリーンシート積層体を作製する。   (3) A ceramic green sheet laminate is produced by laminating and pressing the ceramic green sheets to be the respective insulating layers.

(4)このセラミックグリーンシート積層体を約1500〜1800℃の温度で焼成して、母基板2が複数配列された多数個取り基板を得る。なお、この工程によって、前述したメタライズペーストは、第1貫通導体4や第2貫通導体5や内層パターン6、内部配線層と貫通配線導体とを含む配線導体となる。   (4) The ceramic green sheet laminate is fired at a temperature of about 1500 to 1800 ° C. to obtain a multi-piece substrate in which a plurality of mother substrates 2 are arranged. By this step, the metallized paste described above becomes a wiring conductor including the first through conductor 4, the second through conductor 5, the inner layer pattern 6, the internal wiring layer and the through wiring conductor.

(5)焼成して得られた多数個取り配線基板1に電解めっき法を用いて、第2貫通導体5および配線導体にNiめっきやAuめっきを被着させる。   (5) Ni plating or Au plating is applied to the second through conductor 5 and the wiring conductor using the electrolytic plating method on the multi-piece wiring board 1 obtained by firing.

上記(1)〜(5)の工程によって、多数個取り配線基板1が得られる。   The multi-piece wiring board 1 is obtained by the steps (1) to (5).

このようにして表面にめっき層が被着された多数個取り配線基板1を画像や目視にて外観検査を行い、外側領域1bに設けられた第1貫通導体4および第2貫通導体5のめっき層の被着の有無を確認することで、配線基板領域1a内における配線導体間に断線または短絡が発生している可能性の確認を行うことができる。   In this way, the appearance of the multi-piece wiring board 1 having the plating layer deposited on the surface is visually inspected by image or visual observation, and the first through conductor 4 and the second through conductor 5 provided in the outer region 1b are plated. By confirming the presence or absence of layer deposition, it is possible to confirm the possibility of a disconnection or short circuit between the wiring conductors in the wiring board region 1a.

(6)なお、多数個取り配線基板1を複数の母基板2に分断することによって、複数の配線基板を得ることができる。この分断においては、母基板2の外縁となる箇所に沿って多数個取り配線基板1に分割溝を形成しておき、この分割溝に沿って破断させて分割する方法、またはスライシング法等により母基板2の外縁となる箇所に沿って切断する方法等を用いることができる。なお、分割溝は、焼成後にスライシング装置により多数個取り基板の厚みより小さく切り込むことによって形成することができるが、多数個取り配線基板1用のセラミックグリーンシート積層体にカッター刃を押し当てたり、スライシング装置によりセラミックグリーンシート積層体の厚みより小さく切り込んだりすることによって形成してもよい。   (6) A plurality of wiring boards can be obtained by dividing the multi-cavity wiring board 1 into a plurality of mother boards 2. In this division, a dividing groove is formed in the multi-piece wiring board 1 along a portion that becomes the outer edge of the mother board 2, and the mother board is divided by breaking along the dividing groove or by a slicing method or the like. The method etc. which cut | disconnect along the location used as the outer edge of the board | substrate 2 can be used. The dividing grooves can be formed by cutting the multi-cavity substrate smaller than the thickness of the multi-cavity substrate after firing, but by pressing a cutter blade against the ceramic green sheet laminate for the multi-cavity wiring substrate 1, You may form by cutting smaller than the thickness of a ceramic green sheet laminated body with a slicing apparatus.

(第2の実施形態)
次に、本発明の第2の実施形態による多数個取り配線基板1について図4を参照しつつ説明する。なお、第2の実施形態が第1の実施形態と異なる点は、内層パターン6が接続されている貫通導体である。それ以外の部分は第1の実施形態と同様とする。
(Second Embodiment)
Next, a multi-piece wiring board 1 according to a second embodiment of the present invention will be described with reference to FIG. The second embodiment differs from the first embodiment in the through conductor to which the inner layer pattern 6 is connected. Other parts are the same as those in the first embodiment.

図4に示す例のように、多数個取り配線基板1は、複数の絶縁層が積層されてなるとともに、中央部に縦横に配列された複数の四角形状の配線基板領域1aと配線基板領域1aの外側領域1bとを有しており、表面にめっき電極3が設けられた多数個取り用の母基板2と、絶縁層の少なくとも1つを貫通して母基板2の両主面の少なくとも一方に導出されており、前記外側領域に設けられた第1貫通導体4と、絶縁層の少なくとも1つを貫通して母基板2の両主面の少なくとも一方に導出されており、外側領域1bに第1貫通導体4と隣り合って設けられ、めっき電極3と電気的に接続された第2貫通導体5と、母基板2の内部に設けられ、第1貫通導体4と電気的に接続されており、第2貫通導体5との間ではクリアランス7を有する内層パターン6とを有していてもよい。図4(b)および(c)に示す例においては、多数個取り配線基板1の正常な状態を示しており、第1貫通導体4と内層パターン6とは電気的に接続しているが、内層パターン6はめっき電極3と導通していない。つまり、多数個取り配線基板1をめっき層に浸漬し、電解めっき法によりめっき層を被着させた際に、第1貫通導体4の露出する表面にはめっき層は被着されず、第2貫通導体5の露出する表面には、めっき層が被着される。   As in the example shown in FIG. 4, the multi-piece wiring board 1 includes a plurality of insulating layers laminated, and a plurality of rectangular wiring board regions 1a and wiring board regions 1a arranged vertically and horizontally at the center. A plurality of mother substrates 2 having plating electrodes 3 provided on the surface thereof, and at least one of both main surfaces of the mother substrate 2 penetrating through at least one of the insulating layers. And is led to at least one of the two main surfaces of the mother board 2 through at least one of the first through conductor 4 and the insulating layer provided in the outer region, and the outer region 1b A second through conductor 5 provided adjacent to the first through conductor 4 and electrically connected to the plating electrode 3, provided inside the mother board 2, and electrically connected to the first through conductor 4. And an inner layer having a clearance 7 between the second through conductor 5 Turn 6 and may have a. In the example shown in FIGS. 4B and 4C, the multi-cavity wiring board 1 is in a normal state, and the first through conductor 4 and the inner layer pattern 6 are electrically connected. The inner layer pattern 6 is not electrically connected to the plating electrode 3. That is, when the multi-piece wiring board 1 is immersed in the plating layer and the plating layer is deposited by the electrolytic plating method, the plating layer is not deposited on the exposed surface of the first through conductor 4, and the second A plating layer is deposited on the exposed surface of the through conductor 5.

図4(c)に示す例においても、図3に示した例と同様に、複数の絶縁層を加圧して積層する際に最上層の絶縁層が2つめの絶縁層の所定の位置からずれ、第1貫通導体5と電
気的に接続している内層パターン6と第2貫通導体5とが電気的に接続した状態となった場合に、このような状態の多数個取り配線基板1を、電解めっき法を用いて、めっき層を被着させると、第1貫通導体4の露出した表面にめっき層が被着される。そして、目視ま
たは画像検査にて第2貫通導体5の露出した表面へのめっき層の被着の有無を確認することによって、多数個取り配線基板1の状態にて、配線基板領域1a内の結線の異なる配線導体間の短絡が発生している可能性を確認することができる。
In the example shown in FIG. 4C, as in the example shown in FIG. 3, when the plurality of insulating layers are pressed and stacked, the uppermost insulating layer is displaced from the predetermined position of the second insulating layer. When the inner layer pattern 6 electrically connected to the first through conductor 5 and the second through conductor 5 are electrically connected, the multi-piece wiring board 1 in such a state is When the plating layer is deposited using the electrolytic plating method, the plating layer is deposited on the exposed surface of the first through conductor 4. Then, by confirming whether or not the plating layer is deposited on the exposed surface of the second through conductor 5 by visual inspection or image inspection, the wiring in the wiring board region 1a is connected in the state of the multi-piece wiring board 1 The possibility that a short circuit between different wiring conductors has occurred can be confirmed.

(第3の実施形態)
次に、本発明の第3の実施形態による多数個取り配線基板1について図5〜図8を参照しつつ説明する。
(Third embodiment)
Next, a multi-piece wiring board 1 according to a third embodiment of the present invention will be described with reference to FIGS.

本実施形態における多数個取り配線基板1において第1の実施形態の多数個取り配線基板1と異なる点は、第1貫通導体4と第2貫通導体5との導出した表面に、それぞれの貫通導体よりも幅広の第1電極パターン10と第2電極パターン11を有している点、第1貫通導体4と第2貫通導体5とが母基板2を厚み方向(z軸方向)に貫通し、母基板2の上面および下面の両方に導出している点、各絶縁層間に第1貫通導体4同士および第2貫通導体5同士の電気的接続を補助するためのランド9をそれぞれ設けている点である。   The multi-cavity wiring board 1 of the present embodiment is different from the multi-cavity wiring board 1 of the first embodiment in that the respective through conductors are formed on the surfaces of the first through conductors 4 and the second through conductors 5 derived. The first electrode pattern 10 and the second electrode pattern 11 having a wider width, the first through conductor 4 and the second through conductor 5 penetrate the mother substrate 2 in the thickness direction (z-axis direction), A point leading out to both the upper surface and the lower surface of the mother board 2 and a land 9 for assisting electrical connection between the first through conductors 4 and the second through conductors 5 between the insulating layers. It is.

図5および図6に示す例において、第1貫通導体4および第2貫通導体5は、多数個取り配線基板1の表面にて、それぞれ第1電極パターン10および第2電極パターン11とは、第1貫通導体4および第2貫通導体5よりもそれぞれ幅広であり、平面透視における形状を異ならせている。   In the example shown in FIGS. 5 and 6, the first through conductor 4 and the second through conductor 5 are formed on the surface of the multi-piece wiring substrate 1, respectively, with the first electrode pattern 10 and the second electrode pattern 11. Each of the first through conductor 4 and the second through conductor 5 is wider than the first through conductor 4 and has a different shape in plan perspective.

第1貫通導体4および第2貫通導体5の表面に電極パターンを設けておくことで、多数個取り配線基板1の表面にて可視できる領域を増加させ、めっき層が被着しているか否かの判定を容易にし、誤検出または未検出といった可能性を低減させることができる。   Whether or not the plating layer is deposited by increasing the area visible on the surface of the multi-layer wiring board 1 by providing electrode patterns on the surfaces of the first through conductor 4 and the second through conductor 5. Can be easily determined, and the possibility of false detection or no detection can be reduced.

また、第1電極パターン10と第2電極パターン11とでは、形状を異ならせておくと、特に画像検査において、第1電極パターン10および第2電極パターン11のどちらにめっき層が被着しているかを検出する際に異なる形状として認識させるので、誤検出される可能性を低減することができる。また、目視検査を行う場合においても、電極パターンの形状が異なる方が確認しやすい。また、好ましくは、一方の電極パターンを円形状に近い形とした場合、他方の電極パターンは三角形や傾きの大きい台形等、互いの電極パターンの形状を大きく異ならせたほうがよい。   In addition, if the first electrode pattern 10 and the second electrode pattern 11 have different shapes, the plating layer is deposited on either the first electrode pattern 10 or the second electrode pattern 11, particularly in image inspection. Since it is recognized as a different shape when detecting whether or not, it is possible to reduce the possibility of erroneous detection. In addition, when visual inspection is performed, it is easier to confirm that the electrode pattern has a different shape. Preferably, when one of the electrode patterns has a nearly circular shape, the other electrode pattern should have a greatly different shape from each other, such as a triangle or a trapezoid having a large inclination.

また、図6(a)に示す例では、第1電極パターン10と第2電極パターン11とで大きさはほぼ等しいが、好ましくは表面積に大きく差をつけることが好ましい。例えば、図6(a)に示す例の変形例として、第1電極パターン10の表面積を、第2電極パターン11の1.5倍以上にしておくことが好ましい。これにより画像検査において誤検出をさらに低減させることができる。なお、特に第1電極パターン10を、第2電極パターン11よりも大きくしておくと、正常の状態で第2電極パターン11にはAuめっき層が被着されるので認識しやすい。   In the example shown in FIG. 6A, the first electrode pattern 10 and the second electrode pattern 11 are substantially equal in size, but it is preferable that the surface area is greatly different. For example, as a modification of the example shown in FIG. 6A, it is preferable that the surface area of the first electrode pattern 10 is 1.5 times or more that of the second electrode pattern 11. This can further reduce false detection in image inspection. In particular, if the first electrode pattern 10 is made larger than the second electrode pattern 11, it is easy to recognize because the Au plating layer is deposited on the second electrode pattern 11 in a normal state.

また、図5の示す例のように、第1電極パターン10と第2電極パターン11とは隣接して設けており、第1電極パターン10と第2電極パターン11との距離を0.3mm〜1.0mmとしておくと、画像検査における誤検出を防ぐことができる。   Further, as in the example shown in FIG. 5, the first electrode pattern 10 and the second electrode pattern 11 are provided adjacent to each other, and the distance between the first electrode pattern 10 and the second electrode pattern 11 is 0.3 mm to 1.0 mm. If it is set to mm, erroneous detection in the image inspection can be prevented.

また、本実施形態は図6(b)で示すように、第1貫通導体4および第2貫通導体5が母基板2を厚み方向(Z軸方向)に貫通している。このことによって、多数個取り配線基板1の表裏の向きに関係なく検査を行うことができる。   In this embodiment, as shown in FIG. 6B, the first through conductor 4 and the second through conductor 5 penetrate the mother board 2 in the thickness direction (Z-axis direction). As a result, the inspection can be performed regardless of the front and back directions of the multi-piece wiring board 1.

また、本実施形態では、図6(b)で示すように、内層パターン6は、複数の絶縁層の層間の全てに設けられており、それぞれの内層パターン6との間にクリアランスGを有するように、第1貫通導体4がそれぞれ設けられていることが好ましい。図6(b)では、母基板2は、6層の絶縁層から成っており、各絶縁層の層間はα〜εの5つの絶縁層間を有しており、第1貫通導体4と第2貫通導体5とのペアの個数はP1〜P5の計5個設けている。このように、第1貫通導体4と第2貫通導体5とのペアPをα〜ε層間の各絶縁層間毎に検出できるようにそれぞれ設けることで、どの絶縁層間のペアPに異常が発生している可能性があるのかを確認でき、製品解析の手段の一つとすることができる。なお、絶縁層の層数がnの場合、全ての絶縁層間の状態の確認を行う場合にはペアPの個数はn−1個設ける事になる。   In the present embodiment, as shown in FIG. 6B, the inner layer pattern 6 is provided in all the layers of the plurality of insulating layers, and has a clearance G between each of the inner layer patterns 6. The first through conductors 4 are preferably provided respectively. In FIG. 6 (b), the mother board 2 is composed of six insulating layers, and each insulating layer has five insulating layers α to ε. The total number of pairs with the through conductors 5 is P1 to P5. Thus, by providing the pair P of the first through conductor 4 and the second through conductor 5 so as to be detected for each insulating layer between the α to ε layers, an abnormality occurs in the pair P between the insulating layers. Can be confirmed as one of the means of product analysis. When the number of insulating layers is n, n-1 pairs P are provided when checking the state between all insulating layers.

図7〜図8に本実施形態の絶縁層間α〜δにおける要部拡大上面透視図を示す。   7 to 8 are enlarged top perspective views of main parts in the insulating layers α to δ of the present embodiment.

図7〜図8の示す例のように、第1貫通導体4および第2貫通導体5および配線領域基板1aの各貫通配線導体には、貫通配線導体の径以上の径を有するランド9を各絶縁層間に形成することで、製品の断線や短絡に影響しない程度の製造時のズレによる異常を防ぐことができ、上下の絶縁層間における電気的導通をより高めることができる。また、図7〜図8に示す例のように、クリアランス7を第1貫通導体4の周囲に円形状に設け、その周りに同様に円形状になるように内層パターン6を設けることで、どの方向にズレが生じたとしても確実に配線基板領域1aの内部配線層と貫通配線導体との短絡の検出が可能となる。このとき、クリアランス7の幅Gは第1の実施形態と同様に、それぞれの絶縁層間の配線基板領域1aにおける内部配線層同士、貫通配線導体同士、内部配線層と貫通配線導体同士のなかでの最短の距離とし、その距離は各絶縁層間を確認するペアP毎に異なっていてもよい。   7 to 8, each land wiring conductor of the first through conductor 4, the second through conductor 5 and the wiring area substrate 1a is provided with a land 9 having a diameter equal to or larger than the diameter of the through wiring conductor. By forming between the insulating layers, it is possible to prevent an abnormality caused by a manufacturing shift that does not affect the disconnection or short circuit of the product, and to further increase electrical conduction between the upper and lower insulating layers. Further, as in the example shown in FIGS. 7 to 8, the clearance 7 is provided in a circular shape around the first through conductor 4, and the inner layer pattern 6 is provided in a similar circular shape around the clearance 7. Even if a deviation occurs in the direction, it is possible to reliably detect a short circuit between the internal wiring layer of the wiring board region 1a and the through wiring conductor. At this time, the width G of the clearance 7 is similar to that in the first embodiment in the internal wiring layers, the through wiring conductors, and the internal wiring layers and the through wiring conductors in the wiring substrate region 1a between the respective insulating layers. The shortest distance may be used, and the distance may be different for each pair P that confirms each insulating layer.

図7(b)に示す例のように、本実施形態の多数個取り配線基板1においては、外側領域1bに、めっき電極3と電気的に導通しためっき用の枠状パターン8をβ層に有している。ペアP1〜P5の第2貫通導体5および、配線基板領域1aの内部配線導体はめっき用の枠状パターン8を介してめっき電極3と電気的に導通している。ペアP1〜P5の第2貫通導体5は必ずしもめっき用の枠状パターン8に導通していなくてもよいが、配線基板領域1aの内部配線導体がめっき用の枠状パターン8(めっき電極3)と電気的に導通しているため、図7に示す例のように配線基板領域1aの内部配線導体と導通することで、めっき電極3と電気的に導通させていてもよい。   As in the example shown in FIG. 7B, in the multi-cavity wiring board 1 of the present embodiment, a frame-like pattern 8 for plating electrically connected to the plating electrode 3 is formed in the β layer in the outer region 1b. Have. The second through conductors 5 of the pairs P1 to P5 and the internal wiring conductors of the wiring board region 1a are electrically connected to the plating electrode 3 via the frame pattern 8 for plating. The second through conductors 5 of the pairs P1 to P5 do not necessarily have to be connected to the frame pattern 8 for plating, but the internal wiring conductor in the wiring board region 1a is the frame pattern 8 for plating (plating electrode 3). Therefore, it may be electrically connected to the plating electrode 3 by conducting with the internal wiring conductor of the wiring board region 1a as in the example shown in FIG.

また、第1貫通導体4と第2貫通導体5との複数のペアPは、枠状パターン8に沿って設けられていると、枠状パターン8と複数の第2貫通導体5との距離をそれぞれ等しくしやすく、めっき層を被着させる際にかかる電圧を同程度にすることができ、めっき層の厚みがそれぞれ同程度となるため、被着しためっき層の濃紺による画像検査での誤検出を低減させることができ、より良好に配線基板領域1aの内部配線層と貫通配線導体との短絡および断線の検査を行うことができる。   Further, when the plurality of pairs P of the first through conductors 4 and the second through conductors 5 are provided along the frame-shaped pattern 8, the distance between the frame-shaped pattern 8 and the plurality of second through-conductors 5 is increased. It is easy to make them equal, the voltage applied when depositing the plating layer can be made the same, and the thickness of the plating layer is almost the same, so the false detection in the image inspection by the dark blue of the deposited plating layer Thus, it is possible to inspect the short circuit and the disconnection between the internal wiring layer of the wiring board region 1a and the through wiring conductor more favorably.

なお、第3の実施形態には、第1の実施形態だけでなく、第2の実施形態を組み合わせても良いものとする。   Note that the third embodiment may be combined with the second embodiment in addition to the first embodiment.

なお、本発明は上述の実施形態の例に限定されるものではなく、種々の変形は可能である。   In addition, this invention is not limited to the example of the above-mentioned embodiment, A various deformation | transformation is possible.

また、本実施形態における多数個取り配線基板1の配線基板領域1aの形状は指定されない。   Further, the shape of the wiring board region 1a of the multi-piece wiring board 1 in the present embodiment is not specified.

1・・・・多数個取り配線基板
1a・・・配線基板領域
1b・・・外側領域
2・・・・母基板
3・・・・めっき電極
4・・・・第1貫通導体
5・・・・第2貫通導体
6・・・・内層パターン
7・・・・クリアランス
8・・・・枠状パターン
9・・・・ランド
10・・・第1電極パターン
11・・・第2電極パターン
DESCRIPTION OF SYMBOLS 1 ... Multi-wiring board 1a ... Wiring board area | region 1b ... Outer area | region 2 ... Mother board 3 ... Plating electrode 4 ... 1st penetration conductor 5 ... Second through conductor 6 ... inner layer pattern 7 ... clearance 8 ... frame pattern 9 ... land 10 ... first electrode pattern 11 ... second electrode pattern

Claims (8)

複数の絶縁層が積層されてなるとともに、中央部に縦横に配列された複数の四角形状の配線基板領域と該配線基板領域の外側領域とを有しており、表面にめっき電極が設けられた多数個取り用の母基板と、
前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に設けられた第1貫通導体と、
前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に前記第1貫通導体と隣り合って設けられ、前記めっき電極と電気的に接続された第2貫通導体と、
前記母基板の内部に設けられ、前記第2貫通導体と電気的に接続されており、前記第1貫通導体との間ではクリアランスを有する内層パターンと、を有している
多数個取り配線基板。
A plurality of insulating layers are laminated, and each has a plurality of rectangular wiring board regions arranged in the center in the vertical and horizontal directions and an outer region of the wiring board region, and a plating electrode is provided on the surface. A large number of mother boards,
Passing through at least one of the insulating layers and being led out to at least one of the two main surfaces of the mother substrate, a first through conductor provided in the outer region;
It penetrates at least one of the insulating layers and is led out to at least one of the two main surfaces of the mother substrate, and is provided adjacent to the first through conductor in the outer region, and is electrically connected to the plating electrode. A connected second through conductor;
A multi-piece wiring board, comprising: an inner layer pattern provided inside the mother board, electrically connected to the second through conductor, and having a clearance between the first through conductor.
前記第1貫通導体および前記第2貫通導体は、前記母基板の角部に設けられている
請求項1記載の多数個取り配線基板。
The multi-piece wiring board according to claim 1, wherein the first through conductor and the second through conductor are provided at corners of the mother board.
前記母基板の両主面の少なくとも一方に、前記第1貫通導体と電気的に接続されており、前記第1貫通導体の断面積よりも表面積の大きい第1電極パターンが設けられており、
前記母基板の両主面の少なくとも一方に、前記第2貫通導体と電気的に接続されており、前記第2貫通導体の断面積よりも表面積の大きい第2電極パターンが設けられている
請求項1または請求項2記載の多数個取り配線基板。
At least one of both main surfaces of the mother board is electrically connected to the first through conductor, and a first electrode pattern having a surface area larger than a cross-sectional area of the first through conductor is provided,
The second electrode pattern that is electrically connected to the second through conductor and has a larger surface area than a cross-sectional area of the second through conductor is provided on at least one of both main surfaces of the mother board. The multi-piece wiring board according to claim 1 or 2.
前記外側領域であって、前記複数の絶縁層間または前記母基板の表面に、前記配線基板領域を囲うように設けられためっき用の枠状パターンを有しており、
前記第2貫通導体は、前記枠状パターンを介して前記めっき電極と電気的に接続されている
請求項1乃至請求項3のいずれか記載の多数個取り配線基板。
The outer region has a frame pattern for plating provided on the surface of the plurality of insulating layers or the mother substrate so as to surround the wiring substrate region,
The multi-piece wiring board according to any one of claims 1 to 3, wherein the second through conductor is electrically connected to the plating electrode through the frame pattern.
前記内層パターンは、前記複数の絶縁層の層間の全てに設けられており、
それぞれの前記内層パターンとの間にクリアランスを有するように、前記第1貫通導体がそれぞれ設けられている
請求項1乃至請求項4のいずれか記載の多数個取り配線基板。
The inner layer pattern is provided in all layers between the plurality of insulating layers,
The multi-piece wiring board according to any one of claims 1 to 4, wherein the first through conductors are provided so as to have a clearance between the inner layer patterns.
前記第1貫通導体および前記第2貫通導体は、前記母基板の4つの角部周辺のすべてに
設けられている
請求項1乃至請求項5のいずれか記載の多数個取り配線基板。
The multi-piece wiring board according to any one of claims 1 to 5, wherein the first through conductor and the second through conductor are provided around all four corners of the mother board.
前記母基板には複数の配線導体が設けられており、
前記クリアランスは、前記配線導体どうしの最小の間隔と同程度である
請求項1乃至請求項6のいずれか記載の多数個取り配線基板。
The mother board is provided with a plurality of wiring conductors,
The multi-cavity wiring board according to any one of claims 1 to 6, wherein the clearance is substantially equal to a minimum interval between the wiring conductors.
複数の絶縁層が積層されてなるとともに、中央部に縦横に配列された複数の四角形状の配線基板領域と該配線基板領域の外側領域とを有しており、表面にめっき電極が設けられた多数個取り用の母基板と、
前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に設けられた第1貫通導体と、
前記絶縁層の少なくとも1つを貫通して前記母基板の両主面の少なくとも一方に導出されており、前記外側領域に前記第1貫通導体と隣り合って設けられ、前記めっき電極と電気的に接続された第2貫通導体と、
前記母基板の内部に設けられ、前記第1貫通導体と電気的に接続されており、前記第2貫通導体との間ではクリアランスを有する内層パターンと、を有している
多数個取り配線基板。
A plurality of insulating layers are laminated, and each has a plurality of rectangular wiring board regions arranged in the center in the vertical and horizontal directions and an outer region of the wiring board region, and a plating electrode is provided on the surface. A large number of mother boards,
Passing through at least one of the insulating layers and being led out to at least one of the two main surfaces of the mother substrate, a first through conductor provided in the outer region;
It penetrates at least one of the insulating layers and is led out to at least one of the two main surfaces of the mother substrate, and is provided adjacent to the first through conductor in the outer region, and is electrically connected to the plating electrode. A connected second through conductor;
A multi-layer wiring board, comprising: an inner layer pattern provided inside the mother board, electrically connected to the first through conductor, and having a clearance between the second through conductor.
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Publication number Priority date Publication date Assignee Title
JPS63192298A (en) * 1987-02-05 1988-08-09 株式会社アドバンテスト Method of matching discrepancy of multilayer printed board
JPH0682881U (en) * 1993-05-06 1994-11-25 沖電気工業株式会社 Multilayer printed wiring board
JP2003283145A (en) * 2002-03-26 2003-10-03 Sumitomo Bakelite Co Ltd Method of inspecting misregistration of multilayer wiring board
JP2008181927A (en) * 2007-01-23 2008-08-07 Kyocera Corp Multiple-piece patterned wiring board and manufacturing method thereof
JP2011066252A (en) * 2009-09-18 2011-03-31 Ngk Spark Plug Co Ltd Multi-pattern wiring board and manufacturing method of the same
JP2011249526A (en) * 2010-05-26 2011-12-08 Kyocera Corp Multi-piece wiring substrate
JP2012089797A (en) * 2010-10-22 2012-05-10 Kyocera Corp Multipiece wiring board

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192298A (en) * 1987-02-05 1988-08-09 株式会社アドバンテスト Method of matching discrepancy of multilayer printed board
JPH0682881U (en) * 1993-05-06 1994-11-25 沖電気工業株式会社 Multilayer printed wiring board
JP2003283145A (en) * 2002-03-26 2003-10-03 Sumitomo Bakelite Co Ltd Method of inspecting misregistration of multilayer wiring board
JP2008181927A (en) * 2007-01-23 2008-08-07 Kyocera Corp Multiple-piece patterned wiring board and manufacturing method thereof
JP2011066252A (en) * 2009-09-18 2011-03-31 Ngk Spark Plug Co Ltd Multi-pattern wiring board and manufacturing method of the same
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