JP5558321B2 - Multiple wiring board - Google Patents

Multiple wiring board Download PDF

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JP5558321B2
JP5558321B2 JP2010258416A JP2010258416A JP5558321B2 JP 5558321 B2 JP5558321 B2 JP 5558321B2 JP 2010258416 A JP2010258416 A JP 2010258416A JP 2010258416 A JP2010258416 A JP 2010258416A JP 5558321 B2 JP5558321 B2 JP 5558321B2
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conductor
wiring board
layer
conductor layer
wiring
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JP2012109469A (en
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結美 柿原
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Description

本発明は、半導体素子や弾性表面波素子等の電子部品を搭載するための配線基板となる複数の配線基板領域が母基板に縦横の並びに配列されてなり、各配線基板領域の配線導体にめっき用の電流を供給するためのめっき用端子が母基板の露出表面に形成された多数個取り配線基板に関するものである。   In the present invention, a plurality of wiring board regions serving as wiring boards for mounting electronic components such as semiconductor elements and surface acoustic wave elements are arranged vertically and horizontally on a mother board, and the wiring conductors of each wiring board area are plated. The present invention relates to a multi-piece wiring board in which plating terminals for supplying a current for forming are formed on an exposed surface of a mother board.

従来、半導体素子や弾性表面波素子等の電子部品を搭載するために用いられる配線基板は、ガラスセラミック焼結体や酸化アルミニウム質焼結体等のセラミック焼結体からなる四角形板状の複数の絶縁層が積層されて形成された絶縁基体の上面に電子部品を搭載するための搭載部を有し、この搭載部またはその周辺から絶縁基体の側面や下面にかけてタングステンや銅等の金属材料から成る複数の配線導体が形成された構造を有している。   Conventionally, wiring boards used for mounting electronic components such as semiconductor elements and surface acoustic wave elements have a plurality of rectangular plate-like shapes made of ceramic sintered bodies such as glass ceramic sintered bodies and aluminum oxide sintered bodies. It has a mounting portion for mounting electronic components on the upper surface of the insulating base formed by stacking the insulating layers, and is made of a metal material such as tungsten or copper from the mounting portion or its periphery to the side or lower surface of the insulating base. It has a structure in which a plurality of wiring conductors are formed.

このような配線基板は、一般に、1枚の広面積の母基板から複数個の配線基板を同時集約的に得るようにした、いわゆる多数個取り配線基板の形態で製作されている。多数個取り配線基板は、例えば、平板状の母基板に配線基板となる複数の配線基板領域が縦横の並びに配列形成された構造を有している。   Such a wiring board is generally manufactured in the form of a so-called multi-cavity wiring board in which a plurality of wiring boards are obtained simultaneously from a single large-area mother board. The multi-cavity wiring board has, for example, a structure in which a plurality of wiring board regions serving as wiring boards are arranged vertically and horizontally on a flat mother board.

このような多数個取り配線基板は、配線基板領域の上面から下面等にかけて配線導体が形成され、上下の絶縁層の配線導体同士は絶縁層を厚み方向に貫通する貫通導体を介して互いに電気的に接続されている。   In such a multi-piece wiring board, wiring conductors are formed from the upper surface to the lower surface of the wiring board region, and the wiring conductors of the upper and lower insulating layers are electrically connected to each other via through conductors that penetrate the insulating layer in the thickness direction. It is connected to the.

また、多数個取り配線基板は、所定部位に配線導体となる導体ペーストを印刷した複数のセラミックグリーンシートを積層し、焼成することによって製作されている。貫通導体は、このセラミックグリーンシートにあらかじめ孔あけ加工を施して貫通孔を形成しておき、この貫通孔内に導体ペーストを充填して上記焼成の際に同時焼成することによって形成されている。   Further, the multi-piece wiring board is manufactured by laminating and firing a plurality of ceramic green sheets on which a conductor paste serving as a wiring conductor is printed at a predetermined portion. The through conductor is formed by punching the ceramic green sheet in advance to form a through hole, filling the through hole with a conductive paste, and simultaneously firing at the time of firing.

特開2001−319991号公報JP 2001-319991 特開2003−273272号公報JP 2003-273272 A 特開2007−158183号公報JP 2007-158183 A

しかしながら、上記従来技術の多数個取り配線基板においては、積層された上下のセラミックグリーンシートの間で互いに位置がずれる積層ずれを生じている可能性がある。積層ずれが生じると、上下の配線導体間の電磁的な結合の所定の数値からのずれによる電気特性の変動や、絶縁層(セラミックグリーンシート)を厚み方向に貫通するビア導体を介して上下の配線導体を電気的に接続するときのビア導体と配線導体との断線等の不具合を生じる可能性がある。特に、近年、配線導体を伝送される電気信号の高周波化が進んでいるため、上下の配線導体間の位置ずれによる配線導体の電気特性への影響が大きくなってきている。そのため、多数個取り配線基板においては、このような積層ずれが発生していないものであることを容易かつ確実に検知することが求められるようになっている。   However, in the above-described prior art multi-cavity wiring board, there is a possibility that there is a stacking misalignment between the stacked upper and lower ceramic green sheets. When stacking deviation occurs, the electrical characteristics fluctuate due to deviation from a predetermined numerical value of the electromagnetic coupling between the upper and lower wiring conductors, and the upper and lower via via conductors that penetrate the insulating layer (ceramic green sheet) in the thickness direction. There is a possibility of causing problems such as disconnection between the via conductor and the wiring conductor when the wiring conductor is electrically connected. In particular, since the frequency of electrical signals transmitted through wiring conductors has been increasing in recent years, the influence on the electrical characteristics of the wiring conductors due to the positional deviation between the upper and lower wiring conductors has increased. For this reason, it is demanded that a multi-piece wiring board easily and reliably detect that such a stacking deviation has not occurred.

本発明は、このような従来の問題点に鑑みて完成されたものであり、その目的は、許容
範囲を超える積層ずれが発生していないことを容易かつ確実に検知することが可能な多数個取り配線基板を提供することにある。
The present invention has been completed in view of such conventional problems, and its purpose is to provide a large number of pieces that can easily and reliably detect that a stacking deviation exceeding an allowable range has not occurred. It is to provide a wiring board.

本発明の多数個取り配線基板は、セラミック焼結体からなる複数の絶縁層が積層されて形成された母基板に複数の配線基板領域が縦横の並びに配列され、前記母基板の露出表面に、前記配線基板領域の配線導体にめっき用電流を供給するためのめっき用端子が形成された多数個取り配線基板であって、前記母基板の表面から前記絶縁層の層間にかけて貫通導体が形成されているとともに、前記絶縁層の層間に、前記貫通導体を挟んで対向し合う縁を有し、前記めっき用端子と電気的に接続された導体層が、前記縁と前記貫通導体との間に距離を置いて配置されており、平面視で、前記貫通導体と前記導体層の対向し合う縁とが並ぶ一の方向において前記貫通導体の側面から前記導体層の対向し合う前記縁までのそれぞれの最短距離を合計した長さが、前記一の方向において許容される前記絶縁層の積層ずれ量の2倍に一致していることを特徴とするものである。   In the multi-cavity wiring board of the present invention, a plurality of wiring board regions are arranged vertically and horizontally on a mother board formed by laminating a plurality of insulating layers made of a ceramic sintered body, and on the exposed surface of the mother board, A multi-piece wiring board in which a plating terminal for supplying a plating current to a wiring conductor in the wiring board region is formed, and a through conductor is formed from the surface of the mother board to the interlayer of the insulating layer. And a conductive layer electrically connected to the plating terminal has a distance between the edge and the through conductor, and has an edge facing each other with the through conductor interposed between the insulating layers. In a direction in which the through conductor and the opposing edge of the conductor layer are arranged in a plan view, respectively, from the side surface of the through conductor to the opposing edge of the conductor layer. Sum of shortest distances Saga, and is characterized in that it matches to twice the laminating misalignment amount in the insulating layer to be tolerated in the one direction.

また、本発明の多数個取り配線基板は、上記構成において、前記導体層が、平面視で前記貫通導体を挟んで互いの辺同士が対向し合うように配置された少なくとも一対の四角形状のパターンであることを特徴とするものである。   Further, the multi-cavity wiring board of the present invention is the above configuration, wherein the conductor layer has at least a pair of quadrangular patterns arranged such that the sides of the conductor layer face each other across the through conductor in a plan view. It is characterized by being.

また、本発明の多数個取り配線基板は、上記構成において、前記導体層が、平面視で内側に前記貫通導体が位置するように配置された円環状のパターンであることを特徴とするものである。   Further, the multi-piece wiring board of the present invention is characterized in that, in the above configuration, the conductor layer is an annular pattern arranged so that the through conductor is located inside in a plan view. is there.

また、本発明の多数個取り配線基板は、上記構成において、前記母基板の外周部に枠状のダミー領域が設けられており、前記導体層および前記貫通導体が前記ダミー領域に形成されていることを特徴とするものである。   In the multi-piece wiring board of the present invention, in the above configuration, a frame-shaped dummy region is provided on the outer peripheral portion of the mother substrate, and the conductor layer and the through conductor are formed in the dummy region. It is characterized by this.

本発明の多数個取り配線基板によれば、上記構成を備え、絶縁層の層間に、貫通導体を挟んで対向し合う縁を有するとともにめっき用端子と電気的に接続された導体層が、それぞれの縁と貫通導体との間に距離を置くように配置されており、平面視で、貫通導体と導体層の対向し合う縁とが並ぶ一の方向において貫通導体の側面から導体層の縁までの最短距離を合計した長さが、この一の方向において許容される絶縁層の積層ずれ量の2倍に一致していることから、積層ずれが許容範囲内であるときには、積層ずれによる導体層の一方の縁と貫通導体の側面との間の最短距離の減少分と、他方の縁と貫通導体との間の最短距離の増加分とが一致し、これらの最短距離を合計した長さは一定(許容される積層ずれ量の2倍)に維持され、導体層の対向し合う縁と貫通導体とが接していない(つまり、導体層と貫通導体とが電気的に接続していない。)。   According to the multi-cavity wiring board of the present invention, each of the conductor layers having the above-described configuration, having edges facing each other with the through conductor interposed between the insulating layers and electrically connected to the plating terminal, From the side surface of the through conductor to the edge of the conductor layer in one direction in which the through conductor and the opposing edge of the conductor layer are arranged in a plan view. The total length of the shortest distances is equal to twice the amount of stacking misalignment of the insulating layer allowed in this one direction. Therefore, when the stacking misalignment is within an allowable range, the conductor layer due to stacking misalignment The decrease in the shortest distance between one edge of the conductor and the side of the penetrating conductor matches the increase in the shortest distance between the other edge and the penetrating conductor, and the total length of these shortest distances is The conductor layer is kept constant (twice the allowable stacking deviation) Not in contact with the edge and the through conductor facing each other is (that is, the conductor layer and the through conductor is not electrically connected.).

そのため、めっき用端子にめっき用の電流を通電した際に、導体層を介して貫通導体にめっき用の電流が供給されることはなく、貫通導体の露出している端面にめっき層が被着しない。そして、この貫通導体の露出している端面にめっき層が被着していないことを確認することによって、多数個取り配線基板において許容範囲を超える積層ずれが発生していないことを容易に、かつ確実に検知することができる。したがって、許容範囲を超える積層ずれが発生していないことを容易かつ確実に検知することが可能な多数個取り配線基板を提供することができる。   Therefore, when a plating current is supplied to the plating terminal, the plating current is not supplied to the through conductor via the conductor layer, and the plating layer is deposited on the exposed end surface of the through conductor. do not do. And by confirming that the plating layer is not deposited on the exposed end face of this through conductor, it is easy to confirm that there is no stacking deviation exceeding the allowable range in the multi-piece wiring board, and It can be detected reliably. Therefore, it is possible to provide a multi-piece wiring board capable of easily and reliably detecting that a stacking deviation exceeding an allowable range has not occurred.

なお、許容される範囲を超えて積層ずれが発生した多数個取り配線基板においては、導体層の対向し合う縁のいずれかの部分と貫通導体とが接触するため、導体層を介して貫通導体にめっき用の電力が供給され、貫通導体の露出する端面にめっき層が被着される。し
たがって、上記積層ずれが発生している多数個取り配線基板を容易に識別することができる。
Note that in multi-cavity wiring boards where the stacking deviation has occurred beyond the allowable range, any part of the opposing edges of the conductor layer contacts the through conductor, so that the through conductor is interposed through the conductor layer. Is supplied with power for plating, and a plating layer is deposited on the exposed end face of the through conductor. Therefore, it is possible to easily identify a multi-piece wiring board in which the stacking deviation occurs.

また、本発明の多数個取り配線基板は、上記構成において、導体層が、平面視で貫通導体を挟んで互いの辺同士が対向し合うように配置された少なくとも一対の四角形状のパターンである場合には、導体層の形成が容易であり、また導体層と貫通導体とを上記の位置関係で形成することも容易である。したがって、この場合には、許容範囲を超える積層ずれが発生していないことの検知が容易かつ確実であり、生産性を高く確保する上でも有効な多数個取り配線基板を提供することができる。   In the multi-piece wiring board of the present invention, in the above configuration, the conductor layer is at least a pair of quadrangular patterns arranged so that the sides face each other across the through conductor in a plan view. In this case, it is easy to form the conductor layer, and it is also easy to form the conductor layer and the through conductor in the above positional relationship. Therefore, in this case, it is easy and reliable to detect that the stacking deviation exceeding the allowable range has not occurred, and it is possible to provide a multi-piece wiring board effective in ensuring high productivity.

また、導体層について、互いに対向し合う方向が異なる複数対の四角形状のパターンとすれば、複数の方向、例えば互いに直交しあう2方向(いわゆるX−Y方向)において積層ずれの有無を検知することもできる。   In addition, if the conductor layer has a plurality of pairs of quadrilateral patterns with different directions facing each other, the presence or absence of stacking deviation is detected in a plurality of directions, for example, two directions (so-called XY directions) orthogonal to each other. You can also.

また、本発明の多数個取り配線基板は、上記構成において、導体層が、平面視で内側に貫通導体が位置するように配置された円環状のパターンであり、この円環状の導体層の内周における縁の一部同士が貫通導体を挟んで対向し合っている場合には、円環状のパターンの半径方向のいずれにおいて許容範囲を超える積層ずれが発生しても導体層と貫通導体とが接する。導体層と貫通導体とが接すると貫通導体の露出している端面にめっき層が被着されるため、この端面にめっき層が被着されていない場合には、半径方向のいずれにおいても積層ずれが発生していないことが検知できる。そのため、より有効に、許容範囲を超える積層ずれが発生していないことを検知することが可能な多数個取り配線基板を提供することができる。   In the multi-piece wiring board of the present invention, in the configuration described above, the conductor layer is an annular pattern in which the through conductor is positioned inside in a plan view. When some of the edges on the circumference are opposed to each other with the through conductor interposed between them, the conductor layer and the through conductor are not affected even if a laminating deviation exceeding the allowable range occurs in any radial direction of the annular pattern. Touch. When the conductor layer is in contact with the through conductor, the plating layer is deposited on the exposed end surface of the through conductor. Therefore, if the plating layer is not deposited on this end surface, the stacking misalignment will occur in any radial direction. Can be detected. Therefore, it is possible to provide a multi-piece wiring board that can more effectively detect that a stacking deviation exceeding an allowable range has not occurred.

また、本発明の多数個取り配線基板は、上記いずれかの構成において、母基板の外周部に枠状のダミー領域が設けられており、導体層および貫通導体がダミー領域に形成されている場合には、配線基板領域に不要な導体層および貫通導体を配置する必要がないため、配線基板領域(個片の配線基板)の小型化や配線導体の高密度化を容易としながら、積層ずれが発生していないことを容易に確認することができる多数個取り配線基板を提供することができる。   Further, in the multi-piece wiring board of the present invention, in any of the above configurations, a frame-like dummy region is provided on the outer peripheral portion of the mother board, and the conductor layer and the through conductor are formed in the dummy region. Since there is no need to dispose unnecessary conductor layers and through conductors in the wiring board area, it is easy to downsize the wiring board area (individual wiring board) and to increase the density of the wiring conductor, and to prevent misalignment. It is possible to provide a multi-piece wiring board that can be easily confirmed that it has not occurred.

(a)は本発明の多数個取り配線基板の実施の形態の一例における要部を示す平面図であり、(b)は(a)のA−A線における断面図である。(A) is a top view which shows the principal part in an example of embodiment of the multi-cavity wiring board of this invention, (b) is sectional drawing in the AA of (a). 図1に示す多数個取り配線基板の全体を模式的に示す平面図である。It is a top view which shows typically the whole multi-piece wiring board shown in FIG. 図1(a)の要部を拡大して示す要部拡大平面図である。It is a principal part enlarged plan view which expands and shows the principal part of Fig.1 (a). (a)は本発明の多数個取り配線基板の実施の形態の他の例における要部を示す平面図であり、(b)は参考例の多数個取り配線基板の要部を示す平面図である。(A) is a top view which shows the principal part in the other example of embodiment of the multi-cavity wiring board of this invention, (b) is a top view which shows the principal part of the multi-cavity wiring board of a reference example. is there. (a)および(b)はそれぞれ本発明の多数個取り配線基板の実施の形態の他の例における要部を示す平面図である。(A) And (b) is a top view which shows the principal part in the other example of embodiment of the multi-piece wiring board of this invention, respectively. 本発明の多数個取り配線基板の実施の形態の他の例における要部を示す平面図である。It is a top view which shows the principal part in the other example of embodiment of the multi-cavity wiring board of this invention. 本発明の多数個取り配線基板の実施の形態の他の例を示す平面図である。It is a top view which shows the other example of embodiment of the multi-piece wiring board of this invention.

本発明の多数個取り配線基板について、添付の図面を参照しつつ説明する。   A multi-piece wiring board of the present invention will be described with reference to the accompanying drawings.

図1(a)は、本発明の多数個取り配線基板の実施の形態の一例における要部を示す平面図であり、図1(b)は、図1(a)のA−A線における断面図であり、図2は、図1に示す多数個取り配線基板の全体を模式的に示す平面図である。図1(a),図1(b)
および図2において、1は母基板,2は配線基板領域,3は配線導体,4は貫通導体,5は導体層である。配線導体3が形成された配線基板領域2が母基板1に複数個、縦横の並びに配列されて多数個取り配線基板9が基本的に形成されている。また、母基板1の外周側面や上面の外周部等の露出表面には、配列された複数の配線基板領域2のそれぞれの配線導体3にめっき用電流を供給するためのめっき用端子8が形成されている。図2に示す例に置いては、母基板1の外周部にダミー領域6が形成され、このダミー領域の外周に設けた切り欠きにめっき用端子8が形成されている。
Fig.1 (a) is a top view which shows the principal part in an example of embodiment of the multi-piece wiring board of this invention, FIG.1 (b) is a cross section in the AA line of Fig.1 (a). FIG. 2 is a plan view schematically showing the whole multi-piece wiring board shown in FIG. 1 (a) and 1 (b)
In FIG. 2, 1 is a mother board, 2 is a wiring board region, 3 is a wiring conductor, 4 is a through conductor, and 5 is a conductor layer. A plurality of wiring board regions 9 in which wiring conductors 3 are formed are arranged on the mother board 1 in the vertical and horizontal directions, so that a multi-piece wiring board 9 is basically formed. Further, plating terminals 8 for supplying a plating current to the respective wiring conductors 3 of the plurality of wiring substrate regions 2 formed on the exposed surface such as the outer peripheral side surface of the mother substrate 1 and the outer peripheral portion of the upper surface are formed. Has been. In the example shown in FIG. 2, a dummy region 6 is formed on the outer periphery of the mother substrate 1, and a plating terminal 8 is formed in a notch provided on the outer periphery of the dummy region.

母基板1は、ガラスセラミック焼結体,酸化アルミニウム質焼結体,窒化アルミニウム質焼結体,炭化珪素質焼結体,窒化珪素質焼結体,ムライト質焼結体等のセラミック焼結体からなる複数の絶縁層1aが積層されて形成されている。   The mother substrate 1 is a ceramic sintered body such as a glass ceramic sintered body, an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, and a mullite sintered body. A plurality of insulating layers 1a made of

母基板1に配列された複数の配線基板領域2は、それぞれが個片の配線基板(図示せず)となる領域である。母基板1が配線基板領域2の境界に沿って分割されることにより、複数の配線基板が同時集約的に製作される。   The plurality of wiring board regions 2 arranged on the mother board 1 are areas that each become an individual wiring board (not shown). By dividing the mother board 1 along the boundary of the wiring board region 2, a plurality of wiring boards are manufactured simultaneously and collectively.

個片の配線基板が電子部品搭載用基板として使用される場合には、配線基板領域2の上面の中央部等の表面に電子部品の搭載部(符号なし)が設けられる。図1に示す例においては、配線基板領域2の中央部が電子部品の搭載部とされ、この搭載部から外周部にかけて配線導体3が形成されている。図1および図2に示す例において、配線導体3は、搭載部に近い部分に電子部品の電極がボンディングワイヤやはんだ等の導電性接続材(図示せず)を介して電気的に接続される。   When an individual wiring board is used as an electronic component mounting board, an electronic component mounting portion (no reference numeral) is provided on the surface such as the central portion of the upper surface of the wiring board region 2. In the example shown in FIG. 1, the central portion of the wiring board region 2 is an electronic component mounting portion, and the wiring conductor 3 is formed from the mounting portion to the outer peripheral portion. In the example shown in FIGS. 1 and 2, the wiring conductor 3 is electrically connected to an electrode of an electronic component near a mounting portion via a conductive connecting material (not shown) such as a bonding wire or solder. .

搭載部に搭載される電子部品(図示せず)としては、ICやLSI等の半導体集積回路素子、およびLED(発光ダイオード)やPD(フォトダイオード),CCD(電荷結合素子)等の光半導体素子を含む半導体素子、弾性表面波素子や水晶振動子等の圧電素子、容量素子、抵抗器、半導体基板の表面に微小な電子機械機構が形成されてなるマイクロマシン(いわゆるMEMS素子)等の種々の電子部品が挙げられる。   Electronic components (not shown) mounted on the mounting unit include semiconductor integrated circuit elements such as IC and LSI, and optical semiconductor elements such as LED (light emitting diode), PD (photodiode), and CCD (charge coupled device). Various electronic devices such as semiconductor devices including surface acoustic wave devices, piezoelectric devices such as surface acoustic wave devices and crystal resonators, capacitive devices, resistors, and micromachines (so-called MEMS devices) in which a minute electromechanical mechanism is formed on the surface of a semiconductor substrate. Parts.

電子部品は、搭載部に、例えばエポキシ系樹脂,ポリイミド系樹脂,アクリル系樹脂,シリコーン系樹脂,ポリエーテルアミド系樹脂等の樹脂接着剤や、Au−Sn,Sn−Ag−Cu,Sn−Cu,Sn−Pb等のはんだや、ガラス等の接合材を介して接合される。   The electronic component has a resin adhesive such as an epoxy resin, a polyimide resin, an acrylic resin, a silicone resin, a polyether amide resin, Au-Sn, Sn-Ag-Cu, or Sn-Cu on the mounting portion. , Sn-Pb or the like, or a bonding material such as glass.

配線導体3は、例えば上記のように電子部品と電気的に接続され、この電子部品を外部の電気回路に電気的に接続する導電路となる。図1に示す例においては、絶縁層1aを間に挟んで上下に配線導体3が配置されている。上下の配線導体3同士は互いに重なり合う部分を有し、この重なり合っている部分で電磁的に結合して所定のインダクタンス成分や容量成分を生じるように設定されている。この場合、配線導体3に数百MHz〜数十GHz程度を高周波信号が伝送されるときに、上記配線導体3間の電磁的な結合によって配線導体3の電気特性が所定の値になるように調整される。   The wiring conductor 3 is electrically connected to an electronic component as described above, for example, and serves as a conductive path that electrically connects the electronic component to an external electric circuit. In the example shown in FIG. 1, wiring conductors 3 are arranged above and below with an insulating layer 1a interposed therebetween. The upper and lower wiring conductors 3 have portions that overlap each other, and are set so as to generate a predetermined inductance component and capacitance component by electromagnetic coupling at the overlapping portions. In this case, when a high frequency signal of about several hundred MHz to several tens GHz is transmitted to the wiring conductor 3, the electrical characteristics of the wiring conductor 3 become a predetermined value by electromagnetic coupling between the wiring conductors 3. Adjusted.

配線導体3は、タングステンやモリブデン,銅−タングステン,マンガン,銀,銅,パラジウム,白金,金等の金属材料により形成されている。これらの金属材料は、例えばメタライズ層として絶縁層1aの表面に被着される。   The wiring conductor 3 is made of a metal material such as tungsten, molybdenum, copper-tungsten, manganese, silver, copper, palladium, platinum, or gold. These metal materials are deposited on the surface of the insulating layer 1a as a metallized layer, for example.

なお、配線導体3は、絶縁層1aを厚み方向に貫通する導体(いわゆるビア導体)(図示せず)を含む場合がある。この場合には、絶縁層1aを厚み方向に貫通する貫通孔(図示せず)内に上記と同様のタングステン等の金属材料が充填されることによってビア導体が形成される。   The wiring conductor 3 may include a conductor (so-called via conductor) (not shown) penetrating the insulating layer 1a in the thickness direction. In this case, a via conductor is formed by filling a through-hole (not shown) penetrating the insulating layer 1a in the thickness direction with a metal material such as tungsten similar to the above.

めっき用端子8は、例えば四角平板状の母基板1の外周側面や上下面の外周部等の露出表面に形成され、母基板1の内部や表面等に形成された接続用の導体(図示せず)を介して配線基板領域2の配線導体3と電気的に接続されている。めっき用端子8は、図2に示す例においては、母基板1の外周部に平面視で円弧状等の形状で切り欠きを設け、この切り欠きの内側面に配線導体3と同様の金属材料が被着されて形成されている。   The plating terminal 8 is formed on an exposed surface such as the outer peripheral side of the square flat plate-shaped mother substrate 1 or the outer peripheral portion of the upper and lower surfaces, for example, and is a connection conductor (not shown) formed on the inside or the surface of the mother substrate 1. And the wiring conductor 3 of the wiring board region 2 is electrically connected. In the example shown in FIG. 2, the plating terminal 8 is provided with a notch in the shape of an arc or the like in plan view on the outer peripheral portion of the mother board 1, and the same metal material as that of the wiring conductor 3 on the inner surface of the notch Is formed.

このような、それぞれが配線導体3を有する複数の配線基板領域2が縦横の並びに配列された、めっき用端子8を有する母基板1は、例えば各絶縁層1aが酸化アルミニウム質焼結体からなる場合であれば、次のようにして製作することができる。   In such a mother substrate 1 having plating terminals 8 in which a plurality of wiring substrate regions 2 each having a wiring conductor 3 are arranged vertically and horizontally, for example, each insulating layer 1a is made of an aluminum oxide sintered body. If so, it can be manufactured as follows.

まず、酸化アルミニウムおよび二酸化ケイ素を含むホウケイ酸系ガラスを主成分とし、酸化マグネシウムや酸化カルシウム等を混合してなる原料粉末を、有機溶剤およびバインダと混練するとともに、ドクターブレード法やリップコータ法等の成形方法でシート状に成形して、セラミックグリーンシートを作製する。次に、タングステンやモリブデン等の金属材料の粉末を有機溶剤およびバインダとともに混練して、金属ペーストを作製する。次に、配線基板領域2となる領域のそれぞれに、所定の配線導体3のパターンにスクリーン印刷法等の印刷法で金属ペーストを印刷する。また、必要に応じて、とともに、セラミックグリーンシートに貫通孔を形成して、この貫通孔内にビア導体となる金属ペーストを充填する。そして、複数のセラミックグリーンシートに、所定パターンにめっき用端子8となる金属ペーストを印刷するとともにこれらを積層し、このセラミックグリーンシートの積層体を、母基板1の外形寸法に切断した後、約1500〜1600℃程度の焼成温度で焼成することによって、それぞれが配線導体3を有する複数の配線基板領域2が縦横の並びに配列された、めっき用端子8を有する母基板1を製作することができる。   First, a raw material powder composed mainly of borosilicate glass containing aluminum oxide and silicon dioxide, mixed with magnesium oxide, calcium oxide, etc. is kneaded with an organic solvent and a binder, and a doctor blade method, a lip coater method, etc. A ceramic green sheet is produced by forming into a sheet by a forming method. Next, a metal paste such as tungsten or molybdenum is kneaded with an organic solvent and a binder to produce a metal paste. Next, a metal paste is printed on a pattern of a predetermined wiring conductor 3 by a printing method such as a screen printing method in each region to be the wiring board region 2. Further, as necessary, a through hole is formed in the ceramic green sheet, and a metal paste serving as a via conductor is filled in the through hole. Then, a plurality of ceramic green sheets are printed with a metal paste serving as the plating terminals 8 in a predetermined pattern, and these are laminated. After the ceramic green sheet laminate is cut into the outer dimensions of the mother board 1, about By firing at a firing temperature of about 1500 to 1600 ° C., the mother board 1 having the plating terminals 8 in which the plurality of wiring board regions 2 each having the wiring conductor 3 are arranged vertically and horizontally can be manufactured. .

なお、めっき用端子8となる金属ペーストの印刷は、セラミックグリーンシートを積層する前でも、積層した後でも、どちらでも構わない。この場合、セラミックグリーンシートまたはその積層体の外周部に円弧状等の切り下記を設けておいて、この切り欠きの内側面にめっき用端子8となる金属ペーストを印刷するようにしてもよい。   The printing of the metal paste to be the plating terminal 8 may be performed either before or after the ceramic green sheets are stacked. In this case, an arc-like cut or the like may be provided on the outer peripheral portion of the ceramic green sheet or its laminate, and a metal paste that will serve as the plating terminal 8 may be printed on the inner surface of the cutout.

本発明の多数個取り配線基板9は、母基板1の表面から絶縁層1aの層間にかけて貫通導体4が形成されているとともに、絶縁層1aの層間に、貫通導体4を挟んで対向し合う縁を有するとともにめっき用端子8と電気的に接続された導体層5が、それらの縁と貫通導体4との間に距離を置くように配置されており、例えば図3に示すように、平面視で、貫通導体4と導体層5の対向し合う縁とが並ぶ一の方向Lにおいて貫通導体4の側面から導体層5の対向し合うそれぞれの縁までの最短距離Sを合計した長さが、上記一の方向Lにおいて許容される絶縁層1aの積層ずれ量の2倍に一致している。なお、図3は、図1(a)の要部を拡大して示す要部拡大平面図である。図3において図1と同様の部位には同様の符号を付している。   In the multi-chip wiring board 9 of the present invention, through conductors 4 are formed from the surface of the mother board 1 to the interlayer of the insulating layer 1a, and the edges facing each other with the through conductor 4 interposed between the insulating layers 1a. And a conductor layer 5 electrically connected to the plating terminal 8 is disposed so as to be spaced from the edge and the through conductor 4, for example, as shown in FIG. Then, the total length of the shortest distances S from the side surface of the through conductor 4 to the opposing edges of the conductor layer 5 in one direction L in which the through conductor 4 and the opposing edge of the conductor layer 5 are arranged is: This corresponds to twice the amount of misalignment of the insulating layer 1a allowed in the one direction L. FIG. 3 is an enlarged plan view of the main part showing the main part of FIG. In FIG. 3, the same parts as those in FIG.

このような多数個取り配線基板9によれば、上記構成を備えることから、上下の絶縁層1a間の積層ずれが許容範囲内であるとき(つまり、本発明の範囲内であるとき)には、積層ずれによる導体層5の一方の縁と貫通導体4の側面との間の最短距離Sの減少分と、他方の縁と貫通導体4との間の最短距離Sの増加分とが一致し、これらの最短距離Sを合計した長さは一定(許容される積層ずれ量の2倍)に維持され、導体層5の対向し合う縁と貫通導体4とが接していない(つまり、導体層5と貫通導体4とが電気的に接続していない。)。   According to such a multi-cavity wiring board 9, since the above configuration is provided, when the stacking deviation between the upper and lower insulating layers 1a is within an allowable range (that is, within the scope of the present invention). The decrease in the shortest distance S between one edge of the conductor layer 5 and the side surface of the through conductor 4 due to the misalignment coincides with the increase in the shortest distance S between the other edge and the through conductor 4. The total length of these shortest distances S is maintained constant (twice the allowable stacking deviation), and the opposing edges of the conductor layer 5 and the through conductor 4 are not in contact (that is, the conductor layer). 5 and the through conductor 4 are not electrically connected.)

そのため、めっき用端子8にめっき用の電流を通電した際に、導体層5を介して貫通導体4にめっき用の電流が供給されることはなく、貫通導体4の露出している端面にめっき
層が被着しない。そして、この貫通導体4の露出している端面にめっき層が被着していないことを確認することによって、多数個取り配線基板9において許容範囲を超える積層ずれが発生していないことを容易に、かつ確実に検知することができる。したがって、許容範囲を超える積層ずれが発生していないことを容易かつ確実に検知することが可能な多数個取り配線基板9を提供することができる。
Therefore, when a plating current is supplied to the plating terminal 8, no plating current is supplied to the through conductor 4 via the conductor layer 5, and the exposed end surface of the through conductor 4 is plated. The layer does not adhere. Then, by confirming that the plated layer is not deposited on the exposed end face of the through conductor 4, it is easy to confirm that the stacking deviation exceeding the allowable range does not occur in the multi-piece wiring board 9. And can be detected reliably. Therefore, it is possible to provide the multi-piece wiring board 9 that can easily and surely detect that the stacking deviation exceeding the allowable range has not occurred.

なお、許容される範囲を超えて積層ずれが発生した多数個取り配線基板(図示せず)においては、導体層(図示せず)の縁のいずれかと貫通導体(図示せず)とが接触するため、導体層を介して貫通導体にめっき用の電力が供給され、貫通導体の露出する端面にめっき層が被着される。したがって、上記積層ずれが発生している多数個取り配線基板を容易に識別することができる。   In addition, in a multi-piece wiring board (not shown) in which the stacking deviation has occurred beyond the allowable range, one of the edges of the conductor layer (not shown) and the through conductor (not shown) are in contact with each other. Therefore, the power for plating is supplied to the through conductor via the conductor layer, and the plating layer is deposited on the exposed end surface of the through conductor. Therefore, it is possible to easily identify a multi-piece wiring board in which the stacking deviation occurs.

図4(a)は、本発明の多数個取り配線基板9の実施の形態の他の例における要部を示す平面図であり、図4(b)は、参考例の多数個取り配線基板19の要部を示す平面図である。図4において図1と同様の部位には同様の符号を付している。なお、図4(b)において、11は参考例の多数個取り配線基板19の母基板,12は配線基板領域,13は配線導体,14貫通導体は,15は導体層である。   FIG. 4A is a plan view showing a main part in another example of the embodiment of the multi-cavity wiring board 9 of the present invention, and FIG. 4B is a multi-cavity wiring board 19 of the reference example. It is a top view which shows the principal part. 4, parts similar to those in FIG. 1 are denoted by the same reference numerals. In FIG. 4B, 11 is a mother board of the multi-piece wiring board 19 of the reference example, 12 is a wiring board region, 13 is a wiring conductor, 14 is a through conductor, and 15 is a conductor layer.

図4(a)は、導体層5が形成されている絶縁層1aが上の絶縁層1aに対して、許容される範囲内で右側に積層ずれしている場合の例である。この場合、右側の導体層5の縁と貫通導体4の側面との間の最短距離の増加分と、左側の導体層5の縁と貫通導体4の側面との間の最短距離の減少分とが一致し、これらの最短距離を合計した長さは一定に維持され、左側の導体層5の縁と貫通導体4とは接していない。この場合には、貫通導体4は導体層5からめっき用の電流が供給されないので、その露出している端面にめっき層が被着することはない。そのため、積層ずれが許容範囲内であることが検知できる。   FIG. 4A shows an example in which the insulating layer 1a on which the conductor layer 5 is formed is misaligned to the right within an allowable range with respect to the upper insulating layer 1a. In this case, an increase in the shortest distance between the edge of the right conductor layer 5 and the side surface of the through conductor 4 and a decrease in the shortest distance between the edge of the left conductor layer 5 and the side surface of the through conductor 4 The total length of these shortest distances is kept constant, and the edge of the left conductor layer 5 and the through conductor 4 are not in contact with each other. In this case, since the plating conductor is not supplied with a plating current from the conductor layer 5, the plating layer is not deposited on the exposed end face. Therefore, it can be detected that the stacking deviation is within an allowable range.

言い換えれば、貫通導体4と対向し合う導体層5の縁との間のそれぞれの最短距離の合計が許容ずれ量の2倍に一致していれば、これらの導体層5の縁のそれぞれと貫通導体4との最短距離が互いに同じ最短距離Sである必要はない。図4(a)に示す例においても、対向し合う導体層5の縁と貫通導体4との間のそれぞれの最短距離の合計が許容ずれ量の2倍に一致している。   In other words, if the sum of the shortest distances between the penetrating conductors 4 and the edges of the conductor layer 5 facing each other is equal to twice the allowable deviation amount, each of the edges of the conductor layers 5 and the penetrating holes are penetrated. The shortest distance from the conductor 4 does not have to be the same shortest distance S. Also in the example shown in FIG. 4A, the sum of the shortest distances between the edges of the opposing conductor layers 5 and the through conductors 4 is twice the allowable deviation amount.

これに対して、図4(b)に示す参考例の多数個取り配線基板19においては、導体層15が形成されている絶縁層(符号なし)が上の絶縁層に対して、許容範囲を超えて右側に積層ずれしている。この多数個取り配線基板19においては、左側の導体層15の縁が平面視で貫通導体14と重なる位置にあり、導体層15と貫通導体14とが電気的に接続されている。この場合には、貫通導体14に導体層15を介してめっき用電流が供給されるため、貫通導体14の露出している端面にはめっき液中でめっき層が被着する。そのため、許容範囲を超える積層ずれが発生している多数個取り配線基板19であることが容易に検知される。   On the other hand, in the multi-piece wiring board 19 of the reference example shown in FIG. 4 (b), the insulating layer (no symbol) on which the conductor layer 15 is formed has an allowable range with respect to the upper insulating layer. The stacking is shifted to the right. In the multi-cavity wiring board 19, the edge of the left conductor layer 15 is positioned so as to overlap the through conductor 14 in plan view, and the conductor layer 15 and the through conductor 14 are electrically connected. In this case, since the plating current is supplied to the through conductor 14 via the conductor layer 15, the plating layer is deposited on the exposed end surface of the through conductor 14 in the plating solution. Therefore, it is easily detected that the multi-layer wiring board 19 has a stacking deviation exceeding the allowable range.

導体層5とめっき用端子8との電気的な接続は、例えば絶縁層1aの層間に配置した内部配線(図示せず)や絶縁層1aを厚み方向に貫通するビア導体(図示せず)等を介して行なわせることができる。   The electrical connection between the conductor layer 5 and the plating terminal 8 is, for example, an internal wiring (not shown) arranged between the insulating layers 1a, a via conductor (not shown) penetrating the insulating layer 1a in the thickness direction, or the like. It can be done through.

なお、許容される積層ずれ量とは、例えば前述した上下の配線導体3間の電磁的な結合を所定の値とする上で許容されるずれ量である。この許容ずれ量を超えて上下の絶縁層1aの間で積層ずれが生じたときには、上下の配線導体3間の電磁的な結合量が所定の値から外れ、配線導体3の電気的な特性が所定値から外れてしまう。   Note that the allowable stacking shift amount is, for example, a shift amount allowed when the electromagnetic coupling between the upper and lower wiring conductors 3 described above is set to a predetermined value. When a laminating deviation occurs between the upper and lower insulating layers 1a exceeding the allowable deviation amount, the electromagnetic coupling amount between the upper and lower wiring conductors 3 deviates from a predetermined value, and the electrical characteristics of the wiring conductor 3 are reduced. It deviates from the predetermined value.

許容される積層ずれ量は、例えば上記のように上下の配線導体3間の電磁的な結合を考
慮したものであるときには、絶縁層1aが酸化アルミニウム質焼結体からなり、配線導体3がタングステンまたはモリブデンからなる線幅が約100μm程度のものである場合に、
配線導体3を伝送される電気信号を数百MHz程度の高周波信号とすれば、最大で約25μm程度である。
The allowable stacking deviation amount is, for example, in consideration of electromagnetic coupling between the upper and lower wiring conductors 3 as described above, and the insulating layer 1a is made of an aluminum oxide sintered body, and the wiring conductor 3 is made of tungsten. Or when the line width made of molybdenum is about 100 μm,
If the electrical signal transmitted through the wiring conductor 3 is a high-frequency signal of about several hundred MHz, the maximum is about 25 μm.

この場合、例えば、貫通導体4を直径が約100μmの円形状(円柱状)とするとともに
、貫通導体4を挟んで対向し合う縁を有する導体層5をそれぞれ、互いに対向し合う縁が互いに平行な辺である、1辺の長さが約100μm〜500μmの四角形状(長方形状等)として、これらの互いに平行な外辺のちょうど中央に貫通導体4を位置させるように設定すればよい。許容される積層ずれ量が25μmであるので、平面視で四角形状の導体層5の貫通導体4を挟んで対向し合う辺から貫通導体4の側面までのそれぞれの最短距離が、いずれも約25μm(合計で約50μm)になるように設定する。
In this case, for example, the through conductor 4 has a circular shape (cylindrical shape) having a diameter of about 100 μm, and the conductor layers 5 having edges facing each other across the through conductor 4 are parallel to each other. What is necessary is just to set so that the penetration conductor 4 may be located in the exact center of these mutually parallel outer sides as square shape (rectangular shape etc.) whose length of one side is about 100 micrometers-500 micrometers. Since the allowable stacking deviation amount is 25 μm, the shortest distances from the sides facing each other across the through conductor 4 of the rectangular conductor layer 5 in plan view to the side surface of the through conductor 4 are both about 25 μm. (Set to about 50 μm in total).

このような多数個取り配線基板9によれば、上下の絶縁層1aの間の積層ずれ量が許容ずれ量である25μm以下であれば、導体層5と貫通導体4とが電気的に接続されることはない。すなわち、積層ずれが発生していない(積層ずれ量が0μmである)ときには、左右の導体層5のいずれにおいても、その縁と貫通導体4の側面との平面視における最短距離が設定値と同じ25μm程度になる。また、積層ずれが許容される積層ずれ量と同じ程度であるときには、貫通導体4と導体層5の縁との最短距離が、導体層5の対向し合う縁のいずれか一方においては約50μm程度になり、他方においては0μmに近くなる。   According to such a multi-piece wiring board 9, if the amount of misalignment between the upper and lower insulating layers 1a is 25 μm or less, which is an allowable deviation, the conductor layer 5 and the through conductor 4 are electrically connected. Never happen. That is, when there is no stacking deviation (the stacking shift amount is 0 μm), the shortest distance in plan view between the edge of each of the left and right conductor layers 5 and the side surface of the through conductor 4 is the same as the set value. It becomes about 25μm. Further, when the stacking deviation is the same as the allowable stacking shift amount, the shortest distance between the through conductor 4 and the edge of the conductor layer 5 is about 50 μm at either one of the opposing edges of the conductor layer 5. On the other hand, close to 0 μm.

また、許容される積層ずれ量は、上記の配線導体3間の電磁的な結合以外の要因によって定められたものであっても構わない。例えば、各配線基板領域2の境界に沿って貫通孔(いわゆるキャスタレーション)(図示せず)を設けるときに、このキャスタレーションの内側面からの絶縁層1aの端部分(貫通孔の内側面を構成する部分)の許容される突出量を基準としてもよい。また、上下の配線導体3を、絶縁層1aを厚み方向に貫通する導体(ビア導体)(図示せず)を介して直接に電気的に接続するときに、ビア導体と配線導体3との接続範囲を基準にしてもよい。   The allowable stacking deviation amount may be determined by factors other than the electromagnetic coupling between the wiring conductors 3 described above. For example, when a through hole (so-called castellation) (not shown) is provided along the boundary of each wiring board region 2, the end portion of the insulating layer 1a from the inner side surface of this castellation (the inner side surface of the through hole is defined). The allowable protrusion amount of the component) may be used as a reference. When the upper and lower wiring conductors 3 are directly electrically connected via a conductor (via conductor) (not shown) penetrating the insulating layer 1a in the thickness direction, the connection between the via conductor and the wiring conductor 3 is established. The range may be used as a reference.

めっき用端子8に対するめっき用の電流の供給は、例えばめっき用端子8にめっき用ジグ(いわゆるラック等)(図示せず)の導通ピンを押し当てて、整流器等の電源からめっき用ジグを介してめっき用端子8に所定の電流を通電させることによって行なわれる。この場合、めっき用の電流は、めっき液中において、めっき用端子8から導体層5に供給されるとともに、各配線基板領域2の配線導体3にも供給され、ニッケルやコバルト,銅,金またはこれらを主成分とする合金等のめっき層が配線導体3および貫通導体4の露出面に被着される。この場合、配線基板領域2の間で配線導体3や導体層5を、絶縁層1a間に配置した接続用の導体(図示せず)等を介して互いに電気的に接続させておけば、最外周の配線基板領域2から順次、配列の内側の配線基板領域2にもめっき用の電流が供給される。   The plating current is supplied to the plating terminal 8 by, for example, pressing a conduction pin of a plating jig (so-called rack or the like) (not shown) against the plating terminal 8 and supplying power from a rectifier or the like through the plating jig. The plating terminal 8 is energized with a predetermined current. In this case, the plating current is supplied from the plating terminal 8 to the conductor layer 5 and also to the wiring conductor 3 in each wiring board region 2 in the plating solution, and nickel, cobalt, copper, gold or A plating layer such as an alloy containing these as main components is applied to the exposed surfaces of the wiring conductor 3 and the through conductor 4. In this case, if the wiring conductor 3 and the conductor layer 5 are electrically connected to each other via the connecting conductor (not shown) disposed between the insulating layers 1a between the wiring board regions 2, Sequentially from the outer peripheral wiring board region 2, a plating current is also supplied to the inner wiring board region 2.

なお、本発明の多数個取り配線基板9においては、上記のように貫通導体4の露出する端面にめっき層が被着していないことを確認することによって積層ずれが発生していないものであることを容易に検知することができ、この検知に要する時間は、例えば配線基板領域2が100〜400個程度配列されている場合であれば、10秒程度以内である。これに対して、従来の多数個取り配線基板(図示せず)においては、個々の配線基板領域(図示せず)毎に電気的な検査を施して積層ずれの有無を検査する場合には、自動検査装置を用いて約10分必要である。   In the multi-piece wiring board 9 according to the present invention, the stacking deviation is not generated by confirming that the plating layer is not deposited on the exposed end face of the through conductor 4 as described above. This can be easily detected, and the time required for this detection is, for example, within about 10 seconds if about 100 to 400 wiring board regions 2 are arranged. On the other hand, in the conventional multi-cavity wiring board (not shown), when an electrical inspection is performed for each wiring board region (not shown) to inspect the presence or absence of misalignment, It takes about 10 minutes using an automatic inspection device.

なお、導体層5は、前述したように、積層ずれに応じて、その縁と貫通導体4との間の最短距離が、上記のように一方における増加が他方における減少と同じになるように変化
するものである必要がある。そのため、導体層5の貫通導体4を挟んで対向し合う縁は、貫通導体4を通り、これらの縁の間の中間点を通る直線に対して線対称の関係であることが望ましい。
As described above, the conductor layer 5 changes in accordance with the stacking deviation so that the shortest distance between the edge and the through conductor 4 is the same as the decrease in the other as described above. It needs to be. Therefore, it is desirable that the edges of the conductor layer 5 that face each other across the through conductor 4 have a line-symmetric relationship with respect to a straight line that passes through the through conductor 4 and passes through an intermediate point between these edges.

このような導体層5としては、例えば図1に示したような、貫通導体4を挟んで対向し合う縁が互いに平行な辺である一対の四角形状のパターンや、このような四角形状のパターンが互いの短辺同士を互いに接続する接続導体(図示せず)介して接続されたものや、四角枠状のパターン(図示せず)、円環状のパターン等を挙げることができる。なお、導体層5は、母基板1に配置するスペースや生産性等を考慮すれば、長方形状等の四角形状のパターンが適している。   As such a conductor layer 5, for example, as shown in FIG. 1, a pair of square patterns whose edges facing each other across the through conductor 4 are parallel to each other, or such a square pattern Are connected via connecting conductors (not shown) that connect the short sides of each other, a square frame pattern (not shown), an annular pattern, and the like. Note that a rectangular pattern such as a rectangular shape is suitable for the conductor layer 5 in consideration of the space to be arranged on the mother board 1 and productivity.

すなわち、本発明の多数個取り配線基板9は、導体層5が、平面視で貫通導体4を挟んで互いの辺同士が対向し合うように配置された少なくとも一対の四角形状のパターンである場合には、導体層5の形成が容易であり、また導体層5と貫通導体4とを上記の位置関係で形成することも容易である。したがって、この場合には、許容範囲を超える積層ずれが発生していないことの検知が容易かつ確実であり、生産性を高く確保する上でも有効な多数個取り配線基板9を提供することができる。   That is, in the multi-cavity wiring board 9 of the present invention, the conductor layer 5 is at least a pair of quadrangular patterns arranged so that the sides of the conductor layer 5 face each other with the through conductor 4 in plan view. The conductor layer 5 can be easily formed, and the conductor layer 5 and the through conductor 4 can be easily formed in the above positional relationship. Therefore, in this case, it is easy and reliable to detect that the stacking deviation exceeding the allowable range has not occurred, and it is possible to provide the multi-piece wiring board 9 that is effective in ensuring high productivity. .

また、例えば図5(a)および(b)に示すように、導体層5について、互いに対向し合う方向が異なる複数対の四角形状のパターンとすれば、複数の方向において積層ずれの有無を検知することもできる。なお、図5(a)および(b)は、本発明の多数個取り配線基板9の実施の形態の他の例における要部を示す平面図である。図5において図1と同様の部位には同様の符号を付している。   Further, for example, as shown in FIGS. 5A and 5B, if the conductor layer 5 has a plurality of pairs of quadrilateral patterns with different directions facing each other, the presence or absence of misalignment in a plurality of directions is detected. You can also 5 (a) and 5 (b) are plan views showing the main part in another example of the embodiment of the multi-piece wiring board 9 of the present invention. 5, parts similar to those in FIG. 1 are denoted by the same reference numerals.

図5(a)に示す例は、図1に示すような導体層5と貫通導体4との組み合わせが、2組、それぞれの導体層5の縁と貫通導体4とが並ぶ一の方向L同士が互いに直交し合うように、かつ貫通導体4を共用するようにして配置された形態の例とみなすこともできる。   In the example shown in FIG. 5 (a), two combinations of the conductor layer 5 and the through conductor 4 as shown in FIG. 1 are arranged in one direction L in which the edge of each conductor layer 5 and the through conductor 4 are arranged. Can be regarded as an example of a configuration in which they are arranged so as to be orthogonal to each other and so as to share the through conductor 4.

このような例の場合には、互いに直交しあう2方向(いわゆるX−Y方向)において、上下の絶縁層1a間において積層ずれが許容される範囲内であることを検知することもできる。   In the case of such an example, it can also be detected that a stacking deviation is allowed between the upper and lower insulating layers 1a in two directions orthogonal to each other (so-called XY direction).

2組の導体層5は、図5(b)に示すように、それぞれに異なる貫通導体4を挟んで形成されていてもよい。この場合には、X−Y方向のうちいずれの方向において積層ずれが発生しているかを検知することができる。検知した積層ずれの方向(XまたはYまたはその両方)に応じて、その結果をフィードバックして、続いて製作する多数個取り配線基板の積層ずれを抑制する対策をする上で有利である。   As shown in FIG. 5B, the two sets of conductor layers 5 may be formed with different through conductors 4 interposed therebetween. In this case, it is possible to detect in which direction of the XY directions the stacking deviation has occurred. It is advantageous in taking measures to suppress the stacking deviation of the multi-chip wiring board to be manufactured subsequently by feeding back the result according to the detected direction of the stacking deviation (X and / or Y).

なお、図5に示す例における4つの導体層5は、全部が互いに離れたパターンではなく、一部同士が互いにつながっていてもよい。また、隣り合うもの同士が順次互いにつながって枠状のパターンになっていてもよい。   Note that the four conductor layers 5 in the example shown in FIG. 5 are not all patterns separated from each other, and some of them may be connected to each other. Further, adjacent objects may be sequentially connected to each other to form a frame-like pattern.

また、本発明の多数個取り配線基板9は、例えば図6に示すように、導体層5が、平面視で内側に貫通導体4が位置するように配置された円環状パターンである場合には、円環状パターンの半径方向のいずれにおいて許容範囲を超える積層ずれが発生しても導体層5と貫通導体4とが接する。そのため、より有効に、許容範囲を超える積層ずれが発生していないことを検知することが可能な多数個取り配線基板9を提供することができる。なお、図6は、本発明の多数個取り配線基板9の実施の形態の他の例における要部を示す平面図である。図6において図1と同様の部位には同様の符号を付している。   Further, in the multi-piece wiring board 9 of the present invention, for example, as shown in FIG. 6, when the conductor layer 5 is an annular pattern in which the through conductor 4 is positioned on the inner side in a plan view. The conductor layer 5 and the penetrating conductor 4 are in contact with each other in any radial direction of the annular pattern even if a stacking deviation exceeding an allowable range occurs. Therefore, it is possible to provide the multi-piece wiring board 9 that can more effectively detect that the stacking deviation exceeding the allowable range has not occurred. FIG. 6 is a plan view showing a main part in another example of the embodiment of the multi-piece wiring board 9 of the present invention. In FIG. 6, the same parts as those in FIG.

図6に示す例は、図1に示すような導体層5と貫通導体4との組み合わせが、多数組、それぞれの導体層5の縁と貫通導体4とが並ぶ一の方向L同士が円環状の導体層5の半径方向に沿って、かつ貫通導体4を共用するようにして配列された形態の例とみなすこともできる。   In the example shown in FIG. 6, there are many combinations of the conductor layer 5 and the through conductor 4 as shown in FIG. 1, and one direction L in which the edge of each conductor layer 5 and the through conductor 4 are arranged is annular. It can also be considered as an example of a configuration in which the through conductors 4 are shared along the radial direction of the conductor layer 5.

この場合、平面視で、例えば円形状の貫通導体4の中心が円環状の導体層5の中心またはその付近に位置するように、つまり貫通導体4の側面と導体層5の内周とが同心円状となるように設定すれば、許容範囲を超える積層ずれが発生していないことの検知を効果的に行なうことができる。   In this case, in plan view, for example, the center of the circular through conductor 4 is located at or near the center of the annular conductor layer 5, that is, the side surface of the through conductor 4 and the inner periphery of the conductor layer 5 are concentric. If it is set to be in the shape, it can be effectively detected that the stacking deviation exceeding the allowable range has not occurred.

また、本発明の多数個取り配線基板9は、図7に示すように、上記いずれかの構成において、母基板1の外周部に枠状のダミー領域6が設けられており、貫通導体4および導体層5がダミー領域6に形成されている場合には、配線基板領域2に不要な貫通導体4および導体層5を配置する必要がないため、配線基板領域2(個片の配線基板)の小型化や配線導体3の高密度化を容易としながら、積層ずれが発生していないことを容易に確認することができる多数個取り配線基板9を提供することができる。なお、図7は、本発明の多数個取り配線基板9の実施の形態の他の例における要部を示す平面図である。図7において図1および図2と同様の部位には同様の符号を付している。   Further, as shown in FIG. 7, the multi-piece wiring board 9 of the present invention has a frame-like dummy region 6 provided on the outer peripheral portion of the mother board 1 in any of the above-described configurations. When the conductor layer 5 is formed in the dummy region 6, it is not necessary to dispose unnecessary through conductors 4 and the conductor layer 5 in the wiring substrate region 2, so that the wiring substrate region 2 (individual wiring substrate) It is possible to provide a multi-piece wiring board 9 that can easily confirm that there is no stacking deviation while facilitating downsizing and increasing the density of the wiring conductor 3. FIG. 7 is a plan view showing a main part in another example of the embodiment of the multi-piece wiring board 9 of the present invention. In FIG. 7, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.

図7に示す例において、ダミー領域6は四角枠状であり、このダミー領域6の長さ方向に沿って長方形状の導体層5が、互いの長辺同士が隣り合うように配置されている。また、この導体層5の間に貫通導体4が配置されている。この例においても、貫通導体4と導体層5のそれぞれの縁との間の最短距離は、ともに許容ずれ量と一致していて、これらの最短距離を合計すれば許容ずれ量の2倍に一致する。   In the example shown in FIG. 7, the dummy region 6 has a rectangular frame shape, and the rectangular conductor layers 5 are arranged along the length direction of the dummy region 6 so that the long sides thereof are adjacent to each other. . Further, a through conductor 4 is disposed between the conductor layers 5. Also in this example, the shortest distances between the penetrating conductors 4 and the respective edges of the conductor layer 5 are both equal to the allowable deviation amount, and if these shortest distances are summed, they are equal to twice the allowable deviation amount. To do.

なお、図7に示す例においては、母基板1の互いに対向し合う2つの外周部分にそれぞれ2つずつ切り欠きが設けられ、この切り欠きの内側面から母基板1の上面の外周部にかけて、めっき用端子8として金属層が被着されている。この切り欠きにめっき用ジグのピンをかけて母基板1を上下から挟んで保持すれば、めっき液中における母基板1の保持とめっき用端子8に対するめっき用の電流の供給とを併せて行なうことができる。   In the example shown in FIG. 7, two notches are provided in each of the two outer peripheral portions of the mother substrate 1 facing each other, and the inner surface of the notches extends from the outer surface of the upper surface of the mother substrate 1. A metal layer is applied as the plating terminal 8. If the base plate 1 is sandwiched from above and below by holding the plating jig pins in the notches, the holding of the base substrate 1 in the plating solution and the supply of the plating current to the plating terminals 8 are performed together. be able to.

母基板1の外周部にダミー領域6を設けた構成においても、このダミー領域6に形成する導体層5を、平面視で貫通導体4を挟んで互いの辺同士が対向し合うように配置された少なくとも一対の四角形状のパターンとすれば、前述したのと同様に、許容範囲を超える積層ずれが発生していないことの検知が容易かつ確実であり、生産性を高く確保する上でも有効な多数個取り配線基板9を提供することができる。   Even in the configuration in which the dummy region 6 is provided on the outer peripheral portion of the mother board 1, the conductor layer 5 formed in the dummy region 6 is arranged so that the sides face each other with the through conductor 4 interposed therebetween in plan view. In addition, if at least a pair of square patterns are used, as described above, it is easy and reliable to detect that there is no stacking deviation exceeding an allowable range, and it is effective in ensuring high productivity. A multi-piece wiring board 9 can be provided.

図7に示す例においては、貫通導体4と、貫通導体4を挟んで対向し合う縁とが並ぶ一の方向Lが直交し合う四角形状の導体層5が2組ずつ、ダミー領域6に配置されている。この例では、X−Y方向において多数個取り配線基板9における許容範囲を超える積層ずれの有無をより効果的に検知できる。また、個片の配線基板における配線導体の高密度化等にも有効である。   In the example shown in FIG. 7, two sets of quadrangular conductor layers 5 are arranged in the dummy region 6, each of which is perpendicular to one direction L in which the through conductors 4 and the edges facing each other across the through conductors 4 are arranged. Has been. In this example, the presence or absence of misalignment exceeding the allowable range in the multi-cavity wiring board 9 in the XY direction can be detected more effectively. It is also effective for increasing the density of wiring conductors on a single wiring board.

母基板1の外周部にダミー領域6を設けた構成においても、導体層5を、平面視で内側に貫通導体4が位置するように配置された円環状のパターンとし、この円環状の導体層5の内周における縁の一部同士が貫通導体4を挟んで対向し合うようにすれば、前述したのと同様に、より有効に、許容範囲を超える積層ずれが発生していないことを検知することが可能な多数個取り配線基板を提供することができる。すなわち、この場合にも、導体層5の円環状パターンの半径方向のいずれにおいて許容範囲を超える積層ずれが発生しても導体層5と貫通導体4とが接し、導体層5を介して貫通導体4にめっき用の電流が供給さ
れて貫通導体4の露出している端面にめっき層が被着する。このめっき層が被着していることを検知することによって、許容範囲を超える積層ずれが発生していることを容易に検知することができる。
Even in the configuration in which the dummy region 6 is provided on the outer peripheral portion of the mother board 1, the conductor layer 5 is formed in an annular pattern in which the through conductors 4 are located on the inner side in a plan view, and the annular conductor layer is formed. If some of the edges on the inner circumference of 5 are opposed to each other with the through conductor 4 interposed therebetween, it is more effectively detected that the stacking deviation exceeding the allowable range has not occurred as described above. It is possible to provide a multi-piece wiring board that can be used. That is, also in this case, the conductor layer 5 and the through conductor 4 are in contact with each other through the conductor layer 5 even if a laminating deviation exceeding an allowable range occurs in any radial direction of the annular pattern of the conductor layer 5. 4 is supplied with a plating current, and a plating layer is deposited on the exposed end face of the through conductor 4. By detecting that the plating layer is deposited, it is possible to easily detect that a stacking deviation exceeding an allowable range has occurred.

なお、本発明は以上の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。   It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention.

例えば、貫通導体4の露出する端面(上端面)に配線導体3と同様の金属材料を用いて、この端面よりも面積が大きな認識用の導体パターン(図示せず)を、円形状や楕円形状,四角形状等のパターンで被着させて、積層ずれの認識をより容易にできるようにしてもよい。この場合には、貫通導体4の端面に比べて面積が大きい認識用のパッドによって、めっき層が被着していること、つまり積層ずれが発生していないことをより容易に、かつ確実に認識することができる。   For example, a metal material similar to that of the wiring conductor 3 is used for the exposed end surface (upper end surface) of the through conductor 4 and a recognition conductor pattern (not shown) having a larger area than the end surface is formed into a circular shape or an elliptical shape. , It may be deposited in a pattern such as a quadrilateral shape so that the stacking deviation can be recognized more easily. In this case, the recognition pad having a larger area than the end face of the through conductor 4 can more easily and reliably recognize that the plating layer is deposited, that is, no stacking deviation has occurred. can do.

1・・・母基板
1a・・絶縁層
2・・・配線基板領域
3・・・配線導体
4・・・貫通導体
5・・・導体層
6・・・ダミー領域
8・・・めっき用端子
9・・・多数個取り配線基板
DESCRIPTION OF SYMBOLS 1 ... Mother board 1a .... Insulating layer 2 ... Wiring board area | region 3 ... Wiring conductor 4 ... Through-conductor 5 ... Conductor layer 6 ... Dummy area 8 ... Terminal 9 for plating ... Multi-cavity wiring boards

Claims (4)

セラミック焼結体からなる複数の絶縁層が積層されて形成された母基板に複数の配線基板領域が縦横の並びに配列され、前記母基板の露出表面に、前記配線基板領域の配線導体にめっき用電流を供給するためのめっき用端子が形成された多数個取り配線基板であって、前記母基板の表面から前記絶縁層の層間にかけて貫通導体が形成されているとともに、前記絶縁層の層間に、前記貫通導体を挟んで対向し合う縁を有し、前記めっき用端子と電気的に接続された導体層が、前記縁と前記貫通導体との間に距離を置いて配置されており、平面視で、前記貫通導体と前記導体層の対向し合う前記縁とが並ぶ一の方向において前記貫通導体の側面から前記導体層の対向し合う前記縁までのそれぞれの最短距離を合計した長さが、前記一の方向において許容される前記絶縁層の積層ずれ量の2倍に一致していることを特徴とする多数個取り配線基板。 A plurality of wiring board regions are arranged vertically and horizontally on a mother board formed by laminating a plurality of insulating layers made of a ceramic sintered body, and the wiring conductor of the wiring board area is plated on the exposed surface of the mother board. A multi-piece wiring board in which terminals for plating for supplying current are formed, and through conductors are formed from the surface of the mother board to the interlayer of the insulating layer, and between the layers of the insulating layer, A conductor layer having edges facing each other with the through conductor interposed therebetween and electrically connected to the plating terminal is disposed at a distance between the edge and the through conductor, and is seen in a plan view. Then, the total length of the shortest distances from the side surface of the through conductor to the opposing edges of the conductor layer in one direction in which the through conductors and the opposing edges of the conductor layer are arranged is, In the one direction Multi-piece wiring substrate, wherein the match twice the laminating misalignment amount in the insulating layer acceptable. 前記導体層が、平面視で前記貫通導体を挟んで互いの辺同士が対向し合うように配置された少なくとも一対の四角形状のパターンであることを特徴とする請求項1記載の多数個取り配線基板。 2. The multi-piece wiring according to claim 1, wherein the conductor layer is at least a pair of quadrangular patterns arranged so that the sides thereof face each other across the through conductor in a plan view. substrate. 前記導体層が、平面視で内側に前記貫通導体が位置するように配置された円環状のパターンであることを特徴とする請求項1記載の多数個取り配線基板。 The multi-piece wiring board according to claim 1, wherein the conductor layer is an annular pattern arranged so that the through conductor is located inside in a plan view. 前記母基板の外周部に枠状のダミー領域が設けられており、前記導体層および前記貫通導体が前記ダミー領域に形成されていることを特徴とする請求項1〜請求項3のいずれかに記載の多数個取り配線基板。 The frame-shaped dummy area | region is provided in the outer peripheral part of the said mother board | substrate, The said conductor layer and the said penetration conductor are formed in the said dummy area | region, The Claim 1 characterized by the above-mentioned. Multiple printed wiring board as described.
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