JP2015015540A5 - - Google Patents

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Publication number
JP2015015540A5
JP2015015540A5 JP2013139868A JP2013139868A JP2015015540A5 JP 2015015540 A5 JP2015015540 A5 JP 2015015540A5 JP 2013139868 A JP2013139868 A JP 2013139868A JP 2013139868 A JP2013139868 A JP 2013139868A JP 2015015540 A5 JP2015015540 A5 JP 2015015540A5
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JP
Japan
Prior art keywords
clock
clk
circuit
speed
low
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JP2013139868A
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English (en)
Japanese (ja)
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JP2015015540A (ja
JP6317550B2 (ja
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Priority to JP2013139868A priority Critical patent/JP6317550B2/ja
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Publication of JP2015015540A5 publication Critical patent/JP2015015540A5/ja
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JP2013139868A 2013-07-03 2013-07-03 Ｅｍｉ対策回路 Active JP6317550B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013139868A JP6317550B2 (ja) 2013-07-03 2013-07-03 Ｅｍｉ対策回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013139868A JP6317550B2 (ja) 2013-07-03 2013-07-03 Ｅｍｉ対策回路

Publications (3)

Publication Number Publication Date
JP2015015540A JP2015015540A (ja) 2015-01-22
JP2015015540A5 true JP2015015540A5 (enrdf_load_stackoverflow) 2016-05-19
JP6317550B2 JP6317550B2 (ja) 2018-04-25

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ID=52436997

Family Applications (1)

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JP2013139868A Active JP6317550B2 (ja) 2013-07-03 2013-07-03 Ｅｍｉ対策回路

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JP (1) JP6317550B2 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6414497B2 (ja) * 2015-03-25 2018-10-31 アイシン・エィ・ダブリュ株式会社 メモリコントローラ
US11487316B2 (en) * 2018-10-24 2022-11-01 Magic Leap, Inc. Asynchronous ASIC
JP7418159B2 (ja) * 2019-04-19 2024-01-19 キヤノン株式会社 情報処理装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188516A (ja) * 1986-02-14 1987-08-18 Nec Corp 遅延回路
JPH10124168A (ja) * 1996-10-18 1998-05-15 Nkk Corp 可変クロック動作システム
JP2002108493A (ja) * 2000-09-29 2002-04-10 Fujitsu General Ltd クロック位相シフト回路
US7706484B2 (en) * 2006-06-22 2010-04-27 International Business Machines Corporation Coherent frequency clock generation and spectrum management with non-coherent phase
WO2010050098A1 (ja) * 2008-10-29 2010-05-06 日本電気株式会社 クロック分周回路、クロック分配回路、クロック分周方法及びクロック分配方法

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