JP2015015412A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit occurrence of malfunction on a semiconductor device based on a temperature change.SOLUTION: A semiconductor device 1 is formed in a manner such that each of semiconductor elements 20, 21 has a flexural strength of not less than 100 MPa and not more than 1000 MPa, preferably not less than 400 MPa and not more than 800 MPa. Accordingly, even when an underfill material 40 for encapsulating the semiconductor device 1 deforms by a temperature change caused by heat generation and the like at the time of operation of the semiconductor elements 20, 21 and a temperature change in the external environment of the semiconductor device 1, a stress on a lower region of post electrodes 30e arranged on electrodes of the semiconductor elements 20, 21 is reduced.

Description

  The present invention relates to a semiconductor device.

In an inverter device, an uninterruptible power supply device, a machine tool, an industrial robot, and the like, a semiconductor device (general-purpose module) is used independently of the main body device.
In such a semiconductor device, for example, a power semiconductor element is disposed on an insulating substrate via a solder material, and a flexible printed circuit board on which a post electrode is formed is disposed on the power semiconductor element. Each post electrode is electrically joined to a predetermined electrode of the element by solder (joining material). The semiconductor device is further configured by sealing an insulating substrate on which power semiconductor elements are arranged and a flexible printed circuit board with a resin (for example, see Patent Document 1).

JP 2009-64852 A

  However, in such a semiconductor device, stress is generated inside the semiconductor device when the temperature change due to heat generation during operation of the semiconductor element and the temperature change of the external environment occur and the resin sealing the semiconductor device is deformed. To do. Specifically, when excessive compressive stress is generated on the surface of the semiconductor element inside the semiconductor device, the electrode of the semiconductor element and the surface of the semiconductor element may be damaged, and the semiconductor device may fail.

  The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of a failure based on a temperature change in the semiconductor device.

  In the present invention, in order to solve the above problem, an insulating substrate, a semiconductor element disposed on the main surface of the insulating substrate and having a bending strength of 100 MPa or more and 1000 MPa or less, and opposed to the main surface of the insulating substrate. A plurality of post electrodes that electrically connect at least one of the metal foils formed on the main surface of the printed circuit board and at least one of the electrodes of the semiconductor element, and the insulating substrate. And a sealing resin that seals a gap between the printed circuit board and the printed circuit board.

  According to such a semiconductor device, it is possible to suppress a decrease in reliability even when a temperature change occurs in the semiconductor device.

1 is a diagram illustrating an example of a semiconductor device in an embodiment. It is a figure which shows an example of the connection structure of the post electrode and semiconductor element of the semiconductor device in embodiment. It is a figure which shows an example of the printed circuit board with which the semiconductor device in embodiment is provided. It is a figure which shows the test result of the three-point bending test of the semiconductor element in embodiment. It is a figure which shows the test result of the three-point bending test with respect to the thickness of the semiconductor element in embodiment. It is a figure which shows an example of the principal part of the semiconductor device which a failure generate | occur | produced.

Hereinafter, embodiments will be described with reference to the drawings.
The semiconductor device in the embodiment includes an insulating substrate on which a semiconductor element is disposed on a main surface, a printed circuit board that is disposed so as to face the main surface on which the semiconductor element of the insulating substrate is disposed, and a main surface of the printed circuit board. A plurality of post electrodes that electrically connect at least one of the formed metal foils and at least one of the electrodes of the semiconductor element, and a sealing resin that seals a gap between the insulating substrate and the printed board.

  In the semiconductor device, the semiconductor element further has a bending strength of 100 MPa or more and 1000 MPa or less. For this reason, the semiconductor element of the semiconductor device relaxes the compressive stress generated in the semiconductor device in accordance with the deformation of the sealing resin due to the external environment temperature and the temperature change due to heat generation during the operation of the semiconductor element, and is generated in the semiconductor element. Damage can be suppressed.

Hereinafter, such a semiconductor device will be specifically described with reference to FIG.
FIG. 1 illustrates an example of a semiconductor device in an embodiment.
1A illustrates a top surface of a principal portion of the semiconductor device, and FIG. 1B illustrates a cross-sectional view of the principal portion of the semiconductor device taken along one-dot chain line AB in FIG. 1A.

  The illustrated semiconductor device 1 has a structure in which an insulating substrate 10 and a printed circuit board 30 facing the insulating substrate 10 are integrated by sealing with an underfill material 40 (sealing resin). A plurality of semiconductor elements 20 and 21 are mounted on the top. Further, the semiconductor device 1 is packaged by a resin case (not shown) and functions as a general-purpose module.

  The insulating substrate 10 includes an insulating plate 10a, a metal foil 10b formed by a DCB (Direct Copper Bonding) method on the lower surface of the insulating plate 10a, and a plurality of metal foils also formed on the upper surface of the insulating plate 10a by the DCB method. 10c, 10d. These metal foils 10c and 10d are selectively patterned on the upper surface of the insulating plate 10a.

  Further, on the metal foils 10c and 10d, the main electrode side (for example, collector) of at least one semiconductor element 20 is disposed via a lead (Pb) -free solder layer 11 such as tin (Sn) -silver (Ag). Electrode) or the cathode electrode of the semiconductor element 21 is joined.

  Here, for example, a vertical power semiconductor element such as an IGBT element or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be applied to the semiconductor element 20. For example, a power diode element such as an SBD (Schottky Barrier Diode) or an FWD (Free Wheeling Diode) element can be applied to the semiconductor element 21.

  Furthermore, the bending strength of the semiconductor element 20 is 100 MPa or more and 1000 MPa or less, preferably 400 MPa or more and 800 MPa or less. For example, silicon (Si) or silicon carbide (SiC) is used.

The insulating plate 10a is made of ceramic such as alumina (Al ₂ O ₃ ) sintered body, silicon nitride (Si ₃ N ₄ ), and the metal foils 10b, 10c, and 10d are mainly made of copper (Cu). It is composed of metal as a component.

In the semiconductor device 1, the implant printed circuit board (printed circuit board) 30 is disposed above the semiconductor elements 20 and 21 so as to face the insulating substrate 10.
The printed circuit board 30 has a multilayer structure, for example, a resin layer 30a is disposed at the center, and at least one metal foil 30b is selectively patterned on the upper surface thereof. Further, at least one metal foil 30c is selectively patterned on the lower surface.

  Here, the material of the resin layer 30a is, for example, a polyimide resin, an epoxy resin, or the like. Moreover, what impregnated the inside of the resin layer 30a with the glass cloth comprised by glass fiber as needed can also be applied. In addition, the metal foils 30b and 30c are configured with, for example, copper as a main component.

The rigidity of the printed circuit board 30 may be a hard type having a predetermined rigidity, or may be flexible so that the entire printed circuit board 30 can be distorted.
A resin protective layer 31 is formed on the outermost surface of the printed circuit board 30.

  In the semiconductor device 1, a plurality of through holes 30 d are provided on the printed circuit board 30 immediately above the region where the main electrode (for example, emitter electrode) of the semiconductor element 20 is located so as to be approximately line symmetric. A thin cylindrical plating layer (not shown) is provided in the through hole 30d, and a cylindrical post electrode 30e is injected (implanted) through the cylindrical plating layer in the through hole 30d. .

  Each post electrode 30e is soldered in the through hole 30d and is electrically connected to the metal foils 30b and 30c disposed on the main surface of the printed circuit board 30. In the case where the metal foils 30b and 30c are disposed on both surfaces of the printed circuit board 30, the post electrode 30e is injected through the cylindrical plating layer and soldered in this manner, so that a good electrical connection can be obtained. Mechanical strength can be ensured. Note that when a relatively thick metal foil 30c is formed on one surface of the printed circuit board 30 and the post electrode 30e is injected, the cylindrical plating layer or soldering may be omitted.

  Here, in the arrangement of the post electrodes 30e, for example, immediately after the emitter electrode (not shown, metal plating) region of the semiconductor element 20, a group of five post electrodes 30e constitutes a row, and these are the lines. They are arranged in two rows so as to be symmetrical. The pitch of the post electrodes 30e is configured to be uniform. In addition, the lower end of each post electrode 30 e is electrically connected to the emitter electrode of the semiconductor element 20 via the solder layer 12.

  Further, immediately after the anode side region of the semiconductor element 21, a set of four post electrodes 30e form a row and are arranged in two rows so that they are line symmetric. The pitch of the post electrodes 30e is configured to be uniform. In addition, the lower end of each post electrode 30e is electrically connected to the anode side of the semiconductor element 21 via a solder layer.

  Thereby, in the semiconductor device 1, electrical connection between the emitter electrode of the semiconductor element 20 and the anode side of the semiconductor element 21 is ensured via the post electrode 30e and the metal foil 30b.

The electrical connection between the collector electrode of the semiconductor element 20 and the cathode side of the semiconductor element 21 is ensured via the metal foils 10c and 10d.
The material of the post electrode 30e is, for example, gold (Au), copper, or an alloy made of these metals having a linear expansion coefficient of 14 × 10 ⁻⁶ / K or more and 17 × 10 ⁻⁶ / K or less. Is the main component. The length of each post electrode 30e is uniform.

  In the above example, the number of post electrodes 30e bonded to the emitter electrode of the semiconductor element 20 is limited to ten. However, the number of post electrodes 30e bonded to one semiconductor element 20 is set to this number. It is not limited. For example, when the diameter of the post electrode 30e is 0.3 to 0.6 mm, a current of 8 to 20 A can be applied to one post electrode 30e. Therefore, the number of post electrodes 30e to be joined to the semiconductor element 20 may be determined from the current value according to the capacity of the semiconductor element 20 and arranged in that number.

  Due to the arrangement of the plurality of post electrodes 30e, for example, in the semiconductor element 20, even when a large current is passed between the main electrodes, the large current is distributed to the main electrodes via the respective post electrodes 30e.・ Energize.

  Further, in the printed circuit board 30, a through hole 30f is separately provided above the outside of the emitter electrode region of the semiconductor element 20, and a cylindrical post electrode 30g is injected and joined also into the through hole 30f. . The post electrode 30g is electrically connected to a control electrode (for example, a gate electrode) of the semiconductor element 20 via a solder layer.

Thus, the main electrode or control electrode arranged on the main surface of the semiconductor element 20 and the anode side of the semiconductor element 21 are joined to the post electrodes 30e and 30g.
The structure of the post electrodes 30e and 30g described above is not limited to a rod shape, and may be a pipe shape having a hollow inside.

  Furthermore, in the semiconductor device 1, the underfill material 40 is filled in the gap between the insulating substrate 10 and the printed circuit board 30. Thereby, the semiconductor device 1 is integrated by the insulating substrate 10 and the printed circuit board 30. Details of the underfill material 40 will be described with reference to FIG.

  In addition, the semiconductor device 1 includes a resin case (not shown) made of, for example, PPS (polyphenylene sulfide) so as to surround the insulating substrate 10 sealed with the underfill material 40, the printed circuit board 30, and the like. It has been.

  Alternatively, without using a resin case (not shown), an epoxy resin may be potted or transfer molded so as to surround the semiconductor device 1 using a metal mold (not shown).

  Further, although not particularly shown in FIG. 1, a plurality of lead frames as external connection terminals penetrate vertically through the printed circuit board 30, and these are connected to the respective electrodes of the semiconductor elements 20 and 21. Electrical connection is ensured. Although not particularly shown in FIG. 1, a metal base plate having a larger area than the insulating substrate 10 may be used as the base of the semiconductor device 1. For example, a metal base plate having a thickness of several millimeters may be bonded under the metal foil 10b via a solder layer. Moreover, a heat spreader known as a heat radiator may be installed on the semiconductor elements 20 and 21.

Next, details of the connection structure between the post electrode 30e of the semiconductor device 1 and the semiconductor elements 20 and 21 will be described with reference to FIG.
FIG. 2 is a diagram illustrating an example of a connection structure between a post electrode and a semiconductor element of the semiconductor device according to the embodiment.

2 shows an enlarged view of the periphery of the post electrode 30e disposed in the semiconductor device 1 of FIG. 1 and the semiconductor element 20 joined to the post electrode 30e.
As described above, in the semiconductor device 1, the main electrode (collector electrode) of the semiconductor element 20 is joined to the metal foil 10 d via the solder layer 11.

  A printed circuit board 30 is disposed above the semiconductor element 20, and a plurality of through holes 30 d are formed in the printed circuit board 30. A cylindrical plating layer 30h made of, for example, copper is disposed on the inner wall of the through hole 30d.

  Also, patterned metal foils 30 b and 30 c are disposed on the upper and lower main surfaces of the printed circuit board 30. These metal foils 30b and 30c are covered with a cylindrical plating layer 30h and are electrically connected to the cylindrical plating layer 30h.

  Further, the post electrode 30e described above is injected halfway into the cylindrical plating layer 30h, and is fixed to the cylindrical plating layer 30h by the solder layer 30i. Thereby, the electrical connection between the post electrode 30e and the metal foils 30b and 30c and the mechanical strength at the joint are ensured.

  Further, the lower ends of the plurality of post electrodes 30 e are electrically connected to another main electrode (emitter electrode) of the semiconductor element 20 via the solder layer 12. Thereby, for example, when the control electrode of the semiconductor element 20 is in an on state and the emitter-collector electrode of the semiconductor element 20 is energized, the post electrodes 30e are respectively interposed between the metal foils 30b and 30c and the metal foil 10d. Large current is energized.

Note that the side surface of the solder layer 12 forms a fillet structure, and the bonding between the lower end of the post electrode 30 e and the main electrode of the semiconductor element 20 is strengthened.
Further, in the semiconductor device 1, an underfill material 40 is filled in a gap between the printed circuit board 30 and the insulating substrate 10. The underfill material 40 has a linear expansion coefficient of 10 × 10 ⁻⁶ / K or more and 80 × 10 ⁻⁶ / K or less, for example, an epoxy resin as a main component, and its curing temperature is about 180 degrees. And contains a filler material composed of an inorganic material. As the filler material, for example, an inorganic material having high thermal conductivity such as boron nitride (BN), aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ) or the like is used.

Next, the printed circuit board 30 disposed above the semiconductor elements 20 and 21 will be described in detail.
FIG. 3 is a diagram illustrating an example of a printed board included in the semiconductor device according to the embodiment.
3A is a rear view of the main part of the printed circuit board (the main surface of the printed circuit board viewed from the insulating substrate 10 side shown in FIG. 1), and FIG. 3B is A of FIG. 3A. The principal part sectional drawing of the printed circuit board in -B is shown, respectively.

  As an example, the printed circuit board 30 has a structure corresponding to a semiconductor device (6-in-1 structure) in which six sets of IGBT and FWD parallel connection circuits constituting an inverter circuit are stored in one package.

  As described above, a plurality of metal foils 30 c and 30 j are patterned on any main surface of the resin layer 30 a constituting the printed circuit board 30. Further, a protective layer 31 is formed on the resin layer 30a and the metal foils 30c and 30j. In FIG. 3A, the protective layer 31 formed on the outermost surface of the printed board 30 is not shown in order to clearly show the pattern shape of the metal foils 30c and 30j.

  Such metal foils 30 c and 30 j are arranged so that a part thereof is located on the emitter electrode of the semiconductor element 20 and the region on the anode side of the semiconductor element 21. A plurality of post electrodes 30 e are arranged on the printed circuit board 30.

  For example, in the metal foils 30c and 30j located immediately above the emitter electrode of the semiconductor element 20 and the anode side region of the semiconductor element 21, a plurality of post electrodes 30e are arranged in line symmetry.

  Specifically, the metal foils 30c and 30j on the emitter electrode region of the semiconductor element 20 are arranged in groups of five, and two sets of post electrodes 30e are arranged in two rows in line symmetry. Accordingly, a total of ten post electrodes 30 e are arranged on the metal foils 30 c and 30 j on the emitter electrode region of the semiconductor element 20.

  The metal foils 30c and 30j on the anode side region of the semiconductor element 21 are arranged in groups of four, and two sets of post electrodes are arranged in two rows in line symmetry. Accordingly, a total of eight post electrodes 30 e are arranged on the metal foils 30 c and 30 j on the anode side region of the semiconductor element 21.

Note that the pitch of the post electrodes 30e arranged in the same row is uniform.
In the above example, specific numerical values are exemplified for the number of post electrodes 30e. However, as described above, the number of post electrodes 30e bonded to each of the semiconductor elements 20 and 21 is limited to this number. Is not to be done.

  Further, in addition to the above-described metal foils 30c and 30j, the metal foils 30k and 30l having a narrow line width are patterned on the printed board 30, and a part thereof is a region of a control electrode (for example, a gate electrode) of the semiconductor element 20. It arrange | positions so that it may be located on. Further, a post electrode 30g is disposed in the metal foils 30k and 30l located on the control electrode region of the semiconductor element 20.

  Further, as shown in this figure, the metal foils 30ja, 30jb, and 30jc are extended from the metal foil 30j to a wide area of the printed circuit board 30 other than immediately above the semiconductor element 20 and 21 mounting area. As described above, the metal foil 30j is electrically connected to the emitter electrode or the anode side of the semiconductor elements 20 and 21.

  When such metal foils 30ja, 30jb, and 30jc are present in the printed circuit board 30, electromagnetic shielding is promoted, and noise during operation of the semiconductor device 1 (for example, radiation noise generated by switching of the semiconductor element 20). Can be reduced. That is, the metal foils 30ja, 30jb, and 30jc function as metal foils for electromagnetic shielding.

  For example, when the printed circuit board 30 on which the metal foils 30ja, 30jb, and 30jc are patterned is mounted on the semiconductor device 1 as compared with a printed circuit board that does not include the metal foils 30ja, 30jb, and 30jc, the radiation noise has a predetermined frequency. It is reduced by 5 dB in the band.

Note that the metal foils 30ja, 30jb, and 30jc may be selectively disposed not only on the back surface of the printed board 30 but also on the main surface side.
Further, a plurality of through holes 32 are formed outside the region where the metal foils 30c, 30ja, 30jb, 30jc, 30k, 30l are formed. These through holes 32 are injection ports for allowing the underfill material 40 shown in FIG. 2 to flow into the gap between the insulating substrate 10 and the printed circuit board 30. By providing a plurality of such injection ports in the printed circuit board 30, the paste-like underfill material can smoothly flow into the gap between the printed circuit board 30 and the insulating substrate 10. As a result, after the underfill material that has flowed into the gap is cured, the underfill material 40 is placed in the gap between the insulating substrate 10 and the printed board 30 without any voids remaining inside the underfill material 40. It can be filled tightly.

The bending strength of the semiconductor element 20 (and the semiconductor element 21) of the semiconductor device 1 having such a configuration will be described.
First, a stress distribution simulation performed on the semiconductor device 1 will be described.

  In this simulation, the semiconductor element in the semiconductor device 1 when the temperature cycle in which the external environment temperature of the semiconductor device 1 is changed from 180 degrees to −200 degrees through − (minus) 40 degrees by two cycles is performed by the finite element method. The result of the stress distribution at 20 can be obtained.

  As the semiconductor elements 20 and 21, the semiconductor device 1 to be simulated includes a MOSFET using silicon, an FWD using silicon, a MOSFET using silicon carbide, and an SBD using silicon carbide, respectively. It shall be.

  As a result, the Young's modulus indicating the element strength of the semiconductor elements 20 and 21 was 112700 MPa when silicon was used, and 441000 MPa when silicon carbide was used. According to the simulation result of the stress distribution, it was found that the stress on each of the semiconductor elements 20 and 21 is lower in the case of MOSFET and FWD using silicon than in the case of MOSFET and SBD using silicon carbide. Based on these results, it can be considered that the semiconductor elements 20 and 21 have lower (or higher) stress as the element strength is lower (or higher).

Next, the results of a three-point bending strength test performed on the semiconductor elements 20 and 21 provided in the semiconductor device 1 will be described with reference to FIG.
FIG. 4 is a diagram showing a test result of a three-point bending test of a semiconductor element in the embodiment.

  In the three-point bending strength test shown in FIG. 4, the semiconductor elements 20 and 21 are MOSFETs (A) using silicon, MOSFETs (B to D) using silicon carbide, and SBDs using silicon carbide. (E) was the test subject. In FIG. 4, the vertical axis indicates the type of the semiconductor element 20 to be tested, and the horizontal axis indicates the bending strength (MPa) obtained by the three-point bending test. The range of bending strength in which the results are included is shown.

  According to the test results shown in FIG. 4, the bending strength of the semiconductor element 20 (MOSFET using silicon carbide) in (B) is in the range of about 1900 MPa or more and about 2800 MPa or less. Further, the bending strength of the semiconductor elements 20 and 21 of (A), (C) to (E) is 1000 MPa or less, and in particular, the bending strength of the semiconductor elements 20 and 21 of (C) to (E) related to silicon carbide. The strength is 400 MPa or more and 800 MPa or less. The semiconductor element (A) related to silicon will be described later.

  The bending strength of the semiconductor elements 20 and 21 is changed according to the material and direction of the growth surface of the crystal growth of the substrate of the semiconductor elements 20 and 21 in the manufacturing process, the thickness of the semiconductor elements 20 and 21, and the like. be able to.

Therefore, as an example, the bending strength with respect to the thickness of the semiconductor element 20 (MOSFET using silicon) of (A) will be described with reference to FIG.
FIG. 5 is a diagram showing a test result of a three-point bending test with respect to the thickness of the semiconductor element in the embodiment.

In FIG. 5, the horizontal axis represents the element thickness (μm), and the vertical axis represents the bending strength (MPa).
It can be seen that the bending strength of the semiconductor element 20 of (A) increases in proportion to its thickness, as shown in FIG. According to FIG. 5, the bending strength can be set to about 900 MPa by setting the element thickness to 500 μm.

  Further, the element thickness can be reduced to about 100 μm in consideration of the manufacturing limit of the semiconductor element 20 and the ease of handling of the semiconductor element 20. By setting the element thickness to about 100 μm, the bending strength can be set to about 100 MPa. That is, it can be considered that the bending strength of the semiconductor element 20 of (A) is 100 MPa or more and 900 MPa.

  In view of the description of FIGS. 4 and 5 and the description thereof, the bending strength of the semiconductor elements 20 and 21 is 100 MPa or more and 1000 MPa or less, and preferably 400 MPa or more and 800 MPa or less. .

Next, a heat cycle test performed on the semiconductor elements 20 and 21 of (A) to (E) will be described.
The heat cycle test is performed when a predetermined voltage is applied to the semiconductor device 1 for each temperature cycle in which the external environmental temperature of the semiconductor device 1 is changed from − (minus) 40 degrees to 150 degrees through − (minus) 40 degrees again. Is measured for 500 cycles.

  According to this test result, the semiconductor elements 20 and 21 of (A), (C) to (E) shown in FIG. 4, that is, the semiconductor elements 20 and 21 having a bending strength of 100 MPa or more and 1000 MPa or less are semiconductor elements. There was no significant variation in the 20 properties. Therefore, no defects are observed in the semiconductor elements 20 and 21 of (A) and (C) to (E), and the semiconductor device includes the semiconductor elements 20 and 21 of (A) and (C) to (E). 1 may be that no failure occurred.

  On the other hand, in the semiconductor element 20 of FIG. 4 (B), the leakage current increases in about 50 cycles, and the semiconductor device 1 including the semiconductor element 20 of (B) has failed. Conceivable.

Hereinafter, a failure of the semiconductor device 1 including the semiconductor element 20 of (B) caused by the heat cycle test will be described with reference to FIG.
FIG. 6 is a diagram illustrating an example of a main part of a semiconductor device in which a failure has occurred.

FIG. 6 shows a further enlarged view of the periphery of the post electrode 30e disposed in the semiconductor device 1 of FIG. 2 and the semiconductor element 20 joined to the post electrode 30e.
In the semiconductor device 1, the metal plating 20 b mainly composed of nickel (Ni) or the like is formed on the emitter electrode 20 a mainly composed of aluminum (Al) or the like of the semiconductor element 20 having a bending strength exceeding 1000 MPa (B). ing.

  The post electrode 30 e is disposed immediately above the emitter electrode 20 a and the metal plating 20 b of the semiconductor element 20, and is electrically connected to the emitter electrode 20 a through the solder layer 12. In FIG. 6, the underfill material 40 is filled in a gap between the printed board 30 and the insulating board 10 (not shown), so that the semiconductor element 20, the post electrode 30 e, and the solder layer 12 are sealed.

  In such a semiconductor device 1, when the external environmental temperature rises, the underfill material 40 is deformed and stress is generated inside the semiconductor device 1. In particular, the post electrode 30e also has a difference in linear expansion coefficient from the underfill material 40, and stress concentrates on the lower portion (in the vicinity of the range X in FIG. 6) to damage the emitter electrode 20a and the metal plating 20b. For this reason, a voltage is not appropriately applied to the semiconductor element 20 from the post electrode 30e via the emitter electrode 20a and the metal plating 20b, and the function of the semiconductor element 20 is deteriorated. If stress is further concentrated on the lower portion of the post electrode 30e, the semiconductor element 20 is cracked Y, and the semiconductor device 1 is broken.

  On the other hand, since the semiconductor elements 20 and 21 of (A), (C) to (E) have a bending strength of 1000 MPa or less and are smaller than the semiconductor element 20 of (B), they are formed below the post electrode 30e. Even if the stress is concentrated, the stress can be relaxed. For this reason, it is possible to suppress the occurrence of damage in the lower part of the post electrode 30e (in the vicinity of the range X in FIG. 6) and to suppress the occurrence of a failure of the semiconductor device 1.

  As described above, the semiconductor device 1 includes the insulating substrate 10 on which the semiconductor elements 20 and 21 are arranged on the main surface and the print arranged on the insulating substrate 10 so as to face the main surface on which the semiconductor elements 20 and 21 are arranged. A plurality of post electrodes 30e that electrically connect the substrate 30, at least one of the metal foils formed on the main surface of the printed circuit board 30 and at least one of the electrodes of the semiconductor elements 20, 21, the insulating substrate 10 and the printed circuit board; And an underfill material 40 that seals the gap between the semiconductor element 20 and the semiconductor element 20 and 21 and has a bending strength of 100 MPa or more and 1000 MPa or less, preferably 400 MPa or more and 800 MPa or less.

  Thereby, even if the underfill material 40 that seals the semiconductor device 1 is deformed due to a temperature change due to heat generation or the like during operation of the semiconductor elements 20 and 21 and a temperature change in the external environment of the semiconductor device 1, the semiconductor element 20 or 21 The stress on the lower region of the post electrode 30e disposed on the electrode 21 is relieved. For this reason, in the semiconductor device 1, the occurrence of damage to the lower region of the post electrode 30e is suppressed, and the occurrence of a failure in the semiconductor device 1 can be suppressed.

  From the above results, the semiconductor device 1 has high reliability and good operating characteristics. In addition, the power cycle tolerance of the semiconductor device 1 is further improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Insulating substrate 10a Insulating plate 10b, 10c, 10d, 30b, 30c, 30j, 30ja, 30jb, 30jc, 30k, 30l Metal foil 30e, 30g Post electrode 11, 12, 30i Solder layer 20a Emitter electrode 20, 21 Semiconductor element 30 Printed circuit board 30a Resin layer 30d, 30f Through hole 30h Cylindrical plating layer 31 Protective layer 32 Through hole 40 Underfill material

Claims (5)

An insulating substrate;
A semiconductor element having a bending strength of 100 MPa or more and 1000 MPa or less, disposed on the main surface of the insulating substrate;
A printed circuit board disposed to face the main surface of the insulating substrate;
A plurality of post electrodes that electrically connect at least one of the metal foils formed on the main surface of the printed circuit board and at least one of the electrodes of the semiconductor element;
A sealing resin for sealing a gap between the insulating substrate and the printed board;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the bending strength of the semiconductor element is 400 MPa or more and 800 MPa or less.   2. The semiconductor device according to claim 1, wherein the semiconductor element is made of silicon carbide or silicon.   The semiconductor device according to claim 1, wherein the post electrode is made of copper.   The semiconductor device according to claim 1, wherein the sealing resin has a linear expansion coefficient of 10 × 10 −6 / K or more and 80 × 10 −6 / K or less.

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